DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
For clarity, references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and examiner explanations for 102 and/or 103 rejections are provided in parenthesis.
Election/Restrictions
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on April 24th, 2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 4 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
In claim 1, applicant recites a method step wherein “the first layers” are removed to form wordline openings in the film stack. In claim 4 (dependent on claim 1 via claims 2-3), applicant recites that “the first layers” are silicon oxide. However, in paragraph [0043] and fig. 8 of the instant disclosure, applicant discloses a method step wherein the second layers 108A-D are removed to form wordline openings 150. In paragraph [0035], applicant discloses that first layers 106 may be silicon oxide (SiO) and that second layers 108 may be silicon nitride (SiN). Therefore, applicant discloses that the silicon nitride layers are removed from the film stack to form wordline contacts, yet this conflicts with the recited subject matter of claim 4 in light of the subject matter of independent claim 1. As such, applicant has failed to particularly point out and distinctly claim the subject matter which the inventive entity regards as the invention in claim 4. To overcome this rejection, applicant should clarify which layer(s) of the film stack are removed to form wordline openings—the silicon oxide layer(s) or the silicon nitride layer(s). For the purpose of continued examination, Examiner will examine claim 1 as if applicant had recited “removing the second layers to form a plurality of wordline openings in the film stack” such that claim 4 becomes consistent with applicant’s disclosure.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5, and 7, are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Komukai et al. (US 20230307287 A1), hereinafter referred to as “Komukai”.
Regarding claim 1 (applicant is reminded of the above 112(a) rejection of claim 4), Komukai discloses a method (see figs. 4-15 and [0042]), comprising:
providing a film stack (fig. 4, 3-1 through 3-13 and 2-1 through 2-12; see [0043]: layers 3-1 through 3-13 are collectively referred to as insulating layers 30, and layers 2-1 through 2-12 are collectively referred to as sacrificial layers 20) including a plurality of alternating first layers (fig. 4, 3-1 through 3-13 (i.e. 30)) and second layers (fig. 4, 2-1 through 2-12 (i.e. 20));
forming a plurality of contact openings (fig. 11, CH1b-12b; c.f. figs. 4-10; see [0053]) in the film stack, wherein each contact opening of the plurality of contact openings is formed to a different etch depth relative to an upper surface of the film stack (see fig. 11);
depositing a liner (fig. 12, 60; see [0058]) over the film stack including within each contact opening of the plurality of contact openings (see fig. 12);
removing the second layers (compare figs. 13 and 14; see [0060]: sacrificial layers 20 are removed to form cavities where conductive layers 70 are subsequently formed; see [0038]: conductive layers 7-1 through 7-12 are collectively referred to as conductive layers 70) to form a plurality of wordline openings (see [0060]) in the film stack;
forming a plurality of wordlines (fig. 14, 7-1 through 7-12 (i.e. 70); c.f. fig. 3; see [0034]) by depositing a first conductive material (see [0039]: the first conductive material of conductive layers 70 is tungsten; also see [0060]) within the plurality of wordline openings;
removing the liner from a bottom of each contact opening of the plurality of contact openings (see fig. 15 and [0061]);
and depositing a second conductive material (see [0062]: the second conductive material used to create contact plugs 50 is tungsten; see [0040]) within the plurality of contact openings to form a plurality of wordline contacts (fig. 3, 5-1 through 5-12 (i.e. 50); see [0040] and [0062]).
Regarding claim 5, Komukai discloses the method of claim 1, wherein the first layers (fig. 4, 3-1 through 3-13 (i.e. 30)) of the plurality of alternating first layers and second layers are a dielectric material (see [0039]: insulating layers 30 are silicon oxide),
and wherein the second layers (fig. 4, 2-1 through 2-12 (i.e. 20)) of the plurality of alternating first layers and second layers are a dielectric material or a conductive material (see [0043]: sacrificial layers 20 are silicon nitride).
Regarding claim 7, Komukai discloses the method of claim 1, wherein the liner (fig. 12, 60; see [0058]) is removed from the bottom of each contact opening of the plurality of contact openings (fig. 15, CH1-12) without removing the liner from a sidewall of each contact opening of the plurality of contact openings (see fig. 15 and [0061]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4 are rejected under 35 U.S.C. 103 as being obvious over Komukai, in view of Izumi et al. (US 20160093524 A1), hereinafter referred to as “Izumi”.
Regarding claim 2, Komukai discloses the method of claim 1,
Komukai fails to explicitly disclose wherein forming the plurality of contact openings in the film stack comprises: patterning a first set of openings through a first masking layer; etching, through the first set of openings, a first set of 3 of the plurality of contact openings; patterning a second set of openings through a second masking layer, wherein one opening of the second set of openings is aligned with one contact opening of the first set of contact openings; etching, through the second set of openings, a second set of contact openings of the plurality of contact openings; patterning a third set of openings through a third masking layer, wherein the third masking layer is formed over the first and second sets of contact openings; and etching, through the third set of openings, a third set of contact openings of the plurality of contact openings.
Izumi discloses a method for forming NAND memory devices (see Izumi [0006]) wherein forming a plurality of contact openings (Izumi fig. 10, 69A-F) in a film stack (Izumi fig. 2, 32T-F and 42A-F (alternating stack (32, 42)); see [0021]-[0023]) comprises:
patterning a first set of openings (Izumi fig. 3: 49D and 49F; see [0051]) through a first masking layer (Izumi fig. 3, 45; see [0050]);
etching, through the first set of openings, a first set of contact openings (Izumi fig. 3: 69D and 69F; see [0053]) of the plurality of contact openings;
patterning a second set of openings (Izumi fig. 5: 49’D and 49’E; see [0057]) through a second masking layer (Izumi fig. 5, 45’; see [0055]-[0056]), wherein one opening of the second set of openings (Izumi fig. 5, 49’D) is aligned with one contact opening of the first set of contact openings (Izumi fig. 3, 69D; c.f. fig. 5; mask opening 49’D is aligned with contact opening 69D initially formed with the first set of contact openings);
etching, through the second set of openings, a second set of contact openings (Izumi fig. 6: 69D and 69E; see [0059]) of the plurality of contact openings;
patterning a third set of openings (Izumi fig. 8: 49’’A, 49’’B, 49’’C; see [0065]) through a third masking layer (Izumi fig. 8, 45’’; see [0063]-[0064]), wherein the third masking layer is formed over the first and second sets of contact openings (see Izumi fig. 8; c.f. figs. 3 and 6);
and etching, through the third set of openings, a third set of contact openings (Izumi fig. 9: 69A, 69B, 69C; see [0067]) of the plurality of contact openings.
The contact opening formation method of Izumi is incorporated as the contact opening formation method step of the method of Komukai wherein the combination discloses all of the limitations of claim 2.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Komukai with the contact opening formation method of Izumi to reduce processing complexity (e.g. see Izumi [0011]).
Regarding claim 3, Komukai and Izumi disclose the method of claim 2, wherein a first depth of the first set of contact openings (Izumi fig. 3, 69D and 69F; c.f. fig. 10) is less than a second depth of the second set of contact openings (Izumi fig. 6, 69D and 69E; c.f. fig. 10),
and wherein the second depth of the second set of contact openings (Izumi fig. 6, 69D and 69E; c.f. fig. 10) is less than a third depth of the third set of contact openings (Izumi fig. 9: 69A, 69B, 69C; c.f. fig. 10).
Regarding claim 4, Komukai and Izumi disclose the method of claim 3, wherein the first layers (Komukai fig. 4, 3-1 through 3-13 (i.e. 30)) of the plurality of alternating first layers and second layers are silicon oxide (see [0039]: insulating layers 30 are silicon oxide),
and wherein the second layers (Komukai fig. 4, 2-1 through 2-12 (i.e. 20)) of the plurality of alternating first layers and second layers are silicon nitride (see [0043]: sacrificial layers 20 are silicon nitride).
Claim 6 is rejected under 35 U.S.C. 103 as being obvious over Komukai, in view of Izumi et al. (US 20160307912 A1), hereinafter referred to as “Izumi2”.
Komukai discloses the method of claim 1.
Komukai fails to disclose wherein removing the liner from the bottom of each contact opening of the plurality of contact openings exposes an upper surface of one or more of the plurality of wordlines.
Izumi2 discloses a method for fabricating NAND memory devices (see Izumi2 [0011]) wherein removing a liner (Izumi2 fig. 18, 65; see [0110]: contiguous material layer 65 acts as a liner (“encapsulating liner portions”) disposed within contact openings 69; see figs. 22-23 and [0122]: the contiguous material layer 65 includes the same material as insulating liners 64, and the bottom portions of the contiguous material layer 65 in each contact opening 69 are removed to expose the top surfaces of corresponding conductive electrodes 46) from the bottom of each contact opening of a plurality of contact openings (Izumi2 fig. 23, 69) exposes an upper surface of one or more of a plurality of wordlines (Izumi2 fig. 23, 46; see [0120] and [0126]).
The wordline exposure technique of Izumi2 is incorporated as the wordline exposure technique of the method of Komukai wherein the combination discloses wherein removing the liner from the bottom of each contact opening of the plurality of contact openings exposes an upper surface of one or more of the plurality of wordlines.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Komukai with the liner removal teachings of Izumi2 because the combination is a simple substitution one known method step for another to obtain predictable results—simple substitution of the wordline exposure technique of Komukai (see Komukai fig. 15 and [0061]: contact holes CH1-12 are formed to be in contact with underlying insulating layers 30, and, in a subsequent step, both insulating film 60 on the bottom of the contact holes CH along with the underlying portions of the respective insulating layers 30 are etched to expose the respective conductive layer 70) with the wordline exposure technique of Izumi2 (see Izumi2 figs. 22 and 23 and [0122]: contiguous material layer 65 (i.e. liner) is etched to directly expose conductive electrodes 46) to obtain predictable results (i.e. exposing buried wordlines for external connection).
Claim 8 is rejected under 35 U.S.C. 103 as being obvious over Komukai, in view of Lee et al. (US 20150179663 A1), hereinafter referred to as “Lee”.
Komukai discloses the method of claim 1, comprising forming a set of contact holes (Komukai fig. 11, CH1b-12b; c.f. figs. 4-10; see [0053]) in a film stack (Komukai fig. 4, 3-1 through 3-13 and 2-1 through 2-12; see [0043]).
Komukai fails to explicitly disclose the method further comprising forming a second plurality of contact openings in the film stack, wherein each contact opening of the second plurality of contact openings is formed to a different etch depth relative to an upper surface of the film stack, wherein an average diameter of the second plurality of contact openings is greater than an average diameter of the plurality of contact openings, and wherein an average depth of the second plurality of contact openings is greater than an average depth of the plurality of contact openings.
Lee discloses a method for forming muti-level contacts for vertical NAND memory arrays (see Lee [0022] and [0049]; see figs. 10a-h) comprising forming a second plurality of contact openings (see Lee figs. 10a-10h and [0051]-[0052]; Lee discloses forming a plurality of contact openings to expose up to 256 underlying material layers with mutually increasing depth and diameter (see fig. 10h); exemplary contact openings 130A-B as shown in fig. 10g can be labeled as a second plurality of contact openings) in a material layer (Lee fig. 10e, 124; see [0036]),
wherein each contact opening of the second plurality of contact openings is formed to a different etch depth relative to an upper surface of the material layer (see Lee figs. 10g-h and [0051]-[0052]; note that contact openings 130A-E (130C-E are not shown) extend to a depth defined by a respective step 120 underlying a respective opening in mask 300),
wherein an average diameter of the second plurality of contact openings is greater than an average diameter of the plurality of contact openings (see figs. g-h and [0052]: contact openings 130C-E (not shown) are the plurality of contact openings with a diameter defined by the respective openings 304C-E; the average diameter of contact openings 130A-B is larger than the average diameter of contact openings 130C-E (not shown)),
and wherein an average depth of the second plurality of contact openings is greater than an average depth of the plurality of contact openings (see Lee figs. 10g-h and [0051]; the average depth of contact openings 130A-B is larger than the average depth of contact openings 130C-E (not shown)).
The foregoing teachings of Lee are incorporated into the method of Komukai wherein the combination discloses all of the limitations of claim 8.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Komukai with the foregoing teachings of Lee to achieve faster and more evenly distributed etching (see Lee [0051]: since etching proceeds faster in larger diameter openings, the teachings of Lee enable a common etch step that simultaneously forms the plurality of contact openings with more uniformity than the alternative).
Claims 9, 12, and 14, are rejected under 35 U.S.C. 103 as being obvious over Komukai, in view of van Schravendijk et al. (US 20190043876 A1), hereinafter referred to as “vS”.
Regarding claim 9, Komukai discloses forming a film stack (Komukai fig. 4, 3-1 through 3-13 and 2-1 through 2-12; see [0043]: layers 3-1 through 3-13 are collectively referred to as insulating layers 30, and layers 2-1 through 2-12 are collectively referred to as sacrificial layers 20) including a plurality of alternating first layers (Komukai fig. 4, 2-1 through 2-12 (i.e. 20)) and second layers (Komukai fig. 4, 3-1 through 3-13 (i.e. 30));
forming a plurality of contact openings (Komukai fig. 11, CH1b-12b; c.f. figs. 4-10; see [0053]) in the film stack, wherein each contact opening of the plurality of contact openings is formed to a different etch depth relative to an upper surface of the film stack (see Komukai fig. 11);
depositing a liner (Komukai fig. 12, 60; see [0058]) over the film stack including within each contact opening of the plurality of contact openings (see Komukai fig. 12);
removing the first layers (compare Komukai figs. 13 and 14; see [0060]: sacrificial layers 20 are removed to form cavities where conductive layers 70 are later formed; see [0038]: conductive layers 7-1 through 7-12 are collectively referred to as conductive layers 70) to form a plurality of wordline openings (see Komukai [0060]) in the film stack;
forming a plurality of wordlines (Komukai fig. 14, 7-1 through 7-12 (i.e. 70); c.f. fig. 3; see [0034]) by depositing a first conductive material (see Komukai [0039]: the first conductive material of conductive layers 70 is tungsten; also see [0060]) within the plurality of wordline openings;
removing the liner from a bottom of each contact opening of the plurality of contact openings (see Komukai fig. 15 and [0061]);
and depositing a second conductive material (see Komukai [0062]: the second conductive material used to create contact plugs 50 is tungsten; see [0040]) within the plurality of contact openings to form a plurality of wordline contacts (Komukai fig. 3, 5-1 through 5-12 (i.e. 50); see [0040] and [0062]).
Komukai does not disclose a system, comprising: a processor; and a memory storing instructions executable by the processor to implement the foregoing disclosed method.
vS discloses a system (vS fig. 17, 1700; see [0080] and [0087]), comprising: a processor (vS fig. 17, 1752; see [0087]); and a memory (vS fig. 17, 1756; see [0087]) storing instructions executable by the processor to fabricate a 3D NAND structure through various etching and deposition steps (see vS [0003]-[0004] and [0080]-[0081]).
The system of vS is incorporated to implement the method of Komukai wherein the combination discloses all of the limitations of claim 9.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement the method of Komukai with the system of vS to increase process efficiency and reduce the risk of contamination (e.g. see vS [0072])
Regarding claim 12, Komukai and vS disclose the system of claim 9, wherein the instructions executable by the processor (vS fig. 17, 1752; see [0087]) to form the film stack (Komukai fig. 4, 3-1 through 3-13 and 2-1 through 2-12; see [0043]) including a plurality of alternating first layers (Komukai fig. 4, 2-1 through 2-12 (i.e. 20)) and second layers (Komukai fig. 4, 3-1 through 3-13 (i.e. 30)) comprises forming the first layers using a dielectric material (see [0043]: sacrificial layers 20 are silicon nitride), and forming the second layers using a dielectric material or a conductive material (see [0039]: insulating layers 30 are silicon oxide).
Regarding claim 14, Komukai and vS disclose the system of claim 9, wherein the instructions executable by the processor (vS fig. 17, 1752; see [0087]) to remove the liner (Komukai fig. 12, 60; see [0058]) from the bottom of each contact opening of the plurality of contact openings (Komukai fig. 15, CH1-12) further comprises removing the liner from the bottom of each contact opening of the plurality of contact openings without removing the liner from a sidewall of each contact opening of the plurality of contact openings (see Komukai fig. 15 and [0061]).
Claims 10-11 are rejected under 35 U.S.C. 103 as being obvious over Komukai, in view of vS, further in view of Izumi.
Regarding claim 10, Komukai and vS disclose the system of claim 9 comprising instructions executable by the processor (vS fig. 17, 1752; see [0087]) to form a plurality of contact holes (Komukai fig. 11, CH1b-12b; c.f. figs. 4-10; see [0053]) in a film stack (Komukai fig. 4, 3-1 through 3-13 and 2-1 through 2-12; see [0043]).
Komukai and vS fail to explicitly disclose wherein the instructions executable by the processor to form the plurality of contact openings in the film stack comprises: patterning a first set of openings through a first masking layer; etching, through the first set of openings, a first set of contact openings of the plurality of contact openings; patterning a second set of openings through a second masking layer, wherein one opening of the second set of openings is aligned with one contact opening of the first set of contact openings; etching, through the second set of openings, a second set of contact openings of the plurality of contact openings;
patterning a third set of openings through a third masking layer, wherein the third masking layer is formed over the first and second sets of contact openings; and etching, through the third set of openings, a third set of contact openings of the plurality of contact openings.
Izumi discloses a method for forming NAND memory devices (see Izumi [0006]) wherein forming a plurality of contact openings (Izumi fig. 10, 69A-F) in a film stack (Izumi fig. 2, 32T-F and 42A-F (alternating stack (32, 42)); see [0021]-[0023]) comprises:
patterning a first set of openings (Izumi fig. 3: 49D and 49F; see [0051]) through a first masking layer (Izumi fig. 3, 45; see [0050]);
etching, through the first set of openings, a first set of contact openings (Izumi fig. 3: 69D and 69F; see [0053]) of the plurality of contact openings;
patterning a second set of openings (Izumi fig. 5: 49’D and 49’E; see [0057]) through a second masking layer (Izumi fig. 5, 45’; see [0055]-[0056]), wherein one opening of the second set of openings (Izumi fig. 5, 49’D) is aligned with one contact opening of the first set of contact openings (Izumi fig. 3, 69D; c.f. fig. 5; mask opening 49’D is aligned with contact opening 69D initially formed with the first set of contact openings);
etching, through the second set of openings, a second set of contact openings (Izumi fig. 6: 69D and 69E; see [0059]) of the plurality of contact openings;
patterning a third set of openings (Izumi fig. 8: 49’’A, 49’’B, 49’’C; see [0065]) through a third masking layer (Izumi fig. 8, 45’’; see [0063]-[0064]), wherein the third masking layer is formed over the first and second sets of contact openings (see Izumi fig. 8; c.f. figs. 3 and 6);
and etching, through the third set of openings, a third set of contact openings (Izumi fig. 9: 69A, 69B, 69C; see [0067]) of the plurality of contact openings.
The contact opening formation method of Izumi is incorporated as the contact opening formation method step implemented by combined system of Komukai and vS wherein the combination discloses all of the limitations of claim 10.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement the contact opening formation method of Izumi with combined system of Komukai and vS to reduce processing complexity (e.g. see Izumi [0011]).
Regarding claim 11, Komukai, vS, and Izumi, disclose the system of claim 10, wherein the instructions executable by the processor (vS fig. 17, 1752; see [0087]) to form the plurality of contact openings (Izumi fig. 10, 69A-F) in the film stack (Komukai fig. 4, 3-1 through 3-13 and 2-1 through 2-12; see [0043]) further comprises:
forming the first set of contact openings (Izumi fig. 3, 69D and 69F; c.f. fig. 10) to a first depth;
forming the second set of contact openings (Izumi fig. 6, 69D and 69E; c.f. fig. 10) to a second depth, wherein the second depth is greater than the first depth (see Izumi fig. 10);
and forming the third set of contact openings (Izumi fig. 9: 69A, 69B, 69C; c.f. fig. 10) to a third depth, wherein the third depth is greater than the second depth (see Izumi fig. 10).
Claim 13 is rejected under 35 U.S.C. 103 as being obvious over Komukai, in view of vS, further in view of Izumi2.
Komukai and vS disclose the system of claim 9 comprising instructions executable by the processor (vS fig. 17, 1752; see [0087]) to remove the liner (Komukai fig. 12, 60; see [0058]) from a bottom of each contact opening (Komukai fig. 11, CH1b-12b; c.f. figs. 4-10; see [0053]).
Komukai and vS fail to explicitly disclose wherein the instructions executable by the processor to remove the liner from the bottom of each contact opening of the plurality of contact openings further comprises exposing an upper surface of one or more of the plurality of wordlines.
Izumi2 discloses a method for fabricating NAND memory devices (see Izumi2 [0011]) wherein removing a liner (Izumi2 fig. 18, 65; see [0110]: contiguous material layer 65 acts as a liner (“encapsulating liner portions”) disposed within contact openings 69; see figs. 22-23 and [0122]: the contiguous material layer 65 includes the same material as insulating liners 64, and the bottom portions of the contiguous material layer 65 in each contact opening 69 are removed to expose the top surfaces of corresponding conductive electrodes 46) from the bottom of each contact opening of a plurality of contact openings (Izumi2 fig. 23, 69) further comprises exposing an upper surface of one or more of a plurality of wordlines (Izumi2 fig. 23, 46; see [0120] and [0126]).
The wordline exposure technique of Izumi2 is incorporated as the wordline exposure technique of the previously combined system of Komukai and vS wherein the combination discloses all of the limitations of claim 13.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the combined system of Komukai and vS with the liner removal teachings of Izumi2 because the combination is a simple substitution one known method step for another to obtain predictable results—simple substitution of the wordline exposure technique of the combined method of Komukai and vS (see Komukai fig. 15 and [0061]: contact holes CH1-12 are formed to be in contact with underlying insulating layers 30, and, in a subsequent step, both insulating film 60 on the bottom of the contact holes CH along with the underlying portions of the respective insulating layers 30 are etched to expose the respective conductive layer 70) with the wordline exposure technique of Izumi2 (see Izumi2 figs. 22 and 23 and [0122]: contiguous material layer 65 (i.e. liner) is etched to directly expose conductive electrodes 46) to obtain predictable results (i.e. exposing buried wordlines for external connection).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Komukai, in view of vS, further in view of Lee.
Komukai and vS disclose the system of claim 9 comprising instructions executable by the processor (vS fig. 17, 1752; see [0087]) to form a plurality of contact holes (Komukai fig. 11, CH1b-12b; c.f. figs. 4-10; see [0053]) in a film stack (Komukai fig. 4, 3-1 through 3-13 and 2-1 through 2-12; see [0043]).
Komukai and vS fail to explicitly disclose instructions executable by the processor to form a second plurality of contact openings in the film stack, wherein each contact opening of the second plurality of contact openings is formed to a different etch depth relative to an upper surface of the film stack, wherein an average diameter of the second plurality of contact openings is greater than an average diameter of the plurality of contact openings, and wherein an average depth of the second plurality of contact openings is greater than an average depth of the plurality of contact openings.
Lee discloses a method for forming muti-level contacts for vertical NAND memory arrays (see Lee [0022] and [0049]; see figs. 10a-h) comprising forming a second plurality of contact openings (see Lee figs. 10a-10h and [0051]-[0052]; Lee discloses forming a plurality of contact openings to expose up to 256 material layers with mutually increasing depth and diameter (see fig. 10h); exemplary contact openings 130A-B as shown in fig. 10g can be labeled as a second plurality of contact openings) in a material layer (Lee fig. 10e, 124; see [0036]),
wherein each contact opening of the second plurality of contact openings is formed to a different etch depth relative to an upper surface of the material layer (see Lee figs. 10g-h and [0051]-[0052]; note that contact openings 130A-E (130C-E are not shown) extend to a depth defined by a respective step 120 underlying a respective opening in mask 300),
wherein an average diameter of the second plurality of contact openings is greater than an average diameter of the plurality of contact openings (see figs. g-h and [0052]: contact openings 130C-E (not shown) are the plurality of contact openings; the average diameter of contact openings 130A-B is larger than the average diameter of contact openings 130C-E (not shown)),
and wherein an average depth of the second plurality of contact openings is greater than an average depth of the plurality of contact openings (see Lee figs. 10g-h and [0051]; the average depth of contact openings 130A-B is larger than the average depth of contact openings 130C-E (not shown)).
The foregoing teachings of Lee are incorporated into the previously combined system of Komukai and vS wherein the combination discloses all of the limitations of claim 15.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the combined system of Komukai and vS with the foregoing teachings of Lee to achieve faster and more evenly distributed etching (see Lee [0051]: since etching proceeds faster in larger diameter openings, the teachings of Lee enable a common etch step that simultaneously forms the plurality of contact openings with more uniformity than the alternative).
Conclusion
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/HAMNER FITZHUGH COLLINS IV/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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