Prosecution Insights
Last updated: July 17, 2026
Application No. 18/523,402

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Non-Final OA §103
Filed
Nov 29, 2023
Examiner
CHOWDHARY, NIMARTA KAUR
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
NANYA TECHNOLOGY Corporation
OA Round
1 (Non-Final)
100%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allowance Rate
1 granted / 1 resolved
+32.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
22 currently pending
Career history
22
Total Applications
across all art units

Statute-Specific Performance

§103
88.7%
+48.7% vs TC avg
§102
11.3%
-28.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1 resolved cases

Office Action

§103
DETAILED ACTION IDS All references provided in the IDS have been considered. Election/Restrictions Applicant’s election without traverse of Group II (Claims 10-20) in the reply filed on 03/05/2026 is acknowledged. Examiner notes the cancelation of Claims 1-9. Claim Rejections - 35 USC § 103 The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 10-19 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Yoon (US 20130005110 A1) in view of Song (US 20080029899 A1). Re: Independent Claim 10, Yoon discloses: A method of manufacturing a semiconductor device (Yoon, Fig.1, ¶ [0027], comprising: sequentially forming a landing pad (Yoon, contact plug; Fig. 3, element 130), a first nitride layer (Yoon, interlayer dielectric film, etch stop layer; Fig. 3, elements 120 and 140, respectively make up the first nitride layer, ¶ [0030]), a first oxide layer (Yoon, first supporting layer; Fig. 3, element 152, ¶ [0034]), a second nitride layer (Yoon, second supporting layer; Fig. 3, element 154, ¶ [0034]), a second oxide layer (Yoon, third supporting layer; Fig. 3, element 156, ¶ [0034]), and a third nitride layer (Yoon, first mask pattern; Fig. 3, element 210, ¶ [0059]); forming a trench (Yoon, plurality of openings; Fig. 3, element 160, ¶ [0040]) running through the third nitride layer, the second oxide layer, the second nitride layer, and the first oxide layer; depositing a protective liner layer (Yoon, silicide prevention layer; Fig. 4, element 170) on an inner sidewall of the trench and a top surface of the third nitride layer; punching through the first nitride layer and exposing the landing pad (Yoon, Fig. 4, ¶ [0042]); etching the first nitride layer (Yoon, ¶ [0050]) Yoon does not explicitly disclose: isotropically etching the first nitride layer to form an expanding portion and increase an overall width of the expanding portion; Song discloses: isotropically etching (Song; ¶ [0011]) the first nitride layer (Song; second interlayer insulating layer; Fig. 3, element 120, ¶ [0029]) to form an expanding portion (Song, expanded portion; Fig. 3, element 143) and increase an overall width of the expanding portion (Song; Fig. 3, shows an increasing width for a portion of the expanding portion); Yoon discloses etching the first nitride layer but does not explicitly disclose isotropically etching the first nitride layer. Song discloses isotropically etching the first nitride layer to form an expanding portion and increase an overall width of the expanding portion for providing an increased area for contacting to the storage node pad (Song, ¶ [0033]). It would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date to use isotropic etching, as disclosed by Song, in the method of Yoon because isotropic etching is a well-known technique used to uniformly etch in all directions, with a known result of producing an expanded or widened portion of the etched feature. A POSITA would have reasonably expected that incorporating the etching method of Song to the etching method of Yoon would result in increasing an overall width of the expanding portion, arriving at the claimed invention. Yoon, as modified by Song, further discloses: removing the protective liner layer (Yoon, Figs. 12-13; ¶ [0067]); and depositing an electrode layer (Yoon, lower electrode; Fig. 5, element 180) on the inner sidewall of the trench and the top surface of the third nitride layer (Yoon, Fig. 4, shows element 170 on a top surface of element 210). Re: Claim 11, Yoon and Song disclose all the limitations of claim 10 on which this claim depends. Yoon further discloses: wherein forming the trench (Yoon, plurality of openings; Fig. 3, element 160, ¶ [0040]) is performed such that the first nitride layer (Yoon, interlayer dielectric film, etch stop layer; Fig. 3, elements 120 and 140, respectively make up the first nitride layer, ¶ [0030]) is exposed. Re: Claim 12, Yoon and Song disclose all the limitations of claim 10 on which this claim depends. Yoon further discloses: wherein depositing the protective liner layer (Yoon, silicide prevention layer; Fig. 4, element 170) is performed such that the protective liner layer contacts a top surface (Yoon, the outermost surface of the etch stop layer; Fig. 4, element 140, can be considered a top surface of the first nitride layer) of the first nitride layer (Yoon, interlayer dielectric film, etch stop layer; Fig. 3, elements 120 and 140, respectively make up the first nitride layer, ¶ [0030]). Re: Claim 13, Yoon and Song disclose all the limitations of claim 12 on which this claim depends. Yoon further discloses: wherein punching (Yoon, Fig. 4, ¶ [0042]) through the first nitride layer (Yoon, interlayer dielectric film, etch stop layer; Fig. 3, elements 120 and 140, respectively make up the first nitride layer, ¶ [0030]) and exposing the landing pad (Yoon, contact plug; Fig. 3, element 130) are performed such that a portion of the protective liner layer (Yoon, silicide prevention layer; Fig. 4, element 170) on the top surface (Yoon, the outermost surface of the etch stop layer; Fig. 4, element 140, can be considered a top surface of the first nitride layer) of the first nitride layer is removed (Yoon, ¶ [0050]). Re: Claim 14, Yoon and Song disclose all the limitations of claim 10 on which this claim depends. Yoon and Song further disclose: wherein isotropically etching (Song; ¶ [0011]) the first nitride layer is performed (Song; second interlayer insulating layer; Fig. 3, element 120, ¶ [0029]) after punching (Yoon, Fig. 4, ¶ [0042]) through the first nitride layer (Song; second interlayer insulating layer; Fig. 3, element 120, ¶ [0029]) and exposing the landing pad (Song, contact pads; Fig. 3, elements 114 and 116, ¶ [0046]) (Song, Figs. 8a shows the contact holes and landing being exposed, and this process occurs earlier in the process than the isotropic etching of the first nitride layer, which is shown in Song, Fig. 9C, ¶ [0036]). Re: Claim 15, Yoon and Song disclose all the limitations of claim 10 on which this claim depends. Song further discloses: wherein isotropically etching (Song; ¶ [0011]) the first nitride layer is performed (Song; second interlayer insulating layer; Fig. 3, element 120, ¶ [0029]) such that an expanding portion (Song, expanded portion; Fig. 3, element 143) of the trench (Song, expanded contact hole; Fig. 9C; element 144b) is formed, and wherein the expanding portion of the trench runs through the first nitride layer (Song, Fig. 3). Re: Claim 16, Yoon and Song disclose all the limitations of claim 15 on which this claim depends. Song further discloses: wherein isotropically etching (Song; ¶ [0011]) the first nitride layer (Song; second interlayer insulating layer; Fig. 3, element 120, ¶ [0029]) is performed such that the expanding portion (Song, expanded portion; Fig. 3, element 143) of the trench (Song, expanded contact hole; Fig. 9C; element 144b) is connected between the landing pad (Song, contact pads; Fig. 3, elements 114 and 116) and a top surface of the first nitride layer (Song, Fig. 3, the top surface of the first oxide layer (element 122) can be considered a top surface of the first nitride layer). Re: Claim 17, Yoon and Song disclose all the limitations of claim 15 on which this claim depends. Song further discloses: wherein isotropically etching (Song; ¶ [0011]) the first nitride layer (Song; second interlayer insulating layer; Fig. 3, element 120, ¶ [0029]) is performed such that a width of a top of the expanding portion (Song, expanded portion; Fig. 3, element 143, the middle section of the expanding portion can be considered a width of a top of the expanding portion) of the trench (Song, expanded contact hole; Fig. 9C; element 144b) is greater than a width of a bottom of the expanding portion (Song, Fig. 3, the bottom most portion of the expanding portion can be considered a width of a bottom of the expanding portion) of the trench. Re: Claim 18, Yoon and Song disclose all the limitations of claim 17 on which this claim depends. Song further discloses: wherein isotropically etching (Song; ¶ [0011]) the first nitride layer (Song; second interlayer insulating layer; Fig. 3, element 120, ¶ [0029]) is performed such that the width of the top of the expanding portion (Song, expanded portion; Fig. 3, element 143, the middle section of the expanding portion can be considered the width of a top of the expanding portion) of the trench (Song, expanded contact hole; Fig. 9C; element 144b) is equal to or greater than a width of a top of the trench (Song, Fig 3, the top most part of the contact hole can be considered a top of the trench). Re: Claim 19, Yoon and Song disclose all the limitations of claim 10 on which this claim depends. Yoon further discloses: wherein depositing the electrode layer (Yoon, lower electrode; Fig. 5, element 180) is performed such that the electrode layer contacts the landing pad (Yoon, contact plug; Fig. 5, element 130). Claim(s) 20 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Yoon (US 20130005110 A1) in view of Song (US 20080029899 A1), further in view of Murray (US 9997406 B2). Re: Claim 20, Yoon and Song disclose all the limitations of claim 10 on which this claim depends. Yoon further discloses: the protective liner layer (Yoon, silicide prevention layer; Fig. 4, element 170) Yoon and Song do not explicitly disclose: wherein a thickness of the protective liner layer is equal to or greater than 2 nanometers. Murray discloses: wherein a thickness of the protective liner layer (Murray, crystallization seed layer; Fig. 6, element 601) is equal to or greater than 2 nanometers (Murray, Col. 5, lines 12-18). Yoon and Song collectively disclose a protective liner layer but do not explicitly disclose this protective liner layer to have a thickness greater than or equal to 2 nanometers. Murray discloses a protective liner layer of a thickness between 1-100 nanometers used in an interconnect structure. Yoon, Song, and Murray disclose semiconductor devices, their components, and their configurations, and are therefore analogous art. It would have been obvious to a POSITA before the effective filing date to have a thickness of the protective liner layer of 1-100 nanometers to selectively promote the use of further components (Murray, Col. 5, lines 5-11). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIMARTA KAUR CHOWDHARY whose telephone number is (571)272-7679. The examiner can normally be reached usually Monday - Thursday, 6:45 AM - 4:45 PM (EST). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NIMARTA KAUR CHOWDHARY/ Examiner, Art Unit 2898 /Leonard Chang/ Supervisory Patent Examiner, Art Unit 2898
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Prosecution Timeline

Nov 29, 2023
Application Filed
Apr 23, 2026
Non-Final Rejection mailed — §103
Jun 24, 2026
Interview Requested
Jul 01, 2026
Applicant Interview (Telephonic)
Jul 01, 2026
Examiner Interview Summary

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12666589
MEMORY CELL, MEMORY, AND METHOD OF MANUFACTURING THE SAME
1y 3m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 1 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
100%
Grant Probability
99%
With Interview (+0.0%)
2y 7m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1 resolved cases by this examiner. Grant probability derived from career allowance rate.

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