DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-13 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. as set forth below.
The following analysis is performed as set forth in the 2024 Revised Patent Subject Matter Eligibility Guidance (hereinafter 2024 PEG), as set forth in MPEP § 2106. (Note: the claim limitations below considered to fall within an abstract idea are highlighted in bold font; the remaining features are "additional elements.")
Step 1
Step 1 of the 2024 PEG asks whether a claim is directed to a process, machine, manufacture, or composition of matter.
Claim 1-13 is directed to a method, and therefore fall within a statutory category.
Claim 1 recites:
"A method of monitoring a health state of a power semiconductor device, the method comprising:
receiving an initial transient voltage parameter relating to a transient voltage of the power semiconductor device when turning on, when the power semiconductor device is known to be unaged;
receiving an initial transient current parameter relating to a transient current of the power semiconductor device when turning on, when the power semiconductor device is known to be unaged;
determining an initial energy parameter, relating to an initial turn-on switching energy or power of the power semiconductor device, when the power semiconductor device is known to be unaged, based on the initial transient voltage parameter and the initial transient current parameter;
receiving an operating transient voltage parameter relating to the transient voltage of the power semiconductor device in operation;
receiving an operating transient current parameter relating to the transient current of the power semiconductor device in operation;
determining an operating energy parameter, relating to the turn-on switching energy or power of the power semiconductor device in operation, based on the operating transient voltage parameter and the operating transient current parameter; and
determining the health state of the power semiconductor device based on the initial energy parameter and the operating energy parameter."
The highlighted portion of claim 1 comprises subject matter that falls within the abstract idea judicial exception. Specifically, "… determining an initial energy parameter, relating to an initial turn-on switching energy or power of the power semiconductor device, when the power semiconductor device is known to be unaged, based on the initial transient voltage parameter and the initial transient current parameter; … determining an operating energy parameter, relating to the turn-on switching energy or power of the power semiconductor device in operation, based on the operating transient voltage parameter and the operating transient current parameter; and
determining the health state of the power semiconductor device based on the initial energy parameter and the operating energy parameter" is a series of abstract process steps that, under a broadest reasonable interpretation, covers mathematical concepts/mental processes performed in the human mind and/or with pen and paper.
Nothing in the claim, other than the generically recited computer elements, precludes the identified abstract process steps from practically being performed in the mind and/or with pen and paper.
Step 2A, Prong Two
Step 2A, Prong Two of the 2024 PEG asks whether a claim recites additional elements that integrate the judicial exception into a practical application. In view of the various considerations encompassed by the Step 2A, Prong Two analysis, claims 1-13 do not include additional elements that integrate the recited abstract idea into a practical application. Based on the individual and collective limitations of claims 1-13 applying a broadest reasonable interpretation, the most significant of such considerations appear to include: improvements to the functioning of a computer, or to any other technology or technical field (MPEP 2106.05(a)); applying the judicial exception with, or by use of, a particular machine (MPEP 2106.05(b)); adding a specific limitation other than what is well-understood, routine, conventional activity in the field (MPEP § 2106.05(d)); and applying or using the judicial exception in some other meaningful way beyond generally linking the use of the judicial exception to a particular technological environment, such that the claim as a whole is more than a drafting effort designed to monopolize the exception (MPEP 2106.05(e)).
Regarding improvements to the functioning of a computer or other technology or technical field, claims 1-13 do not include any such improvements.
Regarding applying the judicial exception with, or by use of, a particular machine, claims 1-13 do not apply the judicial exception with, or by use of, a particular machine. Claims 1-13 recite generic computer elements, but this is not sufficient to say that the judicial exception is applied with, or by use of, a particular machine.
Regarding adding a specific limitation other than what is well-understood, routine, conventional activity in the field, claims 1-13 do not appear to contain such a limitation.
Regarding applying or using the judicial exception in some other meaningful way beyond generally linking the use of the judicial exception to a particular technological environment (MPEP 2106.05(e)), claims 1-13 do not apply or use the judicial exception in some other meaningful way.
claims 1-13 thus require further analysis under Step 2B.
Step 2B
Step 2B of the 2024 PEG asks whether the claim recites additional elements that amount to significantly more than the judicial exception.
With regards to claim 1: the additional element of receiving an initial transient voltage parameter relating to a transient voltage of the power semiconductor device when turning on, when the power semiconductor device is known to be unaged merely relates to insignificant extra-solution activity (determining when data gathering is to be performed). The additional element of receiving an initial transient current parameter relating to a transient current of the power semiconductor device when turning on, when the power semiconductor device is known to be unaged merely relates to insignificant extra-solution activity (data gathering). The additional element of receiving an operating transient voltage parameter relating to the transient voltage of the power semiconductor device in operation merely relates to insignificant extra-solution activity (data gathering). The additional element of receiving an operating transient current parameter relating to the transient current of the power semiconductor device in operation merely relates to insignificant extra-solution activity (data gathering). These elements thus fail the "significantly more" test under Step 2B. Claim 1 therefore constitutes ineligible subject matter.
Claims 2-13 are rejected for depending from rejected claim 1 and only amounting to further limit the abstract idea of claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xu et al (CN 112067967A, cited in IDS, using attached translation, heretofore referred to as Xu).
Regarding claim 1, Xu teaches a method of monitoring a health state of a power semiconductor device (Xu; Fig 7, Elements VT1-VT6 and Par 0122-0126; Xu teaches monitoring IGBT health status), the method comprising:
receiving an initial transient voltage parameter relating to a transient voltage of the power semiconductor device when turning on, when the power semiconductor device is known to be unaged (Xu; Fig. 7, Par 0118, and Par 0120-0124; Xu teaches obtaining the turn-on voltage of the IGBT. The IGBT as such, i.e. without the paralleling resistor, is still in a healthy unaged state, so that the initial voltage, current and energy parameters "relate" to the initial voltage, current and energy, respectively, when the semiconductor device is unaged);
receiving an initial transient current parameter relating to a transient current of the power semiconductor device when turning on, when the power semiconductor device is known to be unaged (Xu; Fig. 7, Par 0118, and Par 0120-0124; Xu teaches obtaining the turn-on current of the IGBT. The IGBT as such, i.e. without the paralleling resistor, is still in a healthy unaged state, so that the initial voltage, current and energy parameters "relate" to the initial voltage, current and energy, respectively, when the semiconductor device is unaged);
determining an initial energy parameter, relating to an initial turn-on switching energy or power of the power semiconductor device, when the power semiconductor device is known to be unaged, based on the initial transient voltage parameter and the initial transient current parameter (Xu; Fig. 8, Par 0063-0073 and Par 0120-0124; Xu teaches IGBT turn-on loss, Eon, as initial energy parameter in calculated according to equation 1 based on the received initial transient voltage parameter and the initial transient current parameter. A 3D diagram is generated containing values of said energy loss for different IGBT states. In particular, different paralleling resistors are chosen to simulate different aging degrees. However, the IGBT as such, i.e. without the paralleling resistor, is still in a healthy unaged state, so that the initial voltage, current and energy parameters "relate" to the initial voltage, current and energy, respectively, when the semiconductor device is unaged);
receiving an operating transient voltage parameter relating to the transient voltage of the power semiconductor device in operation (Xu; Fig. 7, Par 0117-0118, and Par 0120-0124; Xu teaches obtaining the output Voltage of the IGBT while in a working state);
receiving an operating transient current parameter relating to the transient current of the power semiconductor device in operation (Xu; Fig. 7, Par 0117-0118, and Par 0120-0124; Xu teaches obtaining the output current of the IGBT while in a working state);
determining an operating energy parameter, relating to the turn-on switching energy or power of the power semiconductor device in operation, based on the operating transient voltage parameter and the operating transient current parameter (Xu; Par 0125; Xu teaches determining the operating current and turn-off loss of the IGBTs under test); and
determining the health state of the power semiconductor device based on the initial energy parameter and the operating energy parameter (Xu; Par 0125; Xu teaches determining the IGBT health state based on the initial energy parameter and the operating energy parameter, i.e. by comparing the switching loss of the tested IGBT with the 3D data of the aging switching loss).
Regarding claim 2, Xu teaches a method according to claim 1, wherein the health state of the power semiconductor device is determined to be aged if the operating energy parameter is above a threshold, the threshold being determined based on the initial energy parameter (Xu; Par 0112; Xu teaches when the aging degree is determined to have exceeded a threshold it may be replaced).
Regarding claim 3, Xu teaches a method according to claim 2, wherein the threshold is at least 20% higher than the initial energy parameter (Xu; Fig. 8-9, Par 0112, and Par 0123; Xu teaches when the aging degree is compared to pre-obtained data that is used to determine the percentage of the threshold).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-6 and 9-13 are rejected under 35 U.S.C. 103 as being unpatentable over Xu in view of Halick et al (US 2020/0241067 A1, heretofore referred to as Halick).
Regarding claim 4, Xu teaches a method according to claim 1. Xu further teaches further comprising: receiving an initial load parameter when the power semiconductor device is known to be unaged (Xu; Par 0122; Xu teaches connecting a load to the IGBT), and receiving an operating load parameter parameter during operation of the power semiconductor device (Xu; Par 0122; Xu teaches applying a DC load current to the connected load).
Xu is silent on wherein the initial energy parameter is normalised based on the initial load parameter and the operating energy parameter is normalised based on the operating load parameter.
Halick teaches wherein the initial energy parameter is normalised based on the initial load parameter and the operating energy parameter is normalised based on the operating load parameter (Halick; Par 0040, Par 0048-0049, and Par 0093-0094; Halick teaches normalization based on based on load parameters).
Before the effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use the method of Xu with the load normalization method of Halick in order to increase accuracy of the method (Halick; Par 0050).
Regarding claim 5, the combination of Xu and Halick teaches a method according to claim 4. Halick further teaches wherein the load parameter comprises at least one of: a temperature parameter relating to a temperature of the power semiconductor device (Halick; Par 0048; Halick teaches junction temperature is used); a predetermined load voltage parameter relating to a load voltage which is applied to the power semiconductor device (Halick; Par 0048-0049; Halick teaches predetermined voltage or current may be used); and a predetermined load current parameter relating to a load current which is applied to the power semiconductor device (Halick; Par 0048-0049; Halick teaches predetermined voltage or current may be used).
Regarding claim 6, Xu teaches a method according to claim 1, wherein the (i) initial energy parameter and the (ii) operating energy parameter are based respectively on (i) digitally integrating initial transient current parameter and initial transient voltage parameter and on (ii) digitally integrating operating transient current parameter and operating transient voltage parameter.
Xu is silent on wherein the (i) initial energy parameter and the (ii) operating energy parameter are based respectively on (i) digitally integrating initial transient current parameter and initial transient voltage parameter and on (ii) digitally integrating operating transient current parameter and operating transient voltage parameter.
Halick teaches wherein the (i) initial energy parameter and the (ii) operating energy parameter are based respectively on (i) digitally integrating initial transient current parameter (Halick; Fig. 6, Par 0080, and Par 0092; Halick teaches integrating the first portion of the turn-off current) and initial transient voltage parameter and on (ii) digitally integrating operating transient current parameter and operating transient voltage parameter (Halick; Fig. 6, Par 0080, and Par 0092; Halick teaches further integrating the operational current of the turn-off current)..
Before the effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use the method of Xu with the current integration method of Halick in order to reduce the data sent to the processor (Halick; Par 0079).
Regarding claim 9, Xu teaches a method according to claim 1.
Xu is silent on further comprising: determining a remaining useful life of the power semiconductor device based on the initial energy parameter and the operating energy parameter, using a machine learning algorithm which has been trained with experimental data of energy parameter variation over a lifecycle of sample power semiconductor devices.
Halick teaches further comprising: determining a remaining useful life of the power semiconductor device based on the initial energy parameter and the operating energy parameter (Halick; Par 0005, Par 0039, and 0061; Halick teaches determining remaining lifetime of the power converter), using a machine learning algorithm which has been trained with experimental data of energy parameter variation over a lifecycle of sample power semiconductor devices (Halick; Par 0005, Par 0039, and 0061; Halick teaches using prognostic methodologies that improve over time, i.e. machine learning).
Before the effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use the method of Xu with the machine learning method of Halick in order to provide a lower rate of failure (Halick; Par 0005).
Regarding claim 10, Xu teaches an external circuit for connecting to a power semiconductor device (Xu; Fig 2A, Elements 1 and 2 and Par 0055; Xu teaches an external measurement circuit) and to perform a method in accordance with claim 1 based on the received signals (Xu; Par 0055; Xu teaches the external circuit performs the method steps of claim 1).
Xu is silent on the external circuit comprising: a rogowski coil for measuring transient current; an analog isolator connected to a voltage sensor; a processor configured receive signals from the analog isolator and the rogowski coil.
Halick teaches comprising: a rogowski coil for measuring transient current (Halick; Fig. 1, Elements 120a-120c and Par 0047); an analog isolator (Halick; Fig. 3A, Elements 128a-128b and Par 0077) connected to a voltage sensor (Halick; Fig. 3A, Element 122 and Par 0077); a processor configured receive signals from the analog isolator and the rogowski coil (Halick; Fig. 3A, Element 134 and Par 0064).
Before the effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use the method of Xu with the external circuitry of Halick in order to protect the controller (Halick; Par 0077).
Regarding claim 11, the combination of Xu and Halick teaches an external circuit according to claim 10. Halick further teaches further comprising a gate driver (Halick; Par 0077) configured to be connected between the analog isolator and a gate of the power semiconductor device, and configured to trigger initiation of voltage monitoring and current monitoring when the circuit is turned on (Halick; Par 0077; Halick teaches the controller may be a gate driver which determines when the circuit is activated).
Regarding claim 12, Xu teaches an external circuit according to claim 10. Halick teaches further comprising a digital integration field-programmable gate array configured to receive signals from the analog isolator, and to integrate the signals for processing by the processor (Halick; Par 0076; Halick teaches an integrator circuit to prepare the signals for processing).
Regarding claim 13, Xu teaches an external circuit according to claim 10. Halick teaches further comprising at least one temperature sensor (Halick; Par 0048-0049; Halick teaches junction temperature and ambient temperature may be measured with a sensor) configured to monitor the temperature of a case of the semiconductor device, and to deliver a signal indicative of the temperature of the case to the processor (Halick; Par 0048 and Par 0060; Halick teaches temperature is used as the operating parameter sent to the controller).
Comments
The prior art of record found as a result of the search, does not teach alone or in combination all of the elements recited in claims 7-8. Therefore, no prior art rejection for claim 7 is presented in this action. However, claims 7-8 are rejected under 35 U.S.C. 101. It is suggested to contact the Examiner for any clarification with respect the rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
-Kuo et al teaches a test circuit for transistor degradation.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM S CLARKE whose telephone number is (571)270-3792. The examiner can normally be reached M-F 8am-4pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached at (571)272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ADAM S CLARKE/Examiner, Art Unit 2858
/JUDY NGUYEN/Supervisory Patent Examiner, Art Unit 2858