DETAILED ACTION
This Office action responds to Applicant’s election filed on 06/26/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The present Office action is made with all previously suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-20.
Election/Restriction
The Applicant’s response on 06/26/2026 in reply to the restriction/election requirements mailed on 04/06/2026 has been entered. Applicant’s election without traverse of invention Group I (drawn to a semiconductor device), drawn to claim 1-18 is acknowledged. Applicant’s election without traverse of Species 2, drawn to claims 1-11, is acknowledged. Examiner agrees. Claims 12-20 were cancelled by the Apllicant. New claims 21-29 were brought by the Applicant. Thus, pending in this Office action are claims 1-11, and 21-29.
Information Disclosure Statement (IDS)
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Specification Objection
The specification has been checked to the extend necessary to determine the presence of possible minor errors. However, the Applicant’s cooperation is requested in correcting any errors of which Applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3 are rejected under 35 U.S.C. 103 as obvious over Roy (US 2011/0260536) in view of Sawada (US 2021/0092214).
Regarding claim 1, Roy shows (see, e.g., Roy: fig. 7) most aspects of the instant invention including a semiconductor device, comprising:
A first switch S1, a second switch S2, a third switch S4, and a fourth switch S3
wherein:
The first switch S1 and the second switch S2 are connected in series between a first reference voltage Vsource and an output voltage Vbuffer
The third switch S4 and the fourth switch S3 are connected in series between the first reference voltage Vsource and a second reference voltage Ground
A capacitor C1 has a first terminal N1 and a second terminal N0
wherein:
The first terminal N1 is coupled to a first node N1 between the first switch S1 and second switch S2
The second terminal N0 is coupled to a second node N0 between the third switch S4 and fourth switch S3
However, Roy fails (see, e.g., Roy: fig. 7) to show that the first switch S1, a second switch S2, a third switch S4, and a fourth switch S3 are formed on a first side of a substrate. Sawada, in a similar device to Roy, shows (see, e.g., Sawada: figs. 1, and 2B) that the first switch 51, a second switch 52, a third switch 53, and a fourth switch 54 are formed on a first side of a substrate 91. Sawada also shows (see, e.g., Sawada: figs. 1, and 2B) the first switch 51, a second switch 52, a third switch 53, and a fourth switch 54 are formed on a first side of a substrate 91 in order to have short connection of switches to the controller RFIC and also to have short transmission paths (see, e.g., Sawaba: par. [0023], and [0027]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the first switch, a second switch, a third switch, and a fourth switch formed on a first side of a substrate of Sawada in the device of Roy, in order to have short connection of switches to the controller RFIC and also to have short transmission paths.
Roy in view of Sawada also shows (see, e.g., Sawada: figs. 1, and 2B) the capacitor 31 (see, e.g., Sawaba: par. [0036], and [0004]) formed on a second side of the substrate 91 opposite to the first side.
Regarding claim 2, Roy in view of Sawada shows (see, e.g., Roy: fig. 7) that the first switch S1 and the fourth switch S3 are configured to be activated while the second switch S2 and third switch S4 are configured to be deactivated, causing voltages at the first terminal N1 and at the second terminal N0 to be equal to the first reference voltage Vsource and the second reference voltage Ground, respectively (see also MPEP 2112.01 and MPEP 2114.I/2114.II).
Also, and with respect to claim 2, note that a limitation in a claim with respect to the manner in which a claimed device is intended to be used does not differentiate the claimed device from a prior-art device, if the prior-art device teaches all structural limitations in the claim and the limitations are found to be inherent in the prior-art device. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); Ex Parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See Hewlett-Packard Co. v. Bausch & Lomb Inc. and the related case law cited therein which makes it clear that it is the final product per se which must be determined in a device claim, and not the patentability of its functions (909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990)). As stated in Best,
Where the claimed and prior art products are identical or substantially identical in structure or composition, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
Note that the applicant has burden of proof once the examiner establishes a sound basis for believing that the products of the applicant and the prior art are the same. See In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990).
Regarding claim 3, Roy in view of Sawada shows (see, e.g., Roy: fig. 7) that, following the voltage at the first terminal N1 being equal to the first reference voltage Vsource, the first switch S1 and the fourth switch S3 are configured to be deactivated while the second switch S2 and third switch S4 are configured to be activated, causing the voltages at the first terminal N1 and at the second terminal N0 to be equal to a multiple of the first reference voltage Vsource and the first reference voltage Vsource, respectively respectively (see also MPEP 2112.01 and MPEP 2114.I/2114.II).
Also, and with respect to claim 3, note that a limitation in a claim with respect to the manner in which a claimed device is intended to be used does not differentiate the claimed device from a prior-art device, if the prior-art device teaches all structural limitations in the claim and the limitations are found to be inherent in the prior-art device. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); Ex Parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See Hewlett-Packard Co. v. Bausch & Lomb Inc. and the related case law cited therein which makes it clear that it is the final product per se which must be determined in a device claim, and not the patentability of its functions (909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990)). As stated in Best,
Where the claimed and prior art products are identical or substantially identical in structure or composition, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
Note that the applicant has burden of proof once the examiner establishes a sound basis for believing that the products of the applicant and the prior art are the same. See In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990).
Regarding claim 26, Roy shows (see, e.g., Roy: fig. 7) most aspects of the instant invention including a semiconductor device, comprising:
A first switch S1, a second switch S2, a third switch S4, and a fourth switch S3
wherein:
The first switch S1 and the second switch S2 are connected in series at a first node N1
The third switch S4 and the fourth switch S3 are connected in series at a second node N0
A fly capacitor C1 has a first terminal N1 coupled to a first node N1 and a second terminal N0 coupled to a first node N0
wherein:
The first switch S1, the second switch S2, the third switch S4, and the fourth switch S3 are configured to alternately activate such that the first switch S1 and the fourth switch S3 are activated while the second switch S2 and the third switch S4 are deactivated, and subsequently the second switch S2 and the third switch S4 are activated while the first switch S1 and the fourth switch S3 are deactivated, to provide an output voltage Vbuffer at the second switch S2 that is a multiple of an input voltage Vsource received at the first switch S1 and the third switch S4 (see also MPEP 2112.01 and MPEP 2114.I/2114.II)
Also, and with respect to claim 26, note that a limitation in a claim with respect to the manner in which a claimed device is intended to be used does not differentiate the claimed device from a prior-art device, if the prior-art device teaches all structural limitations in the claim and the limitations are found to be inherent in the prior-art device. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); Ex Parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See Hewlett-Packard Co. v. Bausch & Lomb Inc. and the related case law cited therein which makes it clear that it is the final product per se which must be determined in a device claim, and not the patentability of its functions (909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990)). As stated in Best,
Where the claimed and prior art products are identical or substantially identical in structure or composition, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
Note that the applicant has burden of proof once the examiner establishes a sound basis for believing that the products of the applicant and the prior art are the same. See In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990).
However, Roy fails (see, e.g., Roy: fig. 7) to show that the first switch S1, a second switch S2, a third switch S4, and a fourth switch S3 are formed on a first side of a substrate. Sawada, in a similar device to Roy, shows (see, e.g., Sawada: figs. 1, and 2B) that the first switch 51, a second switch 52, a third switch 53, and a fourth switch 54 are formed on a first side of a substrate 91. Sawada also shows (see, e.g., Sawada: figs. 1, and 2B) the first switch 51, a second switch 52, a third switch 53, and a fourth switch 54 are formed on a first side of a substrate 91 in order to have short connection of switches to the controller RFIC and also to have short transmission paths (see, e.g., Sawaba: par. [0023], and [0027]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the first switch, a second switch, a third switch, and a fourth switch formed on a first side of a substrate of Sawada in the device of Roy, in order to have short connection of switches to the controller RFIC and also to have short transmission paths.
Roy in view of Sawada also shows (see, e.g., Sawada: figs. 1, and 2B) the fly capacitor 31 (see, e.g., Sawaba: par. [0036], and [0004]) formed on a second side of the substrate 91 opposite to the first side.
Regarding claim 27, Roy in view of Sawada shows (see, e.g., Roy: fig. 7) that the first switch S1, the second switch S2, the third switch S4, and the fourth switch S3 are implemented as a field-effect transistor (see, e.g., Roy: par. [0037]) gated by a clock signal Φ or an inverse of the clock signal ΦB (see, e.g., Roy: par. [0032]).
Allowable Subject Matter
Claims 4-11 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for objecting to claim 4: The prior art of record neither anticipates nor renders obvious that a plurality of first metal tracks disposed in a first one of a plurality of metallization layers on the second side, and a plurality of second metal tracks disposed in the first metallization layer.
Claims 5-11 are objected to because of their dependence on claim 4.
The following is an examiner’s statement of reasons for objecting to claim 28: The prior art of record neither anticipates nor renders obvious that the end portion of the lower electrode overlaps the lower portion.
The following is an examiner’s statement of reasons for objecting to claim 29: The prior art of record neither anticipates nor renders obvious that a plurality of frontside metallization layers disposed over the first side of the substrate, wherein the first switch, the second switch, the third switch, and the fourth switch are coupled to at least one of the input voltage, the output voltage, or a ground reference through frontside metal tracks disposed in the plurality of frontside metallization layers
Claims 21-25 are allowed.
The following is an examiner’s statement of reasons for allowance of claim 21: The prior art of record neither anticipates nor renders obvious that a plurality of via structures extending through the substrate, wherein a first subset of the plurality of via structures couples the first terminal of the capacitor to a first node between a first pair of the plurality of switches, and a second subset of the plurality of via structures couples the second terminal of the capacitor to a second node between a second pair of the plurality of switches.
Claims 22-25 are allowed because of their dependence on claim 21.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIBERIU DAN ONUTA whose telephone number is (571) 270-0074 and between the hours of 9:00 AM to 5:00 PM (Eastern Standard Time) Monday through Friday or by e-mail via Tiberiu.Onuta@uspto.gov. If attempts to reach the examiner by telephone or email are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (in USA or Canada) or 571-272-1000.
/TIBERIU DAN ONUTA/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
Prosecution Insights