DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Claim 1, 3, 4, 5, and 6 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation " said metal control gate" in line 14. There is insufficient antecedent basis for this limitation in the claim. Since the previous statement was “two metal control gates” it is unclear which metal control gate or gates applicant is referring to and thus how many sacrificial layers are required. Examiner is unsure how to interpret this limitation and examined under the impression that it could be any of the combination above, causing the scope of the claim to be unclear. This unclear interpretation of whether applicant is mentioning one metal control gate or both metal control gates is also present in claims 3, 4, 5, and 6. Please distinguish if the limitation pertains to both of the two metal control gates, pertains to at least one of the metal control gates, or pertains to only one metal control gates in line with the specifications.
Claim 1 recites the limitation "said word line." in line 15. There is insufficient antecedent basis for this limitation in the claim. Since the previous statement was “two word lines” it is unclear which word line or lines applicant is referring to. Examiner is unsure how to interpret this limitation and examined under the impression that it could be any of the combination above. This unclear interpretation of whether applicant is mentioning one word line or both word lines is also present in claims 4 and 6. Please distinguish if the limitation pertains to both of the two word lines, pertains to at least one of the word lines, or pertains to only one word lines in line with the specifications.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1- 5 are rejected under 35 U.S.C. 102(a)(1) based upon a public use or sale or other public availability of the invention. The claims are rejected to in anticipation of Meng-Han Lin et al. (US 10937879 B2) hereinafter referred to as “Lin”.
Regarding Claim 1 Lin teaches
An embedded flash memory structure (Col. 1 line 26), comprising:
a semiconductor substrate; (Fig 30B element 210)
an erase gate (312 including the layer SP) on said semiconductor substrate;
two floating gates (232) respectively at two sides (left and right sides) of said erase gate on said semiconductor substrate;
two word lines (314 Col. 7 lines 56) respectively at outer sides of said two floating gates;
and two metal control gates (252) respectively on said two floating gates, wherein a sacrificial layer (242) is provided at at least one side of said metal control gate, and said sacrificial layer is between said metal control gate and said erase gate or between said metal control gate and said word line. (at least a portion of 242 is between 252 and 312 or between 252 and 314).
Regarding Claim 2 Lin teaches
The embedded flash memory structure of claim 1, wherein a material of said sacrificial layer is silicon nitride. (Col. 5 lines 53-56 element 240 once sacrificed and etched becomes 242)
Regarding Claim 3 Lin teaches
The embedded flash memory structure of claim 1, wherein a top surface of said metal control gate is higher than a top surface of said sacrificial layer. (Fig 30B the top surface of 252 is higher than the top surface of 242)
Regarding Claim 4 Lin teaches
The embedded flash memory structure of claim 1, wherein said word line is metal word line (Col. 8 line 66-Col. 9 line 2), said erase gate is metal erase gate (Col. 14 lines 44-48), and tops surface (314a) of said metal word line, said metal erase gate (312a of 312 )and said metal control gate (252) are flush. (see Fig 30A and 30B)
Regarding Claim 5 Lin teaches
The embedded flash memory structure of claim 1, wherein said semiconductor substrate is provided with a memory cell region (shown in Fig 30B Col. 13 lines 7-10) and a logic device region (Col 10, lines 49 the logic stack GS3 is of the logic region), said metal control gate is on said memory cell region (Fig 30B), and a top surface of said metal control gate (252) is flush (Fig 30A)with a top surface of a metal gate (GS3) on said logic device region.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin as applied to claim 5 above, and further in view of Chun-Ming Chen et al. (US 9379121 B1) hereinafter referred to as “Chen”.
Regarding Claim 6 Lin teaches
The embedded flash memory structure of claim 5, wherein said semiconductor substrate is further provided with a high-voltage device region (Col. 10 lines 48-49 the high voltage gate stack GS2 is of the high voltage device region), a polysilicon gate (GS2 Col. 12 lines 38-43 Fig 27) is provided on said high-voltage device region, a top surface of said polysilicon gate (GS2) is flush (Fig 27, 30A)with a top surface of said erase gate (312A) and a top surface of said word line (314A) on said memory cell region,
Lin does not explicitly teach
(that the previously stated top surfaces are flush) but lower than said top surface of said metal gate on said logic device region and said top surface of said metal control gate.
Chen teaches a memory cell and the limitation
but lower than said top surface of said metal gate on said logic device region and said top surface of said metal control gate. (Chen teaches that poly block gates including an erase gate 42 can be recessed lower than the control gate (18) ).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Lin such that the a top surface of said polysilicon gate is flush with a top surface of said erase gate and a top surface of said word line on said memory cell region, but lower than said top surface of said metal gate on said logic device region and said top surface of said metal control gate, as described in Chen because the modification allows for the gates to have room for protective layers disposed on top thusly the gate is left intact enhancing the conductivity. (Chen Col. 5 lines 1-20)
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin as applied to claim 1 above, and further in view of Y.J. Wu et al. (US 20210408023 A1) hereinafter referred to as “Wu”.
Regarding Claim 7 Lin teaches
The embedded flash memory structure of claim 1,
Lin does not explicitly teach
wherein said two metal control gates are not symmetric with respect to said erase gate.
Wu teaches a memory cell
wherein said two metal control gates (CG) are not symmetric (Fig 1A, 1B, 2A) with respect to said erase gate. (EG)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Lin such that the said two metal control gates are not symmetric with respect to said erase gate, as described in Wu because the modification facilitates the formation of contacts. (Wu Para [0024])
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chen; Aaron (US-20170301683-A1), CHUANG; Chiang-Ming (US-20170110466-A1), SU; CHIEN-SHENG (US-20170125429-A1), Bo; Xiangzheng (US-9966380-B1), Huang; Nan-Yuan (US-20200111802-A1), WU; Wei-Cheng (US-20210217892-A1), CHEN; Jhih-Bin (US-20210376120-A1), Lin; Yi-Chuan (US-20220320315-A1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAIME LYNN SPRENGER whose telephone number is (571)272-8444. The examiner can normally be reached Monday - Thursday, 7:30a.m. - 5:00p.m. ET..
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/JAIME LYNN SPRENGER/ Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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