DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/30/2023 has been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1,2, 9-13 are rejected under 35 U.S.C. 103 as being unpatentable over Roizin (US 20090212342) , and further in view of Kadosh (US 5909622).
Regarding claim 1, Roizin teaches a method for fabricating semiconductor device in fig. 4, comprising:
providing a substrate (101A) having a high-voltage (HV) region (refer to HV- region) and a low-voltage (LV) region (refer to LV- region) (see par. 41);
forming a first gate structure (refer to gate 121A as labelled C150A in fig. 4) on the HV region (see par. 41) and a second gate structure (refer to gate 120-1A) on the LV region (see par. 41);
forming a first lightly doped drain (LDD) (refer to left/right LDD 150A) adjacent to one side of the first gate structure (refer to left side of gate 121A) and a second LDD (refer to right/left LDD 150A) adjacent to another side of the first gate structure (refer to right side of gate 121A); and
forming a third lightly doped drain (LDD) adjacent to one side of the second gate structure and a fourth LDD adjacent to another side of the second gate structure (refer to left and right LDD 110) (see fig. 4).
Roizin does not show the first LDD and the second LDD are asymmetrical and wherein the third LDD and the fourth LDD are asymmetrical and the second LDD and the third LDD are symmetrical.
Kadosh teaches the same field of an endeavor wherein a gate comprising: lateral area of LDD regions (124) are asymmetrical (see fig. 4g).
Thus, it would have been obvious to one having ordinary skill in the art before the invention was made to include a gate comprising lateral asymmetrical LDD regions as taught by Kadosh in the teaching of Roizin in order to reduce source-side resistance to enhance drive current--a desirable outcome for high speed circuits (see Abstract).
Replacing the gate structure of Kadosh with asymmetrical lateral LDD regions in each of the HV gate and LV gate of Roizin. Thus, the first HV gate and the second LV gate of Roizin comprising: the first LDD and the second LDD are asymmetrical (refer to lateral LDDs of the gate) and wherein the third LDD and the fourth LDD are asymmetrical (refer to lateral LDDs of the gate) and the second LDD and the third LDD are symmetrical (NOTE: it is considered to be the LDD of each gate that have the same size).
Regarding claim 9, Roizin teaches a semiconductor device in fig. 4, comprising:
a substrate (101A) having a high-voltage (HV) region (refer to HV region) and a low-voltage (LV) region (refer to LV region; see par. 41);
a first gate structure (refer to 121A) on the HV region and a second gate structure (refer to 120-1A) on the LV region (see par. 41);
a first lightly doped drain (LDD) adjacent to one side of the first gate structure and a second LDD adjacent to another side of the first gate structure (refer to left/right sides LDD 150A); and
a third lightly doped drain (LDD) adjacent to one side of the second gate structure and a fourth LDD adjacent to another side of the second gate structure (refer to left and right sides of LDD 110A).
Roizin does not show the first LDD and the second LDD are asymmetrical and wherein the third LDD and the fourth LDD are asymmetrical and the second LDD and the third LDD are symmetrical.
Kadosh teaches the same field of an endeavor wherein a gate comprising: lateral area of LDD regions (124) are asymmetrical (see fig. 4g).
Thus, it would have been obvious to one having ordinary skill in the art before the invention was made to include a gate comprising lateral asymmetrical LDD regions as taught by Kadosh in the teaching of Roizin in order to reduce source-side resistance to enhance drive current--a desirable outcome for high speed circuits (see Abstract).
Replacing the gate structure of Kadosh with asymmetrical lateral LDD regions in each of the HV gate and LV gate of Roizin. Thus, the first HV gate and the second LV gate of Roizin comprising: the first LDD and the second LDD are asymmetrical (refer to lateral LDDs of the gate) and wherein the third LDD and the fourth LDD are asymmetrical (refer to lateral LDDs of the gate) and the second LDD and the third LDD are symmetrical (NOTE: it is considered to be the LDD of each gate that have the same size).
Regarding claim 10, Roizin and Kadosh teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, fig. 4 of Roizin teaches
a first source/drain (S/D) region (refer to right side region D150A) on one side of the first gate structure (refer to C150A); a second S/D region (refer to source region of C150A or drain region of C110A is between C150A and C110A) between the first gate structure and the second gate structure; and a third S/D (refer to S110A) on another side of the second gate structure (refer to left side of C110A).
Regarding claim 11, Roizin and Kadosh teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, fig. 4 of Roizin teaches the first S/D region (refer to D150A), the second S/D region (refer to S150A or D110A), and the third S/D region (refer to S110A) are symmetrical.
Regarding claim 12, Roizin and Kadosh teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, fig. 4 of Roizin teaches the first LDD and the second LDD comprise same concentration (refer to the LDDs of HV MOSFET are doped with a second doping concentration in see claim 4).
Regarding claim 13, Roizin and Kadosh teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, fig. 4 of Roizin teaches the third LDD and the fourth LDD comprise same concentration (refer to the LDDs of LV MOSFET are doped with a first doping concentration in see claim 4).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Roizin in view of Kadosh as applied to claim 1 above, and further in view of Toh (US 2017/0084736).
Regarding claim 8, Roizin and Kadosh teach all the limitations of the claimed invention for the same reasons as set forth above except for the substrate comprises a silicon-on-insulator (SOI) substrate.
Toh teaches the same field of an endeavor wherein the substrate comprises a silicon-on-insulator (SOI) substrate (see par. 16).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the substrate comprises a silicon-on-insulator (SOI) substrate as taught by Toh in the combined teaching of Roizin and Kadosh in order to reduce parasitic capacitance and improving efficiency.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Roizin in view of Kadosh as applied to claim 9 above, and further in view of Toh (US 2017/0084736).
Regarding claim 14, Roizin and Kadosh teach all the limitations of the claimed invention for the same reasons as set forth above except for the substrate comprises a silicon-on-insulator (SOI) substrate.
Toh teaches the same field of an endeavor wherein the substrate comprises a silicon-on-insulator (SOI) substrate (see par. 16).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the substrate comprises a silicon-on-insulator (SOI) substrate as taught by Toh in the combined teaching of Roizin and Kadosh in order to reduce parasitic capacitance and improving efficiency.
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “forming a first spacer adjacent to the first gate structure and a second spacer adjacent to the second gate structure; performing a first ion implantation process to form the first LDD and the second LDD performing a second ion implantation process to form the third LDD and the fourth LDD; forming a third spacer adjacent to the first spacer and a fourth spacer adjacent to the second spacer; and forming a first source/drain (S/D) region on one side of the first gate structure, a second S/D region between the first gate structure and the second gate structure, and a third S/D on another side of the second gate structure”. Claims 3-7 include all of the limitations of claim 2.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Niki Tram Nguyen whose telephone number is (571) 272-5526. The examiner can normally be reached on 6:00am-4:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke can be reached on (703)872-9306. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NIKI H NGUYEN/ Primary Examiner, Art Unit 2818
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