DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
The amended title overcomes the previous rejection.
The amendment to claim 8 overcomes the objection.
The 112 rejections are overcome by the claim amendments.
The applicant asserts that “Chen fails to cure the deficiencies in Li, Saito and Jia because Chen does not teach or suggest, "wherein a first edge of the gate insulating layer, which is a straight line, obliquely intersects a first edge of the first electrode facing the gate electrode in a plan view" of Claims 1 and 9.” (Response page 12). The examiner disagrees. Li discloses at [0074] that “[s]hapes of the second through holes 1042 and the third through holes 1051 are rectangular, polyline-shaped, wave-shaped, or arc-shaped.” “Polyline” is defined as “a continuous line that is composed of one or more connected straight line segments, which, together, make up a shape.” (https://www.webopedia.com/definitions/polyline/.) In a case where the holes (edges of the holes) are poly-line shaped, there will be line segments of different angle that form a shape. The majority of the lines will not be horizontal, as each line segment has a different inclination (otherwise it would not be a separate line segment). Thus there is a likelihood that in using a polyline shape, there will be an oblique intersection with the first electrode. See the rejections below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 2 are rejected under 35 U.S.C. 103 as being unpatentable over Li, CN 113629151 A, or over its corresponding US publication, US 2024/0030239 A1. As these have the same disclosure, the citations in this action will be to the US publication, but all references below to “Li” refer to both documents.
Claim 1: Li discloses
a substrate (106);
a semiconductor layer (101) disposed on the substrate and including a channel area (1101), a first conductive area (1012b) positioned at a first side of the channel area, and a second conductive area (1012a) positioned at a second side of the channel area;
a gate insulating layer (102) covering areas (such as channel region 1011) of the semiconductor layer other than the first conductive area and the second conductive area;
a gate electrode (1033) disposed on the gate insulating layer and overlapping the channel area in a plan view;
and a first electrode (1032) disposed on the gate insulating layer and in contact with a portion of the first conductive area,
wherein a first edge of the gate insulating layer (edge in the hole 1051), which is a straight line, obliquely intersects a first edge of the first electrode facing the gate electrode in a plan view (see other overlap in FIG. 1).
Li discloses at [0074] that “[s]hapes of the second through holes 1042 and the third through holes 1051 are rectangular, polyline-shaped, wave-shaped, or arc-shaped.” “Polyline” is defined as “a continuous line that is composed of one or more connected straight line segments, which, together, make up a shape.” (https://www.webopedia.com/definitions/polyline/.) In a case where the holes (edges of the holes) are poly-line shaped, there will be line segments of different angle that form a shape. As this shape is listed in addition to rectangular, most of such line segments will not simply be horizontal in the figure, otherwise it would be a rectangle or close to a rectangle. The majority of the lines will not be horizontal, as each line segment has a different inclination (otherwise they would not be separate line segments). Thus it would have been likely that the first edge of the first facing the gate electrode obliquely intersects the first edge of the gate insulating layer in the case of using one of these disclosed hole shapes. For this reason it would have been obvious as the most likely outcome and obvious to try in light of the disclosure.
The examiner here uses the definition of “obliquely” as “neither parallel nor at a right angle to a specified or implied line; slanting.” (https://www.google.com/search?q=define:oblique). This corresponds to neither vertical nor horizontal in FIG. 2.
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Note that there is an inconsistency between FIGS. 1 and 2 of Li; in FIG. 1, electrode 1031 is over 105, while in FIG. 2 it is over 104. These are a source and a drain that are symmetric to each other, and thus this inconsistency has no bearing on the substance of the rejection.
Claim 2: the gate electrode and the first electrode face each other in a first direction (horizontal, FIG. 2), wherein the first edge of the first electrode extends in a second direction (vertical, FIG. 2) perpendicular to the first direction, and wherein the first edge of the gate insulating layer extends obliquely to the first direction and the second direction in a plan view (as explained regarding claim 1 above).
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Jia, US 2022/0293711 A1.
Claim 9: Li discloses in the background of the invention that the claimed transistor is for a display, but does not disclose the details of the display. However, those in the art would have understood that the basic recited elements would have been in a display for the invention of Li. See e.g. Jia, which discloses
a substrate (100) including a display area (Q1, FIG. 1) on which sub-pixels are arranged;
a circuit layer (105-134) disposed on the substrate;
and a light emitting element layer (113-118) disposed on the circuit layer and including light emitting elements disposed in areas corresponding to the sub-pixels, respectively, wherein the circuit layer includes pixel driving units electrically connected to the light emitting elements, respectively, and each of the pixel driving units includes a thin film transistor (104-111).
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Those in the art would have expected that a display using the transistor of Li would likely have had these basic elements, as they were ubiquitous in the art.
The TFT of Li (background of the invention) includes
a semiconductor layer (101) disposed on the substrate and including a channel area (1101), a first conductive area (1012b) positioned at first side of the channel area, and a second conductive area (1012a) positioned at a side of the channel area, the second side being an opposite side to the first side in a first direction;
a gate insulating layer (102) covering areas other than the first conductive area and the second conductive area;
a gate electrode (1033) disposed on the gate insulating layer and overlapping the channel area in a plan view;
and a first electrode (1032) disposed on the gate insulating layer and in contact with a portion of the first conductive area,
and wherein a first edge of the gate insulating layer (edge in the hole 1051), which is a straight line, obliquely intersects a first edge of the first electrode facing the gate electrode in a plan view (see other overlap in FIG. 1).
Li discloses at [0074] that “[s]hapes of the second through holes 1042 and the third through holes 1051 are rectangular, polyline-shaped, wave-shaped, or arc-shaped.” “Polyline” is defined as “a continuous line that is composed of one or more connected straight line segments, which, together, make up a shape.” (https://www.webopedia.com/definitions/polyline/.) In a case where the holes (edges of the holes) are poly-line shaped, there will be line segments of different angle that form a shape. As this shape is listed in addition to rectangular, most of such line segments will not simply be horizontal in the figure, otherwise it would be a rectangle or close to a rectangle. The majority of the lines will not be horizontal, as each line segment has a different inclination (otherwise they would not be separate line segments). Thus it would have been likely that the first edge of the first facing the gate electrode obliquely intersects the first edge of the gate insulating layer in the case of using one of these disclosed hole shapes. For this reason it would have been obvious as the most likely outcome and obvious to try in light of the disclosure.
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Claim 10: the gate electrode and the first electrode face each other in the first direction (horizontal, FIG. 2), wherein the first edge of the first electrode extends in a second direction (vertical, FIG. 2) perpendicular to the first direction, and wherein the first edge of the gate insulating layer extends obliquely with respect to the first direction and the second direction in a plan view (as explained regarding claim 1 above).
Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Saito, US 2011/0042674 A1. Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Jia and Saito.
Claims 3 and 11 recite that a length of an edge of the gate insulating layer meeting a side wall of the first electrode is greater than a thickness of the gate insulating layer. The recited edge could be considered either the end of 1052, or the end of 1052 plus the two side lengths of 1052, or the sum of where all these edges are for all of the holes 1052 under the electrode 1032. The length of the end of one hole 1052 is W2, which is 2-5 microns ([0067]), which is a much larger dimension than is used for gate insulating layers in such TFTs. Li does not disclose the thickness of the gate insulating layer, but See Saito, [0123], which discloses a gate insulating layer thickness of 0.4 microns. Those in the art would have known that the gate insulating layer would have been much smaller than the disclosed length of the edge of the first electrode 1032 disposed on a side wall of the gate insulating layer 102.
Claims 4 and 12: Li discloses comprising a second electrode disposed (1031) on the gate insulating layer and in contact with a portion of the second conductive area (in 1041), wherein a second edge of the second electrode facing the gate electrode obliquely intersects a second edge of the gate insulating layer in a plan view. “Shapes of the second through holes 1042 and the third through holes 1051 are rectangular, polyline-shaped, wave-shaped, or arc-shaped.” [0072]. As explained above with respect to claim 1, this would likely have resulted in an oblique intersection.
Claims 5 and 13: the gate electrode and the second electrode face each other in the first direction (horizontal, FIG. 2), wherein the second edge of the second electrode extends in the second direction (vertical), and wherein the second edge of the gate insulating layer extends obliquely with respect to the first direction and the second direction in a plan view (as explained above with respect to claim 1).
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Saito and Chen, CN 114784113, or over its corresponding US publication, US 2023/0343837 A1. As these have the same disclosure, the citations in this action will be to the US publication, but all references below to “Chen” refer to both documents. Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Jia, Saito, and Chen.
Claim 6: Chen discloses a first through hole (212C1, FIG. 3) formed through a portion of the first conductive area, wherein the first through hole is disposed between the gate electrode (23A) and the first electrode (23B) and is disposed adjacent to the first electrode, and wherein the first conductive area includes: a first contact area in contact with the first electrode; a first pass area disposed between the first contact area and the first through hole; and a first main area disposed between the first through hole and the channel area.
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Chen discloses that the through hole 212C “is used to prevent carriers in the lap portion 212A from diffusing toward the active segment 211 after the active layer 21 is subject to the conducting process, thus improving stability of the thin film transistor layer 20.” [0065]. It would have been obvious to have had such a through hole in Li for this benefit.
Claim 7: Chen discloses a second through hole (212C2) formed through a portion of the second conductive area, wherein the second through hole is disposed between the gate electrode and the second electrode (23C) in the first direction and is disposed adjacent to the second electrode, and wherein the second conductive area includes: a second contact area in contact with the second electrode; a second pass area disposed between the second contact area and the second through hole; and a second main area disposed between the second through hole and the channel area (FIG. 7B). See the annotated FIG. 7D above with respect to claim 6; note that the source and drain structures of Chen are symmetric.
Claim 14: Chen discloses a first through hole (212C1, FIG. 3) formed through a portion of the first conductive area, and a second through hole (212C2) formed through a portion of the second conductive area, wherein the first through hole is disposed between the gate electrode (23A) and the first electrode (23B), wherein the second through hole is disposed between the gate electrode (23A) and the second electrode (23C),
wherein the first conductive area includes: a first contact area in contact with the first electrode; a first pass area disposed between the first contact area and the first through hole; and a first main area disposed between the first through hole and the channel area.
and wherein the second conductive area includes: a second contact area in contact with the second electrode; a second pass area disposed between the second contact area and the second through hole; and a second main area disposed between the second through hole and the channel area (FIG. 7B).
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The above annotated figure shows the first conductive area; note that the first and second conductive areas are symmetric and have the same structures.
Claim 14: the one thin film transistor further includes: a first through hole formed through a portion of the first conductive area; and a second through hole formed through a portion of the second conductive area, wherein the first through hole is disposed between the gate electrode and the first electrode, wherein the second through hole is disposed between the gate electrode and the second electrode, wherein the first conductive area includes: a first contact area in contact with the first electrode; a first pass area disposed between the first contact area and the first through hole; and a first main area disposed between the first through hole and the channel area, and wherein the second conductive area includes: a second contact area in contact with the second electrode; a second pass area disposed between the second contact area and the second through hole; and a second main area disposed between the second through hole and the channel area.
Claim 15: Chen discloses that the circuit layer further includes: a light blocking electrode (40) disposed between the substrate and the semiconductor layer to overlap the semiconductor layer in a plan view (FIG. 7D); a buffer layer (30) disposed between the light blocking electrode and the semiconductor layer to cover the light blocking electrode in a plan view; an interlayer insulating layer (50) disposed on the buffer layer and covering the thin film transistor; wherein the interlayer insulating layer is in contact with the buffer layer through each of the first through hole and the second through hole (FIG. 7D).
Chen does not disclose the claimed via layer, as the light emitting element is not shown and thus the connection to the light emitting element is also not shown. However, Jia discloses a via layer (116, FIG. 3) disposed on the interlayer insulating layer (134). These were ubiquitous and would have been obvious to connect the TFT to the light emitting element using a via.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Saito, Chen, and Cho, US 2010/0001284 A1. Chen discloses at [0097] “[p]atterning the insulating layer 22 and the buffer layer 30, wherein a first via hole, a second via hole and a third via hole are formed on the insulating layer 22, and a fourth via hole corresponding to the third via hole is formed on the buffer layer 30. Meanwhile, subjecting the active layer 21 to a first conducting process, so as to form a conductor segment 212 located on both sides of the active segment 211”. Thus the conductive region is formed through the hole in layer 22, likely through implantation of dopants. Chen shows that the conductive (doped) region aligns with the edge of layer 22 on the inside. It was known in the art that it could also align with the outside edge. See e.g. Cho FIG. 1E, [0027], which shows doped regions 132a and 132b that align with both inside and outside edges of openings 133a and 133b.
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It would have been obvious for such a structure to be in Chen or Li as a known outcome of implantation. Also, it would not affect the functioning of the device, as the source and drain contacts would still contact an implanted portion. Thus in light of Cho, the semiconductor layer would further include: a first non-active area (the part of 212 outside 22 on the left in FIG. 7D) connected to the first contact area, covered with the gate insulating layer, and overlapping the first electrode; and a second non-active area (the part of 212 outside 22 on the right in FIG. 7D) connected to the second contact area, covered with the gate insulating layer, and overlapping the second electrode.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Takenaka, JP H10-270699 A.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER BRADFORD/Primary Examiner, Art Unit 2897
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