DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species I, claims 1,2,4,7,8,10,15,17,18,23,25,30,33,35,36, and 70 in the reply filed on 04/17/2026 is acknowledged. Applicant indicates that the election was made with traverse but no argument as to why it should be traversed is given in the arguments. This is not found persuasive.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 4, 10, 30, 33, 35, and 70 are rejected under 35 U.S.C. 102 as being anticipated by Balaraman et al. ( US 2025/0125231 A1; hereinafter Balaraman )
Regarding claim 1, Balaraman teaches a power semiconductor device assembly ( Fig. 8 ) comprising: a semiconductor device package ( Fig. 8: semiconductor device package 940 ) with one or more terminals ( Fig. 8: wire bonds 942 ), wherein the semiconductor device package comprises one or more wide bandgap semiconductor die ( Fig. 4: example semiconductor die 400 includes a wide bandgap substrate 412 and epitaxial layer 414 ); a support structure ( Fig. 8: conductive submount 902 ), wherein the semiconductor device package ( Fig. 8 #940 ) is mounted onto the support structure ( Fig. 8 #902 ); and an underfill structure ( Fig. 8: encapsulating material 944 ), wherein the underfill structure is at least partially on the support structure ( Fig. 8 #902 ) and the semiconductor device package ( Fig. 8 #904 ).
Regarding claim 2, Balaraman teaches the power semiconductor device assembly of claim 1 ( as discussed above), wherein the underfill structure ( Fig. 8 #944 ) is on the support structure ( Fig. 8 #902 ) and extends to a height at least partially contacting the semiconductor device package ( Fig. 8 #940 ).
3. (withdrawn) The power semiconductor device assembly of claim 1, wherein the underfill structure is on the support structure and extends to a height at least partially contacting the one or more terminals.
Regarding claim 4, Balaraman teaches the power semiconductor device assembly of claim 1 ( as discussed above ), wherein the underfill structure ( Fig. 8 #944 ) is a composite epoxy material ( [0063] An encapsulating material 944 (e.g., epoxy mold compound (EMC)) may fill the space around the semiconductor die 904 and the submount 902 ).
Regarding claim 10, Balaraman teaches the power semiconductor device assembly of claim 1 ( as discussed above), wherein the underfill structure comprises a material having a coefficient of thermal expansion in a range of about 16 ppm/C to about 17 ppm/C ( this thermal expansion value is inherent to UF-MC7883-FP produced by Al Technology, Inc. ).
Regarding claim 30, Balaraman teaches the power semiconductor device assembly of claim 1 ( as discussed above ), wherein the one or more wide bandgap semiconductor die comprise silicon carbide ( [0021] the semiconductor die may include, for instance, wide bandgap semiconductor devices, such as silicon carbide-based semiconductor devices (e.g., MOSFETs, Schottky diodes), Group III nitride-based semiconductor devices (e.g., high electron mobility transistor (HEMT) devices), etc. ), wherein the semiconductor device package comprises a silicon carbide-based MOSFET or a silicon carbide- based Schottky diode ( as discussed above ).
Regarding claim 33, Balaraman teaches the power semiconductor device assembly of claim 1 ( as discussed above ), wherein the one or more wide bandgap semiconductor die comprise a Group III-nitride ( [0021] the semiconductor die may include, for instance, wide bandgap semiconductor devices, such as silicon carbide-based semiconductor devices (e.g., MOSFETs, Schottky diodes), Group III nitride-based semiconductor devices (e.g., high electron mobility transistor (HEMT) devices), etc. ), wherein the semiconductor device package comprises a Group III nitride-based high electron mobility transistor ( as discussed above).
Regarding claim 35, Balaraman teaches the power semiconductor device assembly of claim 1 ( as discussed above), wherein the semiconductor device package is a power module ( Fig. 9 power module 1000 ).
Regarding claim 70, Balaraman teaches a method of forming a power semiconductor device assembly ( Fig. 11 ), the method comprising: providing a semiconductor device package ( [0068] FIG. 11 depicts an example method 1200 of providing a semiconductor device package according to example aspects of the present disclosure ) with one or more terminals on a support structure ( [0072] At 1204, the method includes directly bonding the metallization layer to a submount using a direct bonding process ), wherein the semiconductor device package comprises one or more wide bandgap semiconductor die ( [0077] The semiconductor die includes a wide bandgap semiconductor material ) ; and providing an underfill structure ( Fig. 8 #944 ) at least partially on the semiconductor device package ( Fig. 8 #904 ) and the support structure ( Fig. 8 #902 ).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under U.S.C. 103 as being unpatentable over Balaraman et al.; US 2025/0125231 A1; 10/2023 in view of
Claim 7: Balaraman discloses the power semiconductor device assembly of claim 1 ( as discussed above ).
Balaraman does not appear to disclose the underfill structure comprises a material having a comparative tracking index greater than about 600.
However, Thomas teaches the underfill structure comprises a material having a comparative tracking index greater than about 600 ( page 2, right column, after Fig. 4, “Small power packages with short insulation distances often require encapsulants of material group I with a CTI larger than 600.” ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Thomas with Balaraman to implement the underfill structure comprises a material having a comparative tracking index greater than about 600 because this range enhances reliability in a high stress packages.
Claim 8 is rejected under U.S.C. 103 as being unpatentable over Balaraman et al.; US 2025/0125231 A1; 10/2023 in view of Liu et al., “Packaging of Integrated Power Electronics Modules Using Flip-Chip Technology,” APEC 2000. Fifteenth Annual IEEE Applied Power Electronics Conference and Exposition, Vol. 1, 2000, pages 290-296.
Claim 8: Balaraman discloses the power semiconductor device assembly of claim 1 ( as discussed above ).
Balaraman does not appear to disclose the underfill structure comprises a material having a first coefficient of thermal expansion that is less than a second coefficient of thermal expansion of the support structure, wherein the first coefficient of thermal expansion is greater than a third coefficient of thermal expansion associated with the semiconductor device package.
However, Liu teaches the underfill structure ( Fig. 1 underfill ) comprises a material having a first coefficient of thermal expansion ( Table 1, Epoxy, Thermal Conductivity = 0.23 ) that is less than a second coefficient of thermal expansion ( Table 1, Underfill D, CTE = 23 ) of the support structure ( Table 1, Solder, CTE = 25 ), wherein the first coefficient of thermal expansion ( as discussed above ) is greater than a third coefficient of thermal expansion associated ( Table 1, Silicon, CTE = 4.1 ) with the semiconductor device package ( Fig. 1 DBC substrate ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Liu with Balaraman to implement the underfill structure comprises a material having a first coefficient of thermal expansion that is less than a second coefficient of thermal expansion of the support structure, wherein the first coefficient of thermal expansion is greater than a third coefficient of thermal expansion associated with the semiconductor device package because with the underfill having a lower CTE than the substrate strain is reduced lower the risk of cracks.
Claims 11, 15, 17, and 36 are rejected under U.S.C. 103 as being unpatentable over Balaraman et al.; US 2025/0125231 A1; 10/2023 in view of Gomez; US 2009/0127676 A1; 11/2007
Claim 11: Balaraman discloses the power semiconductor device assembly of claim 1 ( as discussed above ).
Balaraman does not appear to disclose the power semiconductor device assembly further comprises an attach layer between the semiconductor device package and the support structure, wherein the underfill structure is on the attach layer.
However, Gomez teaches the power semiconductor device assembly further comprises an attach layer ( Figs. 9 and 10 attach layer 11 ) between the semiconductor device package and the support structure ( Fig. 9 and 10 support structure 9 ), wherein the underfill structure is on the attach layer ( [0047] the molding material 17 therefore serves as an underfill material, which provides the advantage of providing adhesion between the active surfaces of die 13 to the die attach pad 11 and protection of solder joints of solder bumps 12 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Gomez with Balaraman to implement the power semiconductor device assembly further comprises an attach layer between the semiconductor device package and the support structure, wherein the underfill structure is on the attach layer because this approach provides mechanical support and thermal management.
Claim 15: Balaraman and Gomez disclose the power semiconductor device assembly of claim 11 ( as discussed above).
Balaraman does not appear to disclose the attach layer comprises a plurality of attach structures, the attach layer comprising a gap between two or more of the attach structures.
However, Gomez teaches the attach layer ( Figs. 9 and 10 #11 ) comprises a plurality of attach structures ( as shown in Figs. 9 and 10 ), the attach layer comprising a gap between two or more of the attach structures ( as shown in Figs. 9 and 10 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Gomez with Balaraman to implement the attach layer comprises a plurality of attach structures, the attach layer comprising a gap between two or more of the attach structures because this approach provides stress distribution and reliability.
Claim 17: Balaraman and Gomez disclose the power semiconductor device assembly of claim 15 ( as discussed above).
Balaraman does not disclose the underfill structure at least partially fills the gap between two or more of the attach structures.
However, Gomez teaches the underfill structure at least partially fills the gap between two or more of the attach structures ( [0047] the molding material 17 therefore serves as an underfill material, which provides the advantage of providing adhesion between the active surfaces of die 13 to the die attach pad 11 and protection of solder joints of solder bumps 12 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Gomez with Balaraman to implement the underfill structure at least partially fills the gap between two or more of the attach structures because distributing these stresses more evenly reduces the risk of cracks or delamination.
Claim 36: Balaraman discloses a power semiconductor device assembly ( Fig. 8 ) comprising: a semiconductor device package ( Fig. 8: semiconductor device package 940 ) with one or more terminals ( Fig. 8: wire bonds 942 ), wherein the semiconductor device package comprises one or more wide bandgap semiconductor die ( Fig. 4: example semiconductor die 400 includes a wide bandgap substrate 412 and epitaxial layer 414 ); a support structure ( Fig. 8: conductive submount 902 ).
Balaraman does not appear to disclose a patterned attach layer between the semiconductor device package and the support structure, wherein the patterned attach layer comprises a plurality of attach structures, the patterned attach layer comprising a gap between two or more of the attach structures.
However, Gomez teaches a patterned attach layer ( Figs. 9 and 10 #11 ) between the semiconductor device package and the support structure ( Figs. 9 and 10 #9 ), wherein the patterned attach layer comprises a plurality of attach structures ( as shown in Figs. 9 and 10 ), the patterned attach layer comprising a gap between two or more of the attach structures ( as shown in Figs. 9 and 10 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Gomez with Balaraman to implement a patterned attach layer between the semiconductor device package and the support structure, wherein the patterned attach layer comprises a plurality of attach structures, the patterned attach layer comprising a gap between two or more of the attach structures because this approach mechanically secures, thermally couples and electrically connects the components.
Claims 18 and 23 are rejected under U.S.C. 103 as being unpatentable over Balaraman et al.; US 2025/0125231 A1; 10/2023 in view of Hembree et al.; US 2005/0277231 A1; 06/2004
Claim 18: Balaraman discloses the power semiconductor device assembly of claim 1 ( as discussed above).
Balaraman does not appear to disclose a dam structure, wherein the dam structure is on the support structure and at least partially surrounds the underfill structure.
However, Hembree teaches a dam structure ( Fig. 6B structures 90A and 90B form a dam structure ), wherein the dam structure ( as discussed above) is on the support structure ( Fig. 6B carrier substrate face 12 ) and at least partially surrounds the underfill structure ( Fig. 4 underfill structure 50 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Hembree with Balaraman to implement a dam structure, wherein the dam structure is on the support structure and at least partially surrounds the underfill structure because this provides flow control and uniformity and improved defect detection.
Claim 23: Balaraman and Hembree disclose the power semiconductor device assembly of claim 18 ( as discussed above).
Balaraman does not appear to disclose the dam structure is an epoxy material, wherein the epoxy material has a viscosity that is less than a viscosity of the underfill structure.
However, Hembree teaches the dam structure is an epoxy material ( [0039] surface level 62 of the liquid photopolymer resin 60. The laser 108 scans the liquid photopolymer resin 60 in selected portions to at least partially cure (partially polymerize) the liquid photopolymer resin 60 to form structures 90A ), wherein the epoxy material has a viscosity ( it will be less since it is cured ) that is less than a viscosity of the underfill structure ( [0011] The cured photopolymer material may form an underfill structure between the at least one semiconductor die and the carrier substrate ) .
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Hembree with Balaraman to implement the dam structure is an epoxy material, wherein the epoxy material has a viscosity that is less than a viscosity of the underfill structure because a dam with lower viscosity can be more easily dispensed and shaped.
Claim 25 is rejected under U.S.C. 103 as being unpatentable over Balaraman et al.; US 2025/0125231 A1; 10/2023 in view of Troska et al.; US 2023/0343661 A1; 04/2022
Claim 25: Balaraman discloses the power semiconductor device assembly of claim 1 ( as discussed above ).
Balaraman does not appear to disclose the support structure is a heatsink.
However, Troska teaches the support structure is a heatsink ( [0014] hereon and to efficiently extract heat away from these power semiconductor devices during operation. The carrier 102 may be configured to be directly mounted to a support structure, such as a heat sink ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Troska with Balaraman to implement the support structure is a heatsink because this helps to better manage the heat generated during operation.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIMBERLY N FREY whose telephone number is (571)272-5068. The examiner can normally be reached Monday - Friday 7:30 am - 5 pm.
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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