DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of 1-17 in the reply filed on 2/24/26 is acknowledged. Applicant has cancelled non-elected Invention and added claims 21-23.
Information Disclosure Statement
The information disclosure statements (IDS) were submitted on 11/14/24 and 2/25/26. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-17 and 21-23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US PGPub 2022/0285514, hereinafter referred to as “Chen”)
Chen discloses the semiconductor method as claimed. See figures 1A-20 and corresponding text, where Chen teaches, in claim 1, a method of forming a gate stack of a multigate device, the method comprising:
forming a gate dielectric (400) over a channel layer (120) (figures 2 and 3; [0031], [0040-0042]); and
forming a gate electrode (140) over the gate dielectric (400) by: (figure 2; [0033])
forming a work function layer (410) over the gate dielectric (400) (figure 3; [0043]),
forming a cap (420) over the work function layer (410), wherein the forming the cap includes forming a metal nitride layer (420) over the work function layer (410) (figure 3; [0044]) and forming a silicon-comprising layer (430) over the metal nitride layer (420), (figure 3; [0045]) and
forming a fluorine-free tungsten layer (300) over the silicon-comprising layer (430) of the cap without breaking vacuum, wherein the forming the fluorine-free tungsten layer (300) over the silicon-comprising layer (430) includes co-flowing a tungsten-comprising precursor and a hydrogen-comprising precursor (figure 5; [0050-0051]).
Chen teaches, in claim 2, wherein:
the tungsten-comprising precursor is WCl5 and the hydrogen-comprising precursor is H2 ([0050-0051]).
Chen teaches, in claim 3, wherein the metal nitride layer includes titanium and nitrogen, and the work function layer includes titanium, aluminum, and carbon ([0043-0044]).
Chen teaches, in claim 4, wherein the forming the metal nitride layer includes: forming a first metal nitride sublayer over the work function layer ([0043-0044]); and
forming a second metal nitride sublayer over the first metal nitride sublayer ([0043-0044]).
Chen teaches, in claim 5, wherein the second metal nitride sublayer is formed over the first metal nitride sublayer after breaking vacuum ([0043-0044]).
Chen teaches, in claim 6, wherein: (figures 1A and 1B; [0024-0027])
the channel layer (120) is a first channel layer;
the gate dielectric (400) is formed over the first channel layer (120) and a second channel layer (120); and
the method further includes forming the gate dielectric (400) and the gate electrode (140) in a gate opening that exposes the first channel layer and the second channel layer, wherein:
the gate dielectric (400), the work function layer (410), and the cap (420) fill a gap between the first channel layer (120) and the second channel layer (120), and
the gate dielectric (400), the work function layer (410), the cap (420), and the fluorine-free tungsten layer (300) fill a portion of the gate opening over the first channel layer (120).
Chen teaches, in claim 7, wherein the gap is about 10 nm ([0054]).
Chen teaches, in claim 8, wherein:
the channel layer (120) is a first channel layer;
the gate dielectric (400) is formed over the first channel layer (120) and a second channel layer (120); and
the method further includes forming the gate dielectric (400) and the gate electrode (140) in a gate opening that exposes the first channel layer (120) and the second channel layer (120), wherein:
the gate dielectric (400) and the work function layer (420) fill a gap between the first channel layer (120) and the second channel layer (120), and the gate dielectric (400), the work function layer (410), the cap, and the fluorine-free tungsten layer (300) fill a portion of the gate opening over the first channel layer (figure 5; [0050-0051]).
Chen teaches, in claim 9, wherein a thickness of the fluorine-free tungsten layer is greater than a thickness of the silicon-comprising layer (figure 5; [0050-0051]) .
Chen teaches, in claim 10, wherein the work function layer has an aluminum content that is about 20% to about 30% and a thickness that is about 25 A to about 30 A (figure 3; [0042-0044], [0049]).
Chen teaches, in claim 11, a method of forming a gate stack of a multigate device, the method comprising: (figures 1A-1C and figures 3-5; [0024], [0041-0052]);
forming an interfacial layer over a first channel layer and a second channel layer, wherein the first channel layer is disposed over the second channel layer ([0024]);
forming a high-k dielectric layer (400) over the interfacial layer ([0024], [0041-0052]);
forming a titanium aluminum carbide layer (410) over the high-k dielectric layer;
forming a titanium nitride layer (420) over the titanium aluminum carbide layer;
forming a silicon layer (430) over the titanium nitride layer; and
co-flowing WCl5 and H2 into a process chamber to form an in-situ fluorine-free tungsten layer over the silicon layer (figure 5; [0050-0051]).
Chen teaches, in claim 12, wherein the in-situ fluorine-free tungsten layer is formed directly on the silicon layer (figure 5; [0050-0051]).
Chen teaches, in claim 13, wherein the titanium nitride layer is a first titanium nitride layer, the method further comprising forming a second titanium nitride layer over the silicon layer, wherein the in-situ fluorine-free tungsten layer is formed directly on the second titanium nitride layer (figure 3; [0041-0052]).
Chen teaches, in claim 14, wherein the forming the titanium aluminum carbide layer over the high-k dielectric layer includes:
performing an atomic layer deposition process;
and tuning parameters of the atomic layer deposition process to provide the titanium aluminum carbide layer with an aluminum content that is about 20% to about 30% and a thickness that is about 25 A to about 30 A (figure 3; [0042-0044], [0049]).
Chen teaches, in claim 15, wherein the forming the titanium nitride layer over the titanium aluminum carbide layer includes:
forming a first titanium nitride sublayer over the titanium aluminum carbide layer; and
forming a second titanium nitride sublayer over the first titanium nitride sublayer (figure 3; [0042-0044]).
Chen teaches, in claim 16, wherein the forming the titanium nitride layer over the titanium aluminum carbide layer further includes exposing the first titanium nitride sublayer to an oxygen ambient before forming the second titanium nitride sublayer (figure 3; [0042-0044]).
Chen teaches, in claim 17, wherein the interfacial layer, the high-k dielectric layer, and the titanium aluminum carbide layer fill a spacing between the first channel layer and the second channel layer (figure 3; [0042-0044]).
Chen teaches, in claim 21, a method of forming a gate stack of a multigate device, the method comprising:
depositing a titanium aluminum carbide layer (410) around a semiconductor layer (120); depositing a titanium nitride layer (420) over the titanium aluminum carbide layer (410), wherein the depositing the titanium nitride layer includes a first deposition process, a second deposition process, and breaking vacuum between the first deposition process and the second deposition process (figure 3; [0042-0044]);
depositing a silicon layer (430) over the titanium nitride layer (figure 3; [0045]); and
depositing a tungsten layer (300) over the silicon layer without breaking vacuum between the depositing of the tungsten layer and the depositing of the silicon layer, wherein the depositing the tungsten layer implements a fluorine-free tungsten precursor and a hydrogen precursor (figure 5; [0050-0051]).
Chen teaches, in claim 22, wherein:
the depositing the titanium aluminum carbide layer around the semiconductor layer includes performing a first atomic layer deposition (ALD);
the first deposition process is a second ALD;
the second deposition process is a third ALD; and
the depositing the tungsten layer includes performing a fourth ALD (figure 3; [0042-0044]).
Chen teaches, in claim 23, further comprising depositing the silicon layer over the titanium nitride layer without breaking vacuum between the second deposition step of the depositing of the titanium nitride layer and the depositing of the silicon layer (figure 3; [0042-0044]).
Conclusion
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/STANETTA D ISAAC/ Examiner, Art Unit 2898 April 4, 2026