DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim(s) 5 is/are objected to because of the following informalities:
With respect to claim 5, “large than” recited in lines 2-3 of the claim should read “larger than”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Knickerbocker (US 2011/0042795, hereinafter “Knickerbocker”).
Regarding claim 1, Knickerbocker teaches in Fig. 3B (shown below) and related text a method comprising: finding a first plurality of through-silicon vias (326, Fig. 3B) from a first layout of a wafer (306a, Fig. 3B); finding a second plurality of through-silicon vias (e.g. vias 326 on the left side of device shown in Fig. 3B) from the first plurality of through-silicon vias, wherein the second plurality of through-silicon vias are connected in parallel (i.e. through metallization layer on top of the vias 326 on the left side of Fig. 3B); and merging the second plurality of through-silicon vias into a large through-silicon via (e.g. via 328, Fig. 3B) to generate a second layout of the wafer (i.e. layout for the plane 306b, Fig. 3B).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 4-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lukanc (US 6,615,400, hereinafter “Lukanc”) in view of Wang et al. (US 2015/0255529, hereinafter “Wang”).
Regarding claim 1, Lukanc teaches in Figs. 1-5 (shown below) and related text a method comprising: finding a first plurality of through-substrate vias (step 100, Fig. 1 and Figs. 2 and 3) from a first layout of a wafer (Fig. 2); finding a second plurality of through-substrate vias (e.g. vias 205 on the left side of area 210, Fig. 2) from the first plurality of through-silicon vias, wherein the second plurality of through-silicon vias are connected in parallel (Fig. 3); and merging the second plurality of through-substrate vias into a large through-substrate via (Figs. 4-5) to generate a second layout of the wafer (Fig. 4).
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Lukanc, however, does not explicitly teach that the through-substrate vias are through-silicon vias. Nonetheless, forming through-substrate vias disclosed by Lukanc through silicon rather than insulator, would have been obvious to one of ordinary skill in the art as disclosed by Wang (¶[0048]), in order to meet specific design requirements.
Accordingly, since the prior art teaches all of the claim elements, using such elements would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form through-substrate vias disclosed by Lukanc through silicon, as disclosed by Wang, in order to meet specific design requirements.
Regarding claim 4 (1), the combined teaching of Lukanc and Wang discloses the method further comprising: implementing the second layout through a manufacturing process to manufacture the wafer, wherein the manufacturing process comprises forming the large through-silicon via (Lukanc, 405, Fig. 5) penetrating through a semiconductor substrate in the wafer (Lukanc, Fig. 5 and Wang, ¶[0048]).
Regarding claim 5 (1), the combined teaching of Lukanc and Wang discloses, wherein the first plurality of through-silicon vias have a same shape and a same size, and the large through-silicon via has a same shape as, and is large than, one of the first plurality of through-silicon vias (Lukanc, Figs. 2-5).
Regarding claim 6 (1), the combined teaching of Lukanc and Wang wherein the first plurality of through-silicon vias have square, circular or oval top-view shapes (Lukanc, col. 6, ll. 4-8), and the large through-silicon via has an oval top-view shape (Lukanc, col. 6, ll. 8-14).
Regarding claim 7 (1), the combined teaching of Lukanc and Wang discloses wherein in the first layout (Lukanc, Fig. 2), the second plurality of through-silicon vias are joined to a same metal pad (Lukanc, e.g. 310, Fig. 3 and col. 4, ln. 22).
Regarding claim 8 (1), the combined teaching of Lukanc and Wang further discloses: finding a third plurality of through-silicon vias (Lukanc, e.g. vias 205 on the right side of area 210, Fig. 2) from the first plurality of through-silicon vias (Lukanc, e.g. all 205, Fig. 2), wherein the second plurality of through-silicon vias are connected in parallel with the third plurality of through-silicon vias (Lukanc, e.g. vias 205 are connected through metal line 200, Figs. 2 and 3); and merging the third plurality of through-silicon vias into an additional large through-silicon via in the second layout of the wafer (Lukanc, Fig. 3).
Regarding claim 9 (8), the combined teaching of Lukanc and Wang discloses wherein a first total count of the second plurality of through-silicon vias is equal to a second total count of the third plurality of through-silicon vias (Lukanc, i.e. the number of silicon vias on the left side of the area 210 in Fig. 2 is equal to the number of silicon vias on the right side of the area 210, Fig. 2).
Regarding claim 10 (8), the combined teaching of Lukanc and Wang was discussed above in the rejection of claim 8. While Lukanc and Wang do not explicitly teach wherein a first total count of the second plurality of through-silicon vias is greater than a second total count of the third plurality of through-silicon vias, grouping the through-silicon vias (Lukanc, 205, Fig. 2) disclosed by Lukanc and Wang so that the first total count of the second plurality of through-silicon vias is greater than a second total count of the third plurality of through-silicon vias would be within the capabilities of one of ordinary skill in the art as it would amount to nothing more than combining different number of vias (Lukanc, 205, Fig. 2) to form merged vias (Lukanc, 405, Fig. 4) in order to meet specific design requirements.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combined the through-silicon vias disclosed by Lukanc and Wang into merged vias, such that the a first total count of the second plurality of through-silicon vias merged into a first merged via is greater than a second total count of the third plurality of through-silicon vias merged into a second merged via in order to meet specific design requirements.
Regarding claim 11 (8), the combined teaching of Lukanc and Wang further discloses implementing the second layout to manufacture the wafer, wherein in the wafer, the large through-silicon via and the additional large through-silicon via are in physical contact with a metal pad (Lukanc, Fig. 5, where vias 405 are both in contact with metal line 200).
Regarding claim 12 (1), the combined teaching of Lukanc and Wang further discloses finding an additional through-silicon via (Lukanc, e.g. one of the vias 205 on the left side of area 210, Fig. 2) from the first plurality of through-silicon vias (Lukanc, all vias 205, Fig. 2), wherein in the second layout (Lukanc, e.g. layout of Fig. 4), the additional through-silicon via (e.g. one of the vias 205 on the right side of the area 201, Fig. 2 shown as part of the second via 405 in the layout of Fig. 4) is physically separated from, and is connected in parallel with (Lukanc, i.e. through wiring 200, Figs. 4 and 5), the large through-silicon via (Lukanc, i.e. one of the vias 404, Figs. 4 and 5).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Knickerbocker (US 2011/0042795, hereinafter “Knickerbocker”).
Regarding claim 13, Knickerbocker teaches in Figs. 3B, 9A-9C and 10A-10C (Fig. 3B shown below) and related text a method comprising: providing a first layout (e.g. layout of plane 306a, Fig. 3B) comprising: a first plurality of through-vias (e.g. vias 326 connected to Vdd, Fig. 3B); a second plurality of through-vias (e.g. vias 326 connected to GND, Fig. 3B), wherein the first plurality of through-vias and the second plurality of through-vias have a same top-view size (i.e. all vias 326 in Fig. 3B are the same, accordingly they would have the same top-view size); generating a second layout (e.g. layout of plane 306b, Fig. 3B), wherein the generating the second layout comprises merging the first plurality of through-vias to generate a large through-via (e.g. 328, Fig. 3B) in the second layout (e.g. layout of plane 306b, Fig. 3B); and manufacturing a wafer implementing the second layout (Figs. 9A-9C, 10A-10C, and ¶[0073]).
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Knickerbocker, however, does not teach in the embodiment of Fig. 3B that the second plurality of through-vias (e.g. vias 326 in plane 306b connected to vias 326 connected to GND, Fig. 3B) remain to be discrete through-vias in the second layout (e.g. layout of plane 306b, Fig. 3B). Nonetheless, Knickerbocker teaches in the embodiment of Fig. 6 (shown below) that a second plurality of through-vias (e.g. vias 616 in plane 610b connected to vias 614 connected to GND, Fig. 6), similar to the vias disclosed in Fig. 3B, can remain to be discrete through-vias in the second layout (e.g. layout of plane 610b, Fig. 6) in order to support uniform power distribution so as to meet specific design requirements (¶[0057]).
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Thus, since the prior art teaches all of the claimed elements using such elements would lead to predictable results and, as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the second plurality of through-vias disclosed by Knickerbocker in the embodiment of Fig. 3B so that remain to be discrete through-vias in the second layout as disclosed by Knickerbocker in Fig. 6, in in order to support uniform power distribution so as to meet specific design requirements.
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lukanc (US 6,615,400, hereinafter “Lukanc”).
Regarding claim 13, Lukanc teaches in Figs. 1-5 (shown above) and related text a method comprising:
providing a first layout (Fig. 2) comprising:
a first plurality of through-vias (e.g. vias 205 on the left side of Fig. 2 and col, 4, ll. 14-24);
a second plurality of through-vias (e.g. vias 205 on the right side of Fig. 2 and col, 4, ll. 14-24), wherein the first plurality of through-vias and the second plurality of through-vias have a same top-view size (Fig. 2);
generating a second layout (Fig. 3), wherein the generating the second layout comprises merging the first plurality of through-vias to generate a large through-via (405, Fig. 4 and col. 5, ll. 59-67) in the second layout (Fig. 4); and
manufacturing a wafer implementing the second layout (Fig. 5).
While Lukanc, does not exility teach that the second plurality of through-vias remain to be discrete through-vias in the second layout, Lukanc teaches that “[n]ot all vias (not shown) within the electronic device layout will be resized by the present invention, therefore, newly created vias 405 should not be too much larger than the original vias 205 in order to maintain wafer printing and via filling consistencies between the different sized vias (not shown) during manufacture of the electronic device” (col 5, ll. 11-43). Accordingly, forming the second plurality of through-vias so that they remain to be discrete through-vias in the second layout would have been obvious design choice to one of ordinary skill in the art before the effective filing date of the claimed invention in order to meet specific design requirements for the electronic device.
Regarding claim 14 (13), Lukanc further teaches wherein in the wafer, the first plurality of through-vias are joined to a same metal pad (e.g. 200, Figs. 2-3 and col. 4, ln. 22), and wherein the same metal pad has the same size and shape in the first layout and the second layout (Figs. 4-5).
Claim(s) 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Knickerbocker (US 2011/0042795, hereinafter “Knickerbocker”) in view of Kwon et al. (US 2015/0187742, hereinafter “Kwon”).
Regarding claim 18, Knickerbocker teaches in Figs. 6, 9A-9C and 10A-10C (Fig. 3B shown above) and related text a method comprising: finding a first plurality of through-vias (e.g. vias 614 connected to Vdd, Fig. 6) from a first layout of an integrated circuits (e.g. layout of plane 610a, Fig. 6), wherein in the first layout, the first plurality of through-vias are in contact with a metal pad (e.g. pad on top of vias 614 connected to Vdd, Fig. 6 and ¶[0078]); finding a second plurality of through-vias (e.g. vias 326 between vias 614 connected to Vdd and vias 614 connected to GND, Fig. 6) from the first layout (e.g. layout of plane 610a, Fig. 6), wherein in the second layout, the second plurality of through-vias are discrete through-vias (Fig. 6); and manufacturing the large through-vias and the second plurality of through-vias in a wafer (Figs. 9A-9C, 10A-10C, and ¶[0073]).
Knickerbocker, however, does not explicitly teach in the embodiment of Fig. 6 that the first plurality of through-vias are merged to form a large through-via and to generate a second layout. Knickerbocker also does not explicitly teach wherein in the first layout the second plurality of through-vias are in contact with a plurality of metal pads.
To begin with, Knickerbocker teaches in Fig. 3B and related text that a first plurality of through-vias (e.g. 326 connected to Vdd, Fig. 3B), similar to those disclosed in the embodiment of Fig. 6, can be merged to form a large though-via (e.g. 328 above the pad connected to vias 326 connected to Vdd, Fig. 3B) and to generate a second layout (e.g. layout of plane 306b, Fig. 3B) in order to provide higher current as needed (¶[0032]);
Thus, since the prior art teaches all of the claimed elements using such elements would lead to predictable results and, as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to merge the first plurality of though-vias, disclosed by Knickerbocker in the embodiment of Fig. 6, in order to form a large though-via and to generate a second layout, as disclosed as disclosed by Knickerbocker in Fig. 3B in order to provide higher current as needed.
Moreover, forming metal pads at the end of the through-vias disclosed by Knickerbocker, so that the through-vias are in contact with the metal pads would have been obvious to one of ordinary skill in the art as evidenced by Kwon. Specifically, Kwon in Figs. 1 and 8 and related text teaches that when through-vias (e.g. 120, Fig. 1 and ¶[0083]), similar to those disclosed by Knickerbocker, are formed through a substrate (110, Figs. 1 and 8) pads (122, Fig. 1 and ¶[0084]) can be formed and in contact with the through-vias in order to provide connection areas for subsequently formed wiring and/or connection members.
Thus, since the prior art teaches all of the claimed elements using such elements would lead to predictable results and, as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a plurality of metal pads, as disclosed by Kwon, that contact the second plurality of through-vias, disclosed by Knickerbocker, in order to provide connection areas for the subsequently formed wiring and/or connection members.
Regarding claim 19 (18), the combined teaching of Knickerbocker and Kwon discloses wherein the first layout (Knickerbocker, layout of plane 306a, Fig. 3B) further comprises an additional through-via (e.g. one of the vias 326 connected to Vdd, Fig. 3B) in contact with the metal pad (e.g. metal pad on top of four vias 326 connected to Vdd, Fig. 3B), and wherein in the wafer (e.g. in the second layout of plane 306b, Fig. 3B), the additional through-via (e.g. via 328 on the far left of Fig. 3B) and the large through-via (e.g. large through-via 328 connected to vias 326 connected to Vdd, Fig. 3B) are separate through-vias that are connected in parallel (Knickerbocker, e.g. connected though the pad connecting vias 326, Fig. 3B).
Regarding claim 20 (18), the combined teaching of Knickerbocker and Kwon discloses wherein the second plurality of through-vias (Knickerbocker, e.g. vias 614 between vias 614 connected to Vdd and GND, Fig. 6) are arranged as a row (Knickerbocker, Fig. 6).
Allowable Subject Matter
Claim(s) 2-3 and 15-17 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for indicating allowable subject matter:
Regarding claim 2, the prior art of record, alone or in combination, and to the examiner’s knowledge does not teach, disclose, suggest, or render obvious, at least to the skilled artisan, the instant invention regarding a method of determining and merging through-silicon vias, particularly characterized by the steps in which in the first layout, each of the second plurality of through-silicon vias is encircled by a guard ring, and the method further includes a step of merging the guard rings that encircle the second plurality of through-silicon vias into a large guard ring that encircles the large through-silicon via, in combination with all other method steps recited in the claim. Claim(s) 3, which either directly or indirectly depend from claim(s) 2, and which include all of the limitations recited in claim(s) 2, is/are allowed for the similar reasons.
Regarding claim 15, the prior art of record, alone or in combination, and to the examiner’s knowledge does not teach, disclose, suggest, or render obvious, at least to the skilled artisan, the instant invention regarding a method of determining and merging through-silicon vias, particularly characterized by the step of generating a second layout that comprises merging guard rings encircling a first plurality of though-vias to form a large guard ring encircling the large through-via, in combination with all other method steps recited in the claim. Claim(s) 16-17, which either directly or indirectly depend from claim(s) 15, and which include all of the limitations recited in claim(s) 15, is/are allowed for the similar reasons.
Relevant Prior Art
The following prior art is relevant to the invention but not relied upon in any of the rejections:
Papadopoulou (US 6,317,859) teaches in Figs.4A-4B and related text a method of merging a plurality of vias (Fig. 4A) in a larger merged via (Fig. 4B).
Ueda et al. (US 2008/0082947) teaches in Fig. 7 and related text merging of plurality of vias into a merged via.
Conclusion
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/A.B.C/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893