Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election/Restriction
Applicant’s election without traverse of Group I in the reply filed on 12 February 2026 is acknowledged.
Claims 18-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12 February 2026.
Applicant’s submission of new clams 21-23 is acknowledged. As the claims appear to include no new matter, they were examined with the original claims.
Claim Rejections 35 U.S.C § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21 and 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Su et al. ( US Pub 20220271138), hereinafter referred to as Su.
Regarding claim 21, Su teaches a method comprising;
depositing a first dielectric layer (Su, 108, Fig. 1, 266, Fig. 5); over a backside of a substrate (Su, 202, Fig. 5, para. 14), depositing a second dielectric layer (Su, 108, Fig. 1, 268, Fig. 5) over the first dielectric layer; forming an interconnect opening (Su, 271, Fig. 5, para. 24) in the second dielectric layer and the first dielectric layer that exposes a portion of the substrate (Su, 218, Fig. 5, para. 17-18, refers to 218 as a sacrificial plug, however as both it and the substrate can be made of silicon germanium, they are essentially the same), wherein a source/drain (Su, 230, Fig. 5, para. 16) is embedded in the exposed portion of the substrate and the source/drain is disposed at a frontside of the substrate; extending the interconnect opening into the exposed portion of the substrate (Su, 272, Fig. 6, para. 24), wherein the extended interconnect opening exposes a backside of the source/drain (Su, 230, Fig. 6, para. 25); and forming a backside source/drain interconnect (Su, 274, Fig. 7, para. 26) in the extended interconnect opening, wherein the second dielectric layer is removed during the forming of the backside source/drain interconnect (Su, 268, Fig 6-Fig 7, 268 is removed during that stage).
Regarding claim 23, Su teaches the method of claim 21, wherein: the depositing the first dielectric layer includes depositing a nitride layer (Su, 266, Fig. 5, para. 24); and the depositing the second dielectric layer includes depositing an oxide layer (Su, 268, Fig. 5, para. 24).
Claim Rejections 35 U.S.C § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-7, 9-14, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Su, in view of Riess et al. (US Pub 20090239375), hereinafter referred to as Riess.
Regarding claim 1, Su teaches a method comprising: forming a bilayer hard mask (Su, 108, Fig. 1, 266, 267, 268, Fig. 5, para. 24), over a backside of a substrate (Su, 202, Fig. 5, para. 14), wherein the bilayer hard mask includes a first hard mask layer over the backside of the substrate and a second hard mask layer over the first hard mask layer (Su, 266, 268, Fig. 5 para. 24); patterning the bilayer hard mask to form a hard mask opening (Su, 271, Fig. 5, para. 24) therein that exposes a portion of the substrate (Su, 218, Fig. 5, para. 17-18, refers to 218 as a sacrificial plug, however as both it and the substrate can be made of silicon germanium, they are essentially the same) that overlaps a source/drain(Su, 230, Fig. 5, para. 16); forming a backside source/drain via opening (Su, 272, Fig. 6, para. 24) in the substrate that exposes the source/drain by patterning the exposed portion of the substrate using the bilayer hard mask; forming a backside source/drain via (Su, 274, Fig. 7, para. 26) in the backside via opening and the hard mask opening.
Su also teaches and after removing the second hard mask layer, forming a backside metallization layer (Su, 302, fig. 15. Para. 33) over the backside source/drain via, but does not teach wherein the first hard mask remains between the substrate and the metallization layer.
However, Riess teaches method step wherein after the via is filled with the conductive metal (Riess, 160, Fig. 2q, para. 41) it is planarized and the sacrificial layer (Riess, 60, Fig. 2q) is removed. However, the first hard mask layer (Riess, 50, Fig.2s , para. 41) is not always removed.
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the teachings of Su with the remaining mask layer of Riess to use the remaining mask layer as a liner for the second inter level dielectric layer (Riess, para. 41).
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Regarding claim 5, modified Su teaches the method of claim 1, further comprising forming a backside silicide layer (Su, 275, Fig. 7, para. 26) over the exposed source/drain before forming the backside source/drain via.
Regarding claim 6, modified Su teaches the method of claim 1, wherein the removing the second hard mask layer includes performing a planarization process that stops upon reaching the first hard mask layer (Riess, para. 41, hard mask 50 is not completely removed).
Regarding claim 7, modified Su teaches the method of claim 6, wherein the forming the backside source/drain via (Su, 112, Fig. 1, 274, Fig. 7) includes depositing an electrically conductive material over the second hard mask layer that fills the backside source/drain via opening, and performing the planarization process (Su, para. 26) to remove excess electrically conductive material.
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Regarding claim 9, modified Su teaches the method of claim 1, further comprising: forming a frontside source/drain contact (Su, 102, Fig. 1, 236, Fig. 2, para. 16) to the source/drain (Su, 230, Fig. 2); and forming a frontside metallization layer (Su, 256, Fig. 2, para. 20) over the frontside source/drain contact.
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Regarding claim 10, Su teaches A method comprising:
forming a frontside source/drain contact (Su, 102, Fig. 1, 236, Fig. 2, para. 16) on a source/drain of a transistor (Su, 200. Fig. 2); forming a backside source/drain via on the source/drain of the transistor (Su, 274, Fig. 7, para. 26); forming a frontside power rail over the frontside source/drain contact, wherein the frontside power rail is electrically connected to the frontside source/drain contact (Su, 256, Fig. 2, para. 20); forming a backside power rail (Su, 302, Fig. 15, para. 33 over the backside source/drain via, wherein the backside power rail is electrically connected to the backside source/drain via; and wherein the forming the backside source/drain via includes forming a first hard mask layer (Su, 108, Fig. 1, 266, Fig. 5, para. 24), over a backside of a substrate (Su, 202, para. 14), forming a second hard mask layer over the first hard mask layer (Su, 108, Fig. 1, 268, Fig. 5, para. 24), patterning the first hard mask layer and the second hard mask layer (Su, 271, Fig. 5, para. 17), patterning the substrate using the patterned first hard mask layer and the patterned second hard mask layer (Su, 272, Fig. 6, the sacrificial plug (Su, 218, Fig. 5) is removed, but 218 is made of the same material as the substrate), and removing the patterned second hard mask layer (Su, Fig. 7, 268 has been removed).
Su does not teach wherein the patterned first hard mask layer remains between the backside power rail and the backside of the substrate. However, Riess teaches method step wherein after the via is filled with the conductive metal (Riess, 160, Fig. 2q, para. 41) it is planarized and the sacrificial layer (Riess, 60, Fig. 2q) is removed. However, the first hard mask layer (Riess, 50, Fig.2s , para. 41) is not always removed.
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the teachings of Su with the remaining mask layer of Riess to use the remaining mask layer as a liner for the second inter level dielectric layer (Riess, para. 41).
Regarding claim 11, modified Su teaches the method of claim 10, wherein the forming the first hard mask layer (Su, 266, Fig. 5) includes depositing a nitride layer (Su, para. 14) over the backside of the substrate, and the forming the second hard mask layer (Su, 268, Fig. 5) includes depositing an oxide layer (Su, para. 14) over the nitride layer.
Regarding claim 12, modified Su teaches the method of claim 10, wherein a first thickness of the first hard mask layer (Riess, 50, Fig. 2m, para. 34) is less than a second thickness of the second hard mask layer (Riess, 60, Fig. 2m, para. 34).
Regarding claim 13, modified Su teaches the method of claim 10, wherein the forming the backside source/drain via includes depositing an electrically conductive material (Su, 274, Fig. 7, para. 26) in the patterned substrate, the patterned first hard mask layer, and the patterned second hard mask layer and performing a planarization process that removes the patterned second hard mask layer (Su, para. 26, and Su, Fig 7 shows the hard mask layers removed), wherein the planarization process stops upon reaching the patterned first hard mask layer (Riess para. 41, shows the first hard mask is not removed).
Regarding claim 14, modified Su teaches the method of claim 10, wherein the forming the backside source/drain via includes forming a backside silicide layer (Su, 275, Fig. 17, para. 26), the forming the frontside source/drain contact includes forming a frontside silicide layer (Su, para. 18, not explicitly shown in the figures), and the source/drain (Su, 230, Fig. 7, para. 16) is between the backside source/drain via (Su, 274, Fig. 7, para. 26) and the frontside source/drain contact (Su, 236, Fig. 7, para 18).
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Regarding claim 17, modified Su teaches the method of claim 10, wherein the source/drain is a source of a transistor (Su, para. 17).
Claim 2-4 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Su and Riess as applied to claim 1 above, and further in view of Huang et al. (US Pub 20210358842), hereinafter referred to as Huang.
Regarding claim 2, modified Su teaches the method of claim 1, further comprising: extending the backside source/drain via opening by removing a first semiconductor portion of the source/drain. Modified Su also teaches a barrier layer (Su, 273, Fig. 7, para. 26) disposed on the walls of the backside source/drain contact (Su, 274, Fig. 7).
Modified Su does not teach exposing a source/drain isolation structure of the source/drain; and extending the backside source/drain via opening through the source/drain isolation structure of the source/drain when forming via spacers along sidewalls of the backside source/drain via opening.
However, Huang teaches a method for creating a frontside via wherein a contact etch stop layer (CESL) (Huang, 94, Figs. 13A-C, para. 53) is used. In this method a first and second etch process are used to reach the CESL and a third etch process is used to etch the CESL, (Huang, Figs 19A-19C, para. 64).
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to adopt the CESL of Huang into the teachings of Su and Riess by etching through the CESL of Huang while forming the barrier layer of Su to prevent over-etching of the source drain regions (Huang, para. 64).
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Regarding claim 3, modified Su teaches the method of claim 2, but does not explicitly teach wherein the forming the via spacers includes: depositing a dielectric layer over the second hard mask layer, along sidewalls of the hard mask opening formed by the bilayer hard mask, along sidewalls of the backside source/drain via opening formed by the substrate, and over a bottom of the backside source/drain via opening formed by the exposed source/drain;
and etching the dielectric layer, wherein the dielectric layer is removed from over the second hard mask layer and the bottom of the backside source/drain via opening.
However, Su does teach that the barrier layer (Su, 273, Fig. 7, para. 26), while present on the walls of the of the backside source/drain contact (Su, 274, Fig. 7), is not present on the bottom. Su does not explicitly teach how this layer is formed. However, Su teaches another barrier layer (Su, 295, Fig. 14, para. 31) that is deposited using physical vapor deposition or chemical vapor deposition (Su, para. 32). Additionally because the barrier layer must be deposited before the backside source drain contact is deposited, and before the mask layers are planarized it is deposited over them. Additionally to prevent the barrier layer from being present on the bottom of the contact the bottom must have been etched.
Therefore it would be obvious to one having ordinary skill in the art before the filing date of the invention that the creation of the barrier layer must, of necessity include the steps listed in the instant application.
Regarding claim 4, modified Su teaches the method of claim 2, wherein the first hard mask layer (Su, 266 Fig. 5, para. 24), the source/drain isolation structure (Huang, 94, Figs. 13A-13C, para. 53), and the via spacers (Su, 273, Fig. 7, para. 26) include silicon and nitrogen (all can be composed of silicon nitride).
Regarding claim 8, modified Su teaches the method of claim 1, but does not teach wherein it further comprises applying a thinning process to the backside of the substrate before forming the bilayer hard mask.
However, Huang teaches a method wherein the first step for creating the backside vias is to apply a thinning process to the backside of the substrate (Huang, 50, Figs 23A-C, para 78).
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the teachings of Su and Riess with the thinning process of Huang in order to provide a level surface for further processing (Huang, para. 78).
Claims 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Su and Riess as applied to claim 10 above, and further in view of Huang.
Regarding claim 15, modified Su teaches the method of claim 10, wherein: the forming the backside source/drain via includes recessing the source/drain (Su, 272, Fig, 6), but does not teach wherein the recessing stops upon reaching a source/drain isolation structure;
and the forming the backside source/drain via includes etching the source/drain isolation structure of the source/drain to expose a semiconductor portion of the source/drain.
However, Huang teaches a method for creating a frontside via wherein a contact etch stop layer (CESL) (Huang, 94, Figs. 13A-C, para. 53) is used. In this method a first and second etch process are used to reach the CESL and a third etch process is used to etch the CESL, (Huang, Figs 19A-19C, para. 64).
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to adopt the CESL of Huang into the teachings of Su and Riess to prevent over-etching of the source drain regions (Huang, para. 64).
Regarding claim 16, modified Su teaches the method of claim 10, further comprising applying a thinning process to the backside of the substrate (Huang, 50, Figs 23A-C, para. 78) before forming the backside source/drain via.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Su as applied to claim 21 above, and further in view of Huang.
Regarding claim 22, Su teaches the method of claim 21, but does not teach wherein the interconnect opening exposes a third dielectric layer over the backside of the source/drain and the method further includes: depositing a fourth dielectric layer in the interconnect opening,
wherein the fourth dielectric layer is over the third dielectric layer, the second dielectric layer, and the first dielectric layer; and the extending the interconnect opening into the exposed portion of the substrate includes removing a portion of the fourth dielectric layer and a portion of the third dielectric layer that are disposed over the backside of the source/drain.
However, Huang teaches a method for creating a frontside via wherein a contact etch stop layer (CESL) (Huang, 94, Figs. 13A-C, para. 53) is used. In this method a first and second etch process are used to reach the CESL and a third etch process is used to etch the CESL, (Huang, Figs 19A-19C, para. 64). In this instance the CESL of Huang is the third dielectric layer if the instant application.
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to adopt the CESL of Huang into the teachings of Su and Riess to prevent over-etching of the source drain regions (Huang, para. 64).
Further, Su does teach a barrier layer (Su, 273, Fig. 7, para. 26), which, while present on the walls of the of the backside source/drain contact (Su, 274, Fig. 7), is not present on the bottom. Su does not explicitly teach how this layer is formed. However Su teaches another barrier layer (Su, 295, Fig. 14, para. 31) that is deposited using physical vapor deposition or chemical vapor deposition (Su, para. 32). Additionally because the barrier layer must be deposited before the backside source drain contact is deposited, and before the mask layers are planarized it is deposited over them. Additionally to prevent the barrier layer from being present on the bottom of the contact the bottom must have been etched, This would have resulted in the removal of the CESL and the barrier layer.
Therefore it would be obvious to one having ordinary skill in the art before the filing date of the invention that the creation of the barrier layer must, of necessity include the steps listed in the instant application.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Xie et al. (US Pub. US 2024032174)7 teaches a method of making backside power islands wherein the backside processing is conducted through the source region before the source region is formed.
Yao et al. (US Pub. US 20150097293) teaches a method using sacrificial epitaxial layers and masks.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 7:30-5:00.
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/KIERAN M. CUNNINGHAM/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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