Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections 35 U.S.C § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21 and 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Su et al. (US Pub 20220271138), hereinafter referred to as Su.
Regarding claim 21, Su teaches a method comprising; depositing a first dielectric layer (Su, 108, Fig. 1, 266, Fig. 5); over a backside of a semiconductor substrate (Su, 202, Fig. 5, para. 14), depositing a second dielectric layer (Su, 108, Fig. 1, 268, Fig. 5) over the first dielectric layer; forming an interconnect opening (Su, 271, Fig. 5, para. 24) in the second dielectric layer and the first dielectric layer that exposes a portion of the semiconductor substrate that covers a source/drain (Su, 218, Fig. 5, para. 17-18, refers to 218 as a sacrificial plug, however as both it and the substrate can be made of silicon germanium, they are essentially the same), wherein a source/drain (Su, 230, Fig. 5, para. 16) is embedded in the exposed portion of the semiconductor substrate, the source/drain is disposed at a frontside of the semiconductor substrate, and the exposed portion of the semiconductor substrate is disposed between the source/drain and the interconnect opening (Su, Fig. 5, plug/substrate portion 218 is between the source/drain 230 and opening 271); extending the interconnect opening into the exposed portion of the substrate (Su, 272, Fig. 6, para. 24), wherein the extended interconnect opening extends through the semiconductor substrate to expose a backside of the source/drain (Su, 230, Fig. 6, para. 25); and forming a backside source/drain interconnect (Su, 274, Fig. 7, para. 26) in the extended interconnect opening, wherein the second dielectric layer is removed during the forming of the backside source/drain interconnect (Su, 268, Fig 6-Fig 7, 268 is removed during that stage).
Regarding claim 23, Su teaches the method of claim 21, wherein: the depositing the first dielectric layer includes depositing a nitride layer (Su, 266, Fig. 5, para. 24); and the depositing the second dielectric layer includes depositing an oxide layer (Su, 268, Fig. 5, para. 24).
Claim Rejections 35 U.S.C § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-7, 9-14, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Su, Riess et al. (US Pub 20090239375), hereinafter referred to as Riess and Lin (US Pub. 20220216340), hereinafter referred to as Lin.
Regarding claim 1, Su teaches a method comprising: forming a bilayer hard mask (Su, 108, Fig. 1, 266, 267, 268, Fig. 5, para. 24) over a backside of a substrate (Su, 202, Fig. 5, para. 14), wherein the bilayer hard mask includes a first hard mask layer over the backside of the substrate and a second hard mask layer over the first hard mask layer (Su, 266, 268, Fig. 5 para. 24); patterning the bilayer hard mask to form a hard mask opening (Su, 271, Fig. 5, para. 24) therein that exposes a portion of the substrate (Su, 218, Fig. 5, para. 17-18, refers to 218 as a sacrificial plug, however as both it and the substrate can be made of silicon germanium, they are essentially the same) that overlaps and covers a source/drain structure (Su, 230, Fig. 5, para. 16); forming a backside source/drain (Su, 272, Fig. 6, para. 24) via opening that extends from the hard mask opening in the bilayer hard mask, through the exposed portion of the substrate.
Su does not teach, wherein the forming the backside source/drain via opening further includes removing a first source/drain semiconductor portion of the source/drain structure to expose the source/drain isolation structure, wherein the source/drain isolation structure is disposed between the first source/drain semiconductor portion and a second source/drain semiconductor portion of the source/drain structure, after extending the backside source/drain via opening through the source/drain isolation structure to expose the second source/drain semiconductor portion, forming a backside source/drain via in the backside via opening and the hard mask opening in the bilayer hard mask; and after removing the second hard mask layer, forming a backside metallization layer over the first hard mask layer and the backside source/drain via.
However, Lin teaches a method of manufacturing a frontside visa that involves first removing a part of a first source/drain region (Lin, 248-1, Fig. 19, 248-2, Fig. 10, paras, 27-28) to reach separation layer 242 (Fig. 10, para. 25) and then removing a portion of the separation layer to reach the second source/drain region (228-2, Fig. 16, para. 36).
Therefore, it would have been obvious to one having ordinary skill in the art to combine the methods of Su with the method of Lin in order to increase production efficiency and lower associated costs (Lin, para. 1).
Su also teaches after removing the second hard mask layer, forming a backside metallization layer (Su, 302, fig. 15. Para. 33) over the backside source/drain via, but does not teach wherein the first hard mask remains between the substrate and the metallization layer.
However, Riess teaches method step wherein after the via is filled with the conductive metal (Riess, 160, Fig. 2q, para. 41) it is planarized and the sacrificial layer (Riess, 60, Fig. 2q) is removed. However, the first hard mask layer (Riess, 50, Fig. 2, para. 41) is not always removed.
Therefore, it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the teachings of Su and Lin with the remaining mask layer of Riess to use the remaining mask layer as a liner for the second inter level dielectric layer (Riess, para. 41).
Regarding claim 5, modified Su teaches the method of claim 1, further comprising forming a backside silicide layer (Su, 275, Fig. 7, para. 26) over the exposed second source/drain semiconductor portion before forming the backside source/drain via.
Regarding claim 6, modified Su teaches the method of claim 1, wherein the removing the second hard mask layer includes performing a planarization process that stops upon reaching the first hard mask layer (Riess, para. 41, hard mask 50 is not completely removed).
Regarding claim 7, modified Su teaches the method of claim 6, wherein the forming the backside source/drain via (Su, 112, Fig. 1, 274, Fig. 7) includes depositing an electrically conductive material over the second hard mask layer that fills the backside source/drain via opening, and performing the planarization process (Su, para. 26) to remove excess electrically conductive material.
Regarding claim 9, modified Su teaches the method of claim 1, further comprising: forming a frontside source/drain contact (Su, 102, Fig. 1, 236, Fig. 2, para. 16) to the source/drain (Su, 230, Fig. 2); and forming a frontside metallization layer (Su, 256, Fig. 2, para. 20) over the frontside source/drain contact.
Regarding claim 10, Su teaches a method comprising: forming a frontside source/drain contact (Su, 102, Fig. 1, 236, Fig. 2, para. 16) on a source/drain of a transistor (Su, 200. Fig. 2); forming a backside source/drain via on the source/drain of the transistor (Su, 274, Fig. 7, para. 26); forming a frontside power rail over the frontside source/drain contact, wherein the frontside power rail is electrically connected to the frontside source/drain contact (Su, 256, Fig. 2, para. 20); forming a backside power rail (Su, 302, Fig. 15, para. 33 over the backside source/drain via, wherein the backside power rail is electrically connected to the backside source/drain via; and wherein the forming the backside source/drain via includes forming a first hard mask layer (Su, 108, Fig. 1, 266, Fig. 5, para. 24), over a backside of a semiconductor substrate (Su, 202, para. 14), forming a second hard mask layer over the first hard mask layer (Su, 108, Fig. 1, 268, Fig. 5, para. 24), patterning the first hard mask layer and the second hard mask layer (Su, 271, Fig. 5, para. 17), patterning the substrate using the patterned first hard mask layer and the patterned second hard mask layer (Su, 272, Fig. 6, the sacrificial plug (Su, 218, Fig. 5) is removed, but 218 is made of the same material as the substrate), and removing the patterned second hard mask layer (Su, Fig. 7, 268 has been removed).
Su does not teach wherein the patterned first hard mask layer remains between the backside power rail and the backside of the semiconductor substrate. However, Riess teaches method step wherein after the via is filled with the conductive metal (Riess, 160, Fig. 2q, para. 41) it is planarized and the sacrificial layer (Riess, 60, Fig. 2q) is removed. However, the first hard mask layer (Riess, 50, Fig.2s , para. 41) is not always removed.
Therefore, it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the teachings of Su with the remaining mask layer of Riess to use the remaining mask layer as a liner for the second inter level dielectric layer (Riess, para. 41).
Regarding claim 11, modified Su teaches the method of claim 10, wherein the forming the first hard mask layer (Su, 266, Fig. 5) includes depositing a nitride layer (Su, para. 14) over the backside of the semiconductor substrate, and the forming the second hard mask layer (Su, 268, Fig. 5) includes depositing an oxide layer (Su, para. 14) over the nitride layer.
Regarding claim 12, modified Su teaches the method of claim 10, wherein a first thickness of the first hard mask layer (Riess, 50, Fig. 2m, para. 34) is less than a second thickness of the second hard mask layer (Riess, 60, Fig. 2m, para. 34).
Regarding claim 13, modified Su teaches the method of claim 10, wherein the forming the backside source/drain via includes depositing an electrically conductive material (Su, 274, Fig. 7, para. 26) in the patterned semiconductor substrate, the patterned first hard mask layer, and the patterned second hard mask layer and performing a planarization process that removes the patterned second hard mask layer (Su, para. 26, and Su, Fig 7 shows the hard mask layers removed), wherein the planarization process stops upon reaching the patterned first hard mask layer (Riess para. 41, shows the first hard mask is not removed).
Regarding claim 14, modified Su teaches the method of claim 10, wherein the forming the backside source/drain via includes forming a backside silicide layer (Su, 275, Fig. 17, para. 26), the forming the frontside source/drain contact includes forming a frontside silicide layer (Su, para. 18, not explicitly shown in the figures), and the source/drain (Su, 230, Fig. 7, para. 16) is between the backside source/drain via (Su, 274, Fig. 7, para. 26) and the frontside source/drain contact (Su, 236, Fig. 7, para 18).
Regarding claim 17, modified Su teaches the method of claim 10, wherein the source/drain is a source of a transistor (Su, para. 17).
Claim 2-4 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Su and Riess as applied to claim 1 above, and further in view of Huang et al. (US Pub 20210358842), hereinafter referred to as Huang.
Regarding claim 2, modified Su teaches the method of claim 1 further comprising extending the backside source/drain via opening through the source/drain isolation structure (Lin, 249, Fig. 12, para.
Modified Su also teaches a barrier layer (Su, 273, Fig. 7, para. 26) disposed on the walls of the backside source/drain contact (Su, 274, Fig. 16, para. 36).
Modified Su does not teach forming via spacers along sidewalls of the backside source/drain via opening.
However, Huang teaches a method for creating a frontside via wherein a contact etch stop layer (CESL) (Huang, 94, Figs. 13A-C, para. 53) is used. In this method a first and second etch process are used to reach the CESL and a third etch process is used to etch the CESL, (Huang, Figs 19A-19C, para. 64).
Therefore, it would have been obvious to one having ordinary skill in the art before the filing date of the invention to adopt the CESL of Huang into the teachings of Su and Riess by etching through the CESL of Huang while forming the barrier layer of Su to prevent over-etching of the source drain regions (Huang, para. 64).
Regarding claim 3, modified Su teaches the method of claim 2, but does not explicitly teach wherein the forming the via spacers includes: depositing a dielectric layer over the second hard mask layer, along sidewalls of the hard mask opening the bilayer hard mask, along sidewalls of the backside source/drain via opening formed by the substrate, and over a bottom of the backside source/drain via opening formed by the source/drain isolation structure;
and etching the dielectric layer, wherein the dielectric layer is removed from over the second hard mask layer and the bottom of the backside source/drain via opening, wherein the etching of the dielectric layer further removes a portion of the source/drain isolation structure and exposes the second source/drain semiconductor portion.
However, modified Su does teach that the barrier layer (Su, 273, Fig. 7, para. 26), while present on the walls of the of the backside source/drain contact (Su, 274, Fig. 7), is not present on the bottom. Su does not explicitly teach how this layer is formed. However, Su teaches another barrier layer (Su, 295, Fig. 14, para. 31) that is deposited using physical vapor deposition or chemical vapor deposition (Su, para. 32). Additionally, because the barrier layer must be deposited before the backside source drain contact is deposited, and before the mask layers are planarized it is deposited over them. Therefore, to prevent the barrier layer from being present on the bottom of the contact the bottom must have been etched. Finally, Lin teaches a method of creating a via wherein a portion of the isolation structure (Lin, 242, Figs. 10-16) is removed
Therefore, it would be obvious to one having ordinary skill in the art before the filing date of the invention that the creation of the barrier layer must, of necessity, include the steps listed in the instant application.
Regarding claim 4, modified Su teaches the method of claim 2, wherein the first hard mask layer (Su, 266 Fig. 5, para. 24), the source/drain isolation structure (Huang, 94, Figs. 13A-13C, para. 53), and the via spacers (Su, 273, Fig. 7, para. 26) include silicon and nitrogen (all can be composed of silicon nitride).
Regarding claim 8, modified Su teaches the method of claim 1, but does not teach wherein it further comprises applying a thinning process to the backside of the substrate before forming the bilayer hard mask.
However, Huang teaches a method wherein the first step for creating the backside vias is to apply a thinning process to the backside of the substrate (Huang, 50, Figs 23A-C, para 78).
Therefore, it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the teachings of Su and Riess with the thinning process of Huang in order to provide a level surface for further processing (Huang, para. 78).
Claims 15 is rejected under 35 U.S.C. 103 as being unpatentable over Su and Riess as applied to claim 10 above, and further in view of Huang.
Regarding claim 15, modified Su teaches the method of claim 10, wherein: the forming the backside source/drain via includes recessing the source/drain (Su, 272, Fig, 6), but does not teach wherein the recessing stops upon reaching a source/drain isolation structure;
and the forming the backside source/drain via includes etching the source/drain isolation structure of the source/drain to expose a semiconductor portion of the source/drain.
However, Huang teaches a method for creating a frontside via wherein a contact etch stop layer (CESL) (Huang, 94, Figs. 13A-C, para. 53) is used. In this method a first and second etch process are used to reach the CESL and a third etch process is used to etch the CESL, (Huang, Figs 19A-19C, para. 64).
Therefore, it would have been obvious to one having ordinary skill in the art before the filing date of the invention to adopt the CESL of Huang into the teachings of Su and Riess to prevent over-etching of the source drain regions (Huang, para. 64).
Claims 16 is rejected under 35 U.S.C. 103 as being unpatentable over Su, Riess and Huang as applied to claim 15 above, and further in view of Lin.
Regarding claim 16, modified Su teaches the method of claim 10, further comprising applying a thinning process to the backside of the semiconductor substrate (Huang, 50, Figs 23A-C, para. 78) before forming the backside source/drain via.
Modified Su does not teach wherein a portion of the semiconductor substrate remains covering a backside of the source/drain after applying the thinning process.
However, Lin teaches a method of creating a semiconductor wherein the backside substrate (Lin, 202, Fig. 17) is first thinned (Lin, para. 38) (Lin, para. 38) before the backside forming the backside source/drain via. Therefore, i would have been obvious to one having ordinary skill in the art to thin the substrate in order to increase production efficiency and lower associated costs (Lin, para. 1).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Su as applied to claim 21 above, and further in view of Huang.
Regarding claim 22, Su teaches the method of claim 21, but does not teach wherein the interconnect opening exposes a third dielectric layer over the backside of the source/drain and the method further includes: depositing a fourth dielectric layer in the interconnect opening,
wherein the fourth dielectric layer is over the third dielectric layer, the second dielectric layer, and the first dielectric layer; and the extending the interconnect opening into the exposed portion of the semiconductor substrate includes removing a portion of the fourth dielectric layer and a portion of the third dielectric layer that are disposed over the backside of the source/drain.
However, Huang teaches a method for creating a frontside via wherein a contact etch stop layer (CESL) (Huang, 94, Figs. 13A-C, para. 53) is used. In this method a first and second etch process are used to reach the CESL and a third etch process is used to etch the CESL, (Huang, Figs 19A-19C, para. 64). In this instance the CESL of Huang is the third dielectric layer if the instant application.
Therefore, it would have been obvious to one having ordinary skill in the art before the filing date of the invention to adopt the CESL of Huang into the teachings of Su and Riess to prevent over-etching of the source drain regions (Huang, para. 64).
Further, Su does teach a barrier layer (Su, 273, Fig. 7, para. 26), which, while present on the walls of the of the backside source/drain contact (Su, 274, Fig. 7), is not present on the bottom. Su does not explicitly teach how this layer is formed. However, Su teaches another barrier layer (Su, 295, Fig. 14, para. 31) that is deposited using physical vapor deposition or chemical vapor deposition (Su, para. 32). Additionally because the barrier layer must be deposited before the backside source drain contact is deposited, and before the mask layers are planarized it is deposited over them. Additionally to prevent the barrier layer from being present on the bottom of the contact the bottom must have been etched. This would have resulted in the removal of the CESL and the barrier layer.
Therefore, it would be obvious to one having ordinary skill in the art before the filing date of the invention that the creation of the barrier layer must, of necessity include the steps listed in the instant application.
Response to Arguments
Applicant’s arguments, see page 7, line 5 to page 8 line 19, filed 7/7/2026, with respect to the rejections of claims 1, 5-7 and 9 under 35 U.S.C. § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Su, Riess and Lin. Applicant amended claim 1 to incorporate part of claim 2 and further amended that portion to place the source/drain isolation structure between a first and second source/drain semiconductor portion. The features incorporated from claim 2 were rejected under Lin which teaches a method wherein the isolation structure is between the first and dsecond portions of the source/drain structure.
Applicant's arguments filed7/7/2026 regarding claim 10 and corresponding dependent claims have been fully considered but they are not persuasive. Applicant declares that “patterning the semiconductor substrate using the patterned first hard mask layer and the patterned second hard mask layer, and removing the patterned second hard mask layer, wherein the patterned first hard mask layer remains between the backside power rail and the backside of the semiconductor substrate” was added to claim 10, however, except for the word “semiconductor” preceding “substrate” a comparison between claim 10 of 7/7/2026 and claim 10 of 2/12/2026 shows that the claims are identical. Accordingly, the rejection of claim 10 is maintained.
NOTE: claim 16, which depends from claim 10 was amended to include “wherein a portion of the semiconductor substrate remains covering a backside of the source/drain after applying the thinning process.” An updated rejection was made of dependent claim 16 based on Lin.
Applicant’s arguments, see page 10, line 8-page 9, line 8, filed 7/7/2026, with respect to the rejections of claims 21 and 23 under 35 U.S.C. § 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of Su. Applicant refined the exposed portion of the semiconductor substrate and the location of the interconnect opening. Both required locations are shown in Su.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chiu et al. (US Pub. 20210335783) teaches a method of creating a backside via which comprises thinning the backside of the substrate.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 8:30-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 5712703042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KIERAN M. CUNNINGHAM/ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893
Prosecution Insights