DETAILED ACTION
Election/Restriction
1. Applicant's election without traverse of Group II, claims 1 - 16, and newly added claims 21 - 23 is acknowledged.
Specification
2. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claim(s) 21, 22, 24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lai et al. (20220285561).
With regard to claim 21, Lai et al. disclose a method, comprising: providing a structure comprising:
a stack (206, 208, fig. 7A) of alternating first semiconductor layers (208, fig. 7A) and second semiconductor layers (206, fig. 7A), and
a dummy gate (226, fig. 7A) disposed on a top surface and first sidewalls (referred to as “208A” by examiner’s annotation shown in fig. 7A below) of the stack (206, 208, fig. 7A);
performing a selective etching process to remove a first portion (a portion is removed for forming a recess 207) of the second semiconductor layers (206, fig. 7A) from the first sidewalls (206A) of the stack (206, 208, fig. 7A), thereby forming a recess (207) between adjacent first semiconductor layers (208, fig. 7A);
depositing a gate spacer layer (252, fig. 8A) over the dummy gate (226, fig. 8A) and the stack (206, 208, fig. 8A), wherein a portion of the gate spacer layer (252, fig. 8A) is disposed in the recess (207);
recessing a source/drain region of the stack (206, 208, figs. 7A, 9A) to form a source/drain recess (246);
forming a source/drain feature (237, 239, fig. 11A) in the source/drain recess (246);
removing the dummy gate (226, figs.18A, 19A) and a second portion of the second semiconductor layers (206, figs.18A, 19A), thereby forming a gate trench (a gate trench, fig. 19A, for forming a metal gate stacks 280); and forming a metal gate (280) in the gate trench (the gate trench, fig. 19A, for forming the metal gate stacks 280).
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With regard to claim 22, Lai et al. disclose the selective etching process is a first selective etching process; wherein the source/drain recess (246) exposes a second sidewall (referred to as “208B” by examiner’s annotation shown in fig. 7A below) of the stack (206, 208); and wherein the method further comprises: performing a second selective etching process to remove a third portion of the second semiconductor layers (206) from the second sidewall (referred to as “208B” by examiner’s annotation shown in fig. 7A below) of the stack (206, 208), thereby forming inner spacer recesses (207, fig. 7A); and forming inner spacers (252, fig. 9A) in the inner spacer recesses (207, fig. 9A).
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With regard to claim 24, Lai et al. disclose the recess (207) is directly below the dummy gate (226).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 11, 13 - 16 are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (11211456) in view of Wang et al. (12148836).
With regard to claim 11, Jung et al. disclose a method (for example, see figs. 10 – 19), comprising:
providing a workpiece (114, 124, fig. 10) comprising: first and second channel layers (124, fig. 10; for example, see column 5, lines 14, 15) extending lengthwise along a first direction (for example, see 1st direction as shown in fig. 10), and
a sacrificial layer (114, fig. 10) disposed between first and second channel layers (124, fig. 10);
forming a dummy gate structure (175, fig. 10) over the first and second channel layers (124, fig. 10), and the sacrificial layer (114, fig. 10), wherein the dummy gate structure (175, fig. 10) extends lengthwise along a second direction (for example, see 2nd direction as shown in fig. 10) perpendicular to the first direction (for example, see 1st direction as shown in fig. 10);
performing an etching process to selectively and partially recess (200, fig. 13) the sacrificial layer (114, fig. 13) from a first sidewall (referred to as “114A” by examiner’s annotation shown in fig. 12 below) of the sacrificial layer (114) parallel to the first direction (for example, see 1st direction as shown in fig. 13);
depositing a gate spacer layer (210, fig. 13) over the dummy gate structure (175, fig. 13), the first and second channel layers (124, fig. 13), and the sacrificial layer (114, fig. 13);
recessing a source/drain region (a trench 190, fig. 12 for forming a source/drain feature forming in a source/drain region) of the first and second channel layers (124, figs. 12, 14), and sacrificial layer (114, figs. 12, 14), to form a source/drain opening (the trench 190, for forming a source/drain feature, functioning as a source/drain opening); and
forming a source/drain feature (250, fig. 17) in the source/drain opening (190).
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Jung et al. do not clearly disclose after the forming of the source/drain feature, a portion of the gate spacer layer is sandwiched between the first channel layer and the second channel layer.
However, Wang et al. disclose after the forming of the source/drain feature (250, fig. 10A), a portion (referred to as “242A” by examiner’s annotation shown in fig. 11A below) of the gate spacer layer (242) is sandwiched between the first and second channel layer (semiconductor layers 204A functioning as first and second channel layers). (for example, see figs. 10A, 11A).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Jung et al.’s device to have the depositing of the epitaxial layer is performed prior to the selectively and partially recessing of the inner spacers as taught by Wang et al. in order to secure leakage currents may not be generated and minimize the signal interference for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 13, Jung et al. disclose after the etching process, in a cross-sectional view perpendicular to the first direction, a second sidewall (referred to as “114B” by examiner’s annotation shown in fig. 13 below) of the sacrificial layer (114) is recessed from sidewalls of the first and second channel layers (124).
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With regard to claim 14, Wang et al. disclose the performing of the etching process comprises performing a wet etching process with a solution comprising hydrogen fluoride (for example, see column 9, lines 55 – 64, fig. 5A).
With regard to claim 15, Jung et al. disclose the performing of the etching process forms a recess (200) directly under the dummy gate structure (175).
With regard to claim 16, Jung et al. disclose the depositing of the gate spacer layer (210) comprises depositing the gate spacer layer (210) in the recess (200).
7. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (11211456) in view of Wang et al. (12148836) and further in view of Pranda et al. (2025/0046617).
With regard to claim 12, Jung et al. and Wang et al. do not clearly disclose after the etching process, in a horizontal plane across the sacrificial layer, the sacrificial layer has a first width along the first direction and adjacent the dummy gate structure, and the dummy gate structure has a second width along the first direction, wherein the first width is smaller than the second width.
However, Pranda et al. disclose after the etching process, in a horizontal plane across the sacrificial layer, the sacrificial layer (220) has a first width (referred to as “X1” by examiner’s annotation shown in fig. 2B below) along the first direction (X-direction) and adjacent the dummy gate structure (250), and the dummy gate structure (250) has a second width (referred to as “X2” by examiner’s annotation shown in fig. 2B below) along the first direction (X-direction), wherein the first width (X1) is smaller than the second width (X2).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Jung et al. and Wang et al.’s device to have after the etching process, in a horizontal plane across the sacrificial layer, the sacrificial layer has a first width along the first direction and adjacent the dummy gate structure, and the dummy gate structure has a second width along the first direction, wherein the first width is smaller than the second width as taught by Pranda et al. in order to enhance a high electron mobility of the semiconductor device for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
8. Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (20220285561) in view of Wang et al. (12148836).
With regard to claim 23, Lai et al. disclose the selective etching process is a first selective etching process, but Lai et al. do not clearly disclose a dielectric layer between the stack and the dummy gate; wherein the selective etching process is a first selective etching process; and wherein the method further comprises performing a second selective etching process to remove a portion of the dielectric layer to enlarge the recess.
However, Wang et al. disclose a dielectric layer (224, fig. 8A) between the stack (204A, 204B) and the dummy gate (210); and wherein the method further comprises performing a second selective etching process to remove a portion of the dielectric layer (224, fig. 9) to enlarge the recess (referred to as “R1” by examiner’s annotation shown in fig. 9A below).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Jung et al. and Wang et al.’s device to have a dielectric layer between the stack and the dummy gate; and wherein the method further comprises performing a second selective etching process to remove a portion of the dielectric layer to enlarge the recess as taught by Wang et al. in order to form the gate spacer on the dummy gate and the semiconductor layers for minimizing the signal interference and enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Allowable Subject Matter
9. Claims 1 - 10 are allowable over the prior art of record because none of these references disclose or can be combined to yield the claimed invention such as recessing a source/drain region of the stack of semiconductor layers to form a source/drain opening exposing a sidewall of the stack of semiconductor layers; after the recessing of the source/drain region, performing a second etching process to selectively recess the second semiconductor layers from the source/drain opening to form inner spacer recesses as recited in claim 1.
Conclusion
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812
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