DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
Applicant is reminded of the proper content of an abstract of the disclosure.
A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art.
If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives.
Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps.
Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length.
See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts.
The abstract of the disclosure is objected to because it refers to purported merits of the invention. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Objections
Claims 10 – 15 are objected to because of the following informalities: In line 5 of claim 10 “containing” should be replaced with –contains--. Appropriate correction is required. Claims 11 – 15 inherit this discrepancy.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 – 6, 10 – 12, 14, and 15 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by US Patent Application No. 2023/0009485 to Lee et al.
Regarding claim 1, Lee et al. teach a method, comprising:
depositing an interfacial layer (62A) on a semiconductor channel region;
depositing a high-K dielectric layer (62B) on the interfacial layer;
treating the high-K dielectric layer to incorporate a filler element with vacancies in the high-K dielectric layer (¶ [0059]); and
depositing a gate electrode layer (80) on the high-K dielectric layer.
Regarding claim 2, Lee et al. teach a method, wherein treating the high-K dielectric layer comprises:
depositing a source layer (66) over the high-K dielectric layer, wherein the source layer contains the filler element;
depositing a capping layer (64) over the source layer;
performing an anneal process to incorporate the filler element into the high-K dielectric layer (Abstract, ¶¶[0046],[0054]); and
removing the capping layer and the source layer ((236) Fig. 28).
Regarding claim 3, Lee et al. teach a method, wherein the filler element is fluorine.
Regarding claim 4, Lee et al. teach a method, wherein depositing the source layer comprises depositing a tungsten layer using a fluorine-containing precursor (¶ [0048]).
Regarding claim 5, Lee et al. teach a method, wherein the fluorine-containing precursor is tungsten hexafluoride (¶ [0048]).
Regarding claims 6 and 12, Lee et al. teach a method, wherein the capping layer comprises titanium nitride (¶ [0045]).
Regarding claim 10, Lee et al. teach a method, comprising:
depositing an interfacial layer (62A) on a semiconductor channel region;
depositing a high-K dielectric layer (62B) on the interfacial layer;
depositing a source layer (66) on the high-K dielectric layer, wherein the source layer contains fluorine (¶ [0046]);
performing a solid phase anneal process to drive fluorine from the source layer to the high-K dielectric layer (Abstract, ¶¶[0046],[0054]);
removing the source layer ((236) Fig. 28); and
depositing a gate electrode layer (80) on the high-K dielectric layer.
Regarding claim 11, Lee et al. teach a method, further comprising:
depositing a first capping layer (64) on the source layer prior to performing the solid phase anneal process (¶¶ [0014], [0046]); and
removing the first capping layer ((236) Fig. 28).
Regarding claim 14, Lee et al. teach a method, wherein depositing the source layer comprises depositing a tungsten layer using tungsten hexafluoride (¶ [0048]).
Regarding claim 15, Lee et al. teach a method, wherein the anneal process is performed at a temperature range between about 500°C and about 700°C (¶ [0054]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7 – 9, 16 – 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al.
Regarding claims 7 and 8, Lee et al. teach a method, wherein the capping layer is thick enough to protect the high-k dielectric layer (¶ [0059]). Lee et al. do not teach a thickness between 18 and 28 Angstroms, or 9 and 13 Angstroms. It would have been obvious to one having ordinary skill in the art to arrive at the optimal thickness of the capping layer through routine experimentation since it is desirable to the capping layer to be thick enough to protect the high-k dielectric layer.
Regarding claim 9, Lee et al. teach a method, wherein the anneal process is performed at a temperature range between about 500°C and about 700°C (¶ [0054]).
Regarding claim 16, Lee et al. teach a method, comprising:
forming a semiconductor device comprising:
a first source/drain region (48);
a second source/drain region (48);
a channel region (¶ [0037]) disposed between the first and second source/drain regions;
an interfacial layer (62A) formed on the channel region;
a high-K dielectric layer (62B) formed on the interfacial layer and comprising fluorine; and
a gate electrode layer (80) disposed over the high-K dielectric layer.
Lee et al. do not teach wherein the high-K dielectric layer comprises fluorine at a molecular concentration in a range between about 18% and about 22%. The molecular concentration of fluorine in the gate dielectric is a result effective variable (¶ [0015]). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to find the optimal concentration of the fluorine to achieve the desired device performance characteristics.
Regarding claim 17, Lee et al. teach a method, wherein the gate electrode layer comprises aluminum (¶¶ [0062] - [0063]).
Regarding claim 18, Lee et al. teach a method, further comprises a capping layer (64) disposed between the high-K dielectric layer and the gate electrode layer.
Regarding claim 20, Lee et al. teach a method, wherein the channel region comprises two or more nanosheet channels (¶ [0149]).
Allowable Subject Matter
Claims 13 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application No. 2018/0145149 to Chiang et al. also teaches a method comprising: depositing an interfacial layer on a semiconductor channel region; depositing a high-K dielectric layer on the interfacial layer; treating the high-K dielectric layer to incorporate a filler element with vacancies in the high-K dielectric layer; and depositing a gate electrode layer on the high-K dielectric layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS W OWENS whose telephone number is (571)272-1662. The examiner can normally be reached M-F 5:30-1:30.
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DOUGLAS W. OWENS, Esq.
Primary Patent Examiner
Art Unit 2897
/DOUGLAS W OWENS/Primary Patent Examiner, Art Unit 2897