DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election without traverse of the invention of group II in the reply filed on March 15, 2026 is acknowledged. Double Patenting Claim s 16 – 20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 9 – 13 of copending Application No. 19/294,346 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application recite the limitations the copending application, or are obvious, as shown in the table below. This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented. 18/524,661 (instant application) 19/294,346 16. A method, comprising: forming a semiconductor fin on a front side of a substrate; forming a sacrificial gate structure over the semiconductor fin; etching the semiconductor fin and the substrate to form source/drain recesses on two sides of the sacrificial gate structure; depositing buried features in the source/drain recesses; forming source/drain regions over the buried features; forming a replacement gate structure; thinning a backside of the substrate to expose the buried features; selectively removing the substrate between the buried features to expose the replacement gate structure; and forming a backside gate contact between the buried features. 9. A method, comprising: forming a fin structure on a front side of a substrate , wherein the fin structure comprises a well portion extending from the substrate and a channel portion disposed on the well portion, and the channel portion includes two or more semiconductor channel layers; forming a sacrificial gate structure over the fin structure ; etching the fin structure to form source/drain recesses on two sides of the sacrificial gate structure ; depositing buried features in the source/drain recesses , wherein the buried features are adjacent the well portion of the fin structure; forming source/drain regions over the buried features , wherein the source/drain regions are connected to the two or more semiconductor channel layers; forming a replacement gate structure around the two or more semiconductor channel layers; thinning a backside of the substrate to expose the buried features ; selectively removing the well portion of the fin structure between the buried features to expose the replacement gate structure; and forming a backside gate contact between the buried features . 17. The method of claim 16, further comprising: prior to forming the source/drain regions, depositing an isolation layer on the buried features. 10. The method of claim 9, further comprising: prior to forming the source/drain regions, depositing an isolation layer on the buried features. 18. The method of claim 16, further comprising: forming a gate spacer on the buried features prior to forming the backside gate contact. 11. The method of claim 9, further comprising: forming a gate spacer on the buried features prior to forming the backside gate contact. 19. The method of claim 16, further comprising: selectively removing one of the buried features to expose the corresponding source/drain region; and forming a backside source/drain contact. 12. The method of claim 9, further comprising: selectively removing one of the buried features to expose the corresponding source/drain region; and forming a backside source/drain contact. 20. The method of claim 19, further comprising forming a backside source/drain contact spacer prior to forming the backside source/drain contact. 13. The method of claim 12, further comprising forming a backside source/drain contact spacer prior to forming the backside source/drain contact. Allowable Subject Matter Claims 21 – 35 are allowed. The following is a statement of reasons for the indication of allowable subject matter: the prior art of record does not teach or reasonably suggest a method as recited in claims 21 and 32, including the steps of “ flipping over the substrate; and forming a gate contact opening from a back side of the substrate to expose the gate electrode layer; and forming a gate contact in the gate contact opening ” or “ etching the semiconductor fin and the substrate to form source/drain recesses on two sides of the sacrificial gate structure . . . thinning a backside of the substrate; forming a backside contact opening to expose the gate electrode layer; and forming a backside gate contact in the backside contact opening. ” Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publication No. 2024/0290864 to Ho et al. teach a method of forming a backside gate contact by removing backside material. Ho et al. do not teach forming the buried feature. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT DOUGLAS W OWENS whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-1662 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F 5:30-1:30 . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Chad Dicke can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 571-270-7996 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. FILLIN "Examiner Stamp" \* MERGEFORMAT DOUGLAS W. OWENS, Esq. Primary Patent Examiner Art Unit 2897 /DOUGLAS W OWENS/ Primary Patent Examiner, Art Unit 2897