Prosecution Insights
Last updated: April 19, 2026
Application No. 18/525,028

Power Semiconductor Package

Non-Final OA §103
Filed
Nov 30, 2023
Examiner
WALL, VINCENT
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Wolfspeed, Inc.
OA Round
1 (Non-Final)
62%
Grant Probability
Moderate
1-2
OA Rounds
2y 8m
To Grant
87%
With Interview

Examiner Intelligence

Grants 62% of resolved cases
62%
Career Allow Rate
488 granted / 793 resolved
-6.5% vs TC avg
Strong +25% interview lift
Without
With
+25.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
52 currently pending
Career history
845
Total Applications
across all art units

Statute-Specific Performance

§101
2.0%
-38.0% vs TC avg
§103
48.9%
+8.9% vs TC avg
§102
16.9%
-23.1% vs TC avg
§112
27.2%
-12.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 793 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on November 30, 2023, and September 8, 2025 were considered by the examiner. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-2, 35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Silicon Carbide MOSFET TO-247, https://web.archive.org/web/20220813001443/https://ppmpower.co.uk/products/high-power-semiconductors/low-power-semiconductor-modules/silicon-carbide-mosfet-to-247/, Aug., 13, 2022 (“PPM”), in view of Kanetake et al. (US 2020/0066620 A1) (“Kanetake”). Regarding claim 1, PPM teaches: one or more semiconductor die (SIC Mosfet Chip) comprising a wide bandgap semiconductor material (SIC); a housing (mold resin); one or more electrical leads (there are four leads extending from the mold resin) extending from the housing (mold resin). PPM does not teach, a non-rectangular creepage cutout in the housing. PPM teaches: A rectangular style creepage cutout in the housing (this is clearly shown in PPM). Kanetake teaches at least in figures 14-15: a non-rectangular creepage cutout in the housing (figure 14 element 7a). It would have been obvious to one of ordinary skill in the art to change the shape of the creepage cutout of PPM to be non-rectangular as Kanetake teaches that both the rectangular creepage cutout and the non-rectangular creepage cutout perform the same function which is to increase the withstand voltage and response speed. ¶¶ 0083-88. Based upon this under MPEP 2144.04(IV)(A), 2144.04(IV)(B), and 2144.06-07, the shape of the creepage cutout, it’s size and proportions, are art recognized equivalents, all of which are suitable for the intended purpose of being a cutout which can improve the withstand voltage and response speed of the device. Regarding claim 2, PPM teaches: wherein a first lead of the one or more electrical leads is connected to a source contact of the one or more semiconductor die and a second lead of the one or more electrical leads is connected to a drain contact of the one or more semiconductor die (this is shown in the TO-247-4L figure of PPM). Regarding claim 35, PPM teaches: wherein the one or more semiconductor die comprise a metal-oxide-semiconductor field-effect transistor (MOSFET) (SIC MOSFET chip), wherein a first lead of the one or more electrical leads is connected to a gate contact of the MOSFET (G) and a second lead of the one or more electrical leads is connected to a source contact (S or KS) of the MOSFET (SIC MOSFET chip). Claim(s) 6, 8, 10, 14, 16, 18, 20, 22, 24, 26, 89, 95, 115-118, and 132 is/are rejected under 35 U.S.C. 103 as being unpatentable over PPM, in view of Kanetake, in view of Iwade et al. (US 2007/0052072 A1) (“Iwade”). Regarding claim 6, PPM teaches: Further comprising a thermal pad (heat dissipation surface) that is electrically isolated (isolated substrate) from the one or more electrical leads lead frame). PPM does not teach: a creepage feature between the thermal pad and the one or more electrical leads. Iwade teaches at least in figures 1A-1C: A creepage feature (10 or 11) between the thermal pad (3 or 4 / PPM heat dissipation surface) and the one or more electrical leads (8a-8e). It would have been obvious to one of ordinary skill in the art to add the creepage feature to the device of PPM as Iwade teaches that the creepage feature lengthens the creepage distance, ¶¶ 0040-41, preventing the a creepage dielectric breakdown in the device, ¶ 0007. Regarding claim 8, Iwade teaches at least in figures 1A-1C: wherein the creepage feature (10/11) defines a step structure in the housing (10/11 so define such a step structure). Regarding claim 10, the prior art teaches: wherein: the creepage cutout (Kanetake figures 14-15 element 7a) is on a first surface of the housing (based upon the prior art this is obvious); the creepage feature (Iwade 10/11) is on a second surface of the housing (based upon the prior art this is obvious), the second surface being adjacent to the first surface (the bottom and the top of the device); and the thermal pad (PPM heat dissipation surface) is on the second surface bottom surface). Regarding claim 14, the prior art teaches: wherein the creepage cutout is a T-shaped creepage cutout between a first lead of the one or more electrical leads and a second lead of the one or more electrical leads (based upon the discussion of claim 1 above, and based upon Applicant’s disclosure, the shape of the creepage cutout does not have any critical aspect to the claimed device. The prior art teaches one shape produces the same result as another shape. The applications specification teaches this same thing, such that there is no criticality disclosed between one shape and another shape. As such, based upon the prior art the change in shape of the creepage cutout can be considered a change in size or proportion, a change in shape, and/or equivalent substitution. Regarding claims 16, 18, 20, 22, 24, 26, These claims are obvious for the reasons given in claim 1 and/or claim 14 above. Regarding claim 89, Claim 89 contains the subject matter of claims 1 and 6. Claim 89 is rejected for the same reasons as 1 and 6 above. Regarding claim 95, Claim 95 is rejected for the same reason as claims 1, 6 and 8 above. Regarding claim 115, the prior art teaches: wherein the creepage cutout (PPM cutout) is on a first surface of the housing (it is on the first surface) and the creepage feature (Iwade 10/11) is on a second surface of the housing (it is on the second surface), wherein the housing further comprises a third surface and an opposing fourth surface, the third surface and the fourth surface laterally bounding the second surface (the device of PPM has sides which join the top and bottom surfaces), and wherein the creepage cutout comprises: a first cutout portion defined by at least two sidewall segments, the first cutout portion extending from the first surface towards a center of the housing; and a second cutout portion defined by at least three sidewall segments, the second cutout portion extending laterally between the third surface and the fourth surface (based upon all the figures of the application the creepage cutout is formed throughout the entire height (or thickness depending on how one views the device) of the device. The prior art teaches the same with their cutout). Regarding claims 116-118, It appears that Applicant is attempting to claim the cutout is actually two cutouts. However, all the figures shows the cutout is the same shape and size on the top surface and the bottom surface of the device. This is also shown in the prior art. Therefore, the prior art teaches these claims as these claims appear to be attempting to claim a distinction where none exist. Regarding claim 132, Claim 132 is rejected for the same reasons as claims 1, 14, 16, 18, 20, 22, 24, and/or 26. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT WALL whose telephone number is (571)272-9567. The examiner can normally be reached Monday to Thursday at 7:30am to 2:30pm PST. Interviews can be scheduled on Tuesday thru Thursday at 10am PST or 2pm PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VINCENT WALL/Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Nov 30, 2023
Application Filed
Jan 26, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
62%
Grant Probability
87%
With Interview (+25.4%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 793 resolved cases by this examiner. Grant probability derived from career allow rate.

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