DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, corresponding to claims 1-13, drawn to method, in the reply filed on 03/10/2026, is acknowledged.
Information Disclosure Statement
The prior art documents submitted by applicant in the Information Disclosure Statement filed on 11/30/2023 has been considered and made of record.
Specification
The disclosure is objected to because of the following informalities:
Paragraph [0067], “switching semiconductor layer A1” should read “driving semiconductor layer A1”.
Paragraph [0095] and [0097], “driving drain electrode D2” should read “switching drain electrode D2”.
Appropriate correction is required.
Claim Objections
Claim 13 is objected to because of the following informalities: the first(second) gate electrode and the first(second) bottom metal layer facing each other, implies that the two elements are aligned so that they can see of be seen by one another. Considering Fig. 7-11, and the presence of the layers between the gate electrode and the bottom metal layer, a more appropriate description of the geometric relation between the gate electrodes and the corresponding bottom layers might be: an orthographic projection of the gate electrode in a thickness direction is surrounded by (or overlaps with) an orthographic projection of the bottom metal layer in the same direction.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 4-7 and 9-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by disclosed prior art, Imai et al., (United States Patent Number, US 11,569,324 B2), hereinafter referenced as Imai.
Regarding claim 1, Imai teaches a method of fabricating a display apparatus, the method comprising: providing a substrate having a first thin film transistor region and a second thin film transistor region (Fig.4H, substrate element #1, first thin film transistor region is the left half of the figure, second thin film transistor region is the right half of the figure); forming a first oxide semiconductor layer on the substrate in the first thin film transistor region (Fig.4H, element #14(OS1)); forming a first gate insulating layer covering the first oxide semiconductor layer in the first thin film transistor region (Fig.4H, element #L1 covers element #14(OS1)); forming a second oxide semiconductor layer on the substrate in the second thin film transistor region (Fig.4H, element #24(OS2)); forming a second gate insulating layer on the substrate on which the first gate insulating layer and the second oxide semiconductor layer are formed (Fig.4H, element #L2); forming a first gate electrode in the first thin film transistor region (Fig.4H, element #16(M1)) and forming a second gate electrode in the second thin film transistor region (Fig.4H, element #26(M1)), over the second gate insulating layer (Fog.4H, element #16(M1) and #26(M1) are over element #L2); and forming a first gate electrode stack and a second gate electrode stack (Fig.4I, first gate electrode stack is formed by elements #15 and #16(M1), and second gate electrode stack is formed by elements #25(L2) and #26(M1)), by etching the first gate insulating layer, which is under the first gate electrode (Fig.4I, part of element #L1 is etched), and etching the second gate insulating layer, which is under the first and second gate electrodes (Fig.4I, part of element #L2 is etched), by using the first gate electrode and the second gate electrode as etching masks (Fig.4I, elements #16(M1) and #26(M1) are used as masks, column 9, rows 38-41).
Regarding claim 2, Imai teaches the method of claim 1 as set forth in the anticipation rejection. Imai further teaches the method of claim 1, wherein the forming of the first gate insulating layer comprises: forming an insulating layer for the first gate insulating layer on the substrate (Fig.4H, element #L1 is formed); and removing a portion of the insulating layer from the second thin film transistor region (Fig.4I, a portion of element #L1 is removed from the right side of the figure).
Regarding claim 4, Imai teaches the method of claim 1 as set forth in the anticipation rejection. Imai further teaches the method of claim 1, wherein a thickness of each of the first gate insulating layer and the second gate insulating layer is from about 600 Å to about 2000 Å (column 14, rows 46-53).
Regarding claim 5, Imai teaches the method of claim 1 as set forth in the anticipation rejection. Imai further teaches the method of claim 1, wherein each of the first gate insulating layer and the second gate insulating layer comprises at least one of silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2) (column 14, rows 32-34).
Regarding claim 6, Imai teaches the method of claims 1 and 5 as set forth in the anticipation rejection. Imai further teaches the method of claim 5, wherein the first gate insulating layer and the second gate insulating layer are formed of a same material (column 14, rows 38-39).
Regarding claim 7, Imai teaches the method of claims 1 and 5 as set forth in the anticipation rejection. Imai further teaches the method of claim 5, wherein the first gate insulating layer and the second gate insulating layer are formed of different materials from each other (column 14, rows 32-38).
Regarding claim 9, Imai teaches the method of claim 1 as set forth in the anticipation rejection. Imai further teaches the method of claim 1, wherein the second oxide semiconductor layer has a higher electron mobility than that of the first oxide semiconductor layer (Table 1, mobility of the second oxide semiconductor is higher than 20cm^2/Vs, and the mobility of the first oxide semiconductor is between 5 and 20 cm^2/Vs).
Regarding claim 10, Imai teaches the method of claims 1 and 9as set forth in the anticipation rejection. Imai further teaches the method of claim 9, wherein the first oxide semiconductor layer has an electron mobility of about 1 to about 20 cm2/V·s, and wherein the second oxide semiconductor layer has an electron mobility of about 30 to about 80 cm2/V·s (Table 1, mobility of the second oxide semiconductor is higher than 20cm^2/Vs, and the mobility of the first oxide semiconductor is between 5 and 20 cm^2/Vs).
Regarding claim 11, Imai teaches the method of claims 1 and 9as set forth in the anticipation rejection. Imai further teaches the method of claim 9, wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises an indium-gallium-zinc oxide (InGaZnO), a hafnium-indium-zinc oxide (HfInZnO), an indium-tin-zinc oxide (InSnZnO), an aluminum-indium-tin oxide (AlInZnO), a gallium-tin-zinc oxide (GaSnZnO), a gallium-aluminum-zinc oxide (GaAlZnO), an aluminum-tin-zinc oxide (AlSnZnO), an indium-zinc oxide (InZnO), an indium-gallium oxide (InGaO), a zinc-tin oxide (ZnSnO), an aluminum-tin oxide (AlZnO), or any combination thereof (column 15, rows 46-55).
Regarding claim 12, Imai teaches the method of claims 1, 9 and 11 as set forth in the anticipation rejection. Imai further teaches the method of claim 11, wherein the first oxide semiconductor layer comprises InGaZnO, HfInZnO, AlInZnO, InZnO, InGaO, AlZnO, or any combination thereof (column 15, rows 46-59), and the second oxide semiconductor layer comprises InSnZnO, InSnGaZnO, GaSnZnO, ZnSnO, or any combination thereof (column 15, rows 50-51).
Regarding claim 13, Imai teaches the method of claim 1, as set forth in the anticipation rejection. Imai further teaches the method of claim 1, wherein the substrate further comprises: a first bottom metal layer in the first thin film transistor region (Fig.4H, element #12(ML)); a second bottom metal layer in the second thin film transistor region (Fig.4H, element #22(ML)); and a buffer layer on the first bottom metal layer and the second bottom metal layer (Fig.4H, element #4), wherein the first gate electrode and the first bottom metal layer face each other, and the second gate electrode and the second bottom metal layer face each other (Fig.4H elements #12(ML) and #16(M1) face each other and elements #22(ML) and #26(M1) face each other).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Imai.
Regarding claim 3, Imai teaches the method of claim 1 as set forth in the anticipation rejection. Imai further teaches the method of claim 1, further comprising: forming an interlayer insulating layer on the substrate (Fig.4J, element #5); forming, on the interlayer insulating layer, a first source electrode and a first drain electrode to be in contact with the first oxide semiconductor layer (Fig.4K, element #17(M2) and #18(M2)), and a second source electrode and a second drain electrode to be in contact with the second oxide semiconductor layer (Fig.4K, element #27(M2) and #28(M2)); forming a planarization layer on the interlayer insulating layer the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode (Fig.4L, element #7). In a different embodiment, Imai teaches forming an organic light-emitting device that is connected to the first source electrode or the first drain electrode on the planarization layer (Fig.11, transistor element #71, corresponds to the transistor in the first region, column 21, rows 37-39, column 24, rows 66-67, and column 25, rows 1-2, has the drain connected to an OLED, element #80, column 25, rows 19-22, see also Fig.5 for drain connection on the planarization layer). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to combine the teachings of Imai and disclose forming an organic light-emitting device that is connected to the first source electrode or the first drain electrode on the planarization layer. As disclosed by Imai, this allows the manufacture of pixels as part of an active matrix used in a display device
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Imai, in view of Isobe et al., (United States Patent Number US 6620658 B2) hereinafter referenced as Isobe.
Regarding claim 8, Imai teaches the method of claim 1 as set forth in the anticipation rejection. Imai does not teach teaches the method of claim 1 wherein a concentration of hydrogen in the first gate insulating layer is higher than a concentration of hydrogen in the second gate insulating layer. Isobe teaches wherein a concentration of hydrogen in the first gate insulating layer is higher than a concentration of hydrogen in the second gate insulating layer (column 3, rows 16-23). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Isobe and disclose a concentration of hydrogen in the first gate insulating layer is higher than a concentration of hydrogen in the second gate insulating layer. As disclosed by Isobe, hydrogen in the first insulating layer can be diffused into the semiconductor to adjust the threshold voltage of the transistor and relive internal stress, while the second insulating layer, having less hydrogen is denser and prevents oxygen diffusion to the outside (column 2, rows 63-67, column 3 rows 1-5).
Conclusion
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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