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Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
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The information disclosure statement (IDS) submitted on 12/01/2023 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner and made of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed
invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4 are rejected under 35 U.S.C. 103 as being unpatentable over Peng, Cheng-Yi () “Peng et al.” in view of LEE, Hsiang-Chen (US 20130234252 A1) “LEE et al.”.
Regarding Independent Claim 1, Peng et al. Figs. 6-26 discloses a semiconductor device, comprising:
a first vertical structure (“fin 310b” ¶ [0028]) over a substrate (“a substrate 100” ¶ [0015]), wherein the first vertical structure comprises:
a first portion with alternating first and second semiconductor layers (“Alternating epitaxial layer structure 102 may include alternating layers of a first epitaxial layer 102a and a second epitaxial layer 102b (collectively referred to as the alternating epitaxial layer structure 102)” ¶ [0018]); and
a second portion with the second semiconductor layers, wherein the second semiconductor layers from the first portion extend through the second portion (“the first epitaxial layer 102a may be a silicon germanium layer and the second epitaxial layer 102b may be a silicon layer, wherein the silicon layer will form nanowires for the n-type FinFETs and the silicon germanium layers will act as the channel regions while the silicon layers act as stressors for the p-type FinFETs.” ¶ [0018]);
a second vertical structure (“fin 310a” ¶ [0028]) over the substrate 100, wherein the second vertical structure comprises:
a third portion with the alternating first and second semiconductor layers (“Alternating epitaxial layer structure 102 may include alternating layers of a first epitaxial layer 102a and a second epitaxial layer 102b (collectively referred to as the alternating epitaxial layer structure 102)” ¶ [0018]); and
a fourth portion with the second semiconductor layers, wherein the second semiconductor layers from the third portion extend through the fourth portion (“the first epitaxial layer 102a may be a silicon germanium layer and the second epitaxial layer 102b may be a silicon layer, wherein the silicon layer will form nanowires for the n-type FinFETs and the silicon germanium layers will act as the channel regions while the silicon layers act as stressors for the p-type FinFETs.” ¶ [0018]); and
a first gate structure (“The dummy gate electrode 720 and the dummy gate dielectric 718 collectively form a dummy gate stack 726.” ¶ [0036]) over the second portion of the first vertical structure, wherein the first gate structure surrounds the second semiconductor layers of the second portion of the first vertical structure (Fig. 7 shows a first gate structure over the fin 310b and surrounds 310b); and
a second gate structure (“The dummy gate electrode 720 and the dummy gate dielectric 718 collectively form a dummy gate stack 726.” ¶ [0036]) over the fourth portion of the second vertical structure, wherein the second gate structure surrounds the second semiconductor layers of the fourth portion of the second vertical structure (Fig. 7 shows a first gate structure over the fin 310a and surrounds 310a),
wherein a first portion of the first gate structure adjacent the first vertical structure has a first bottom surface level with a second bottom surface of a second portion of the second gate structure adjacent the second vertical structure (Fig. 7 a first portion of the first gate structure adjacent the first vertical structure 310b has a first bottom surface level with a second bottom surface of a second portion of the second gate structure adjacent the second vertical structure 310a).
However, Peng et al. does not disclose, wherein a height of the second gate structure over the fourth portion of the second vertical structure is different from a height of the first gate structure over the second portion of the first vertical structure.
In the similar field of endeavor of integrated circuit structure incorporating multiple gate field effect transistors LEE et al. Figs. 1K discloses wherein a height of the second gate structure 112a of the second vertical structure (semiconductor device 160a, ¶ [0050]) is different (“The metal gate 150 is disposed on the second gate dielectric layer 110b with a second thickness h2 greater than the first thickness h1 of the poly-silicon gate 112a.” ¶ [0055]) from a height of the first gate structure 150 of the first vertical structure 160b.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the gate heights of the gate structures of Peng et al. with the different gate heights for two transistors in an integrated circuits of LEE et al. in order to increase the flexible of use of the integrated circuit. Furthermore, the method of the invention can simplify the process of forming two gates with different heights, so that the process cost and the consuming time can be decreased (LEE et al. ¶ [0065]).
Regarding Claim 2, Peng et al. as modified by LEE et al. discloses the limitations of claim 1. Peng et al further discloses, further comprising:
a first epitaxial structure (“second source/drain regions 932” ¶ [0039]) over the first portion of the first vertical structure adjacent the first gate structure; and
a second epitaxial structure (“epitaxial first source/drain regions 930” ¶ [0039]) over the third portion of the second vertical structure adjacent the second gate structure.
Regarding Claim 4, Peng et al. as modified by LEE et al. discloses the limitations of claim 1. Peng et al. Figs. 16-24 further discloses, wherein a height of the first vertical structure 310b is greater than a height of the second vertical structure 310a.
Claims 3 are rejected under 35 U.S.C. 103 as being unpatentable over Peng, Cheng-Yi () “Peng et al.” in view of LEE, Hsiang-Chen (US 20130234252 A1) “LEE et al.” further in view of Hsu, William (US 20200006478 A1) “Hsu et al.”.
Regarding Claim 3, Peng et al. as modified by LEE et al. discloses the limitations of claim 1. However, Peng et al. does not disclose, wherein a width of the first vertical structure is different than a width of the second vertical structure.
In the similar field of endeavor of transistors, Hsu et al. Figs. 5A-5B discloses wherein a width of the first vertical structure is different than a width of the second vertical structure (Figs. 5A-5B show the first and second vertical structures have different width).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the widths of the vertical structures of Peng et al. with the vertical structures with different widths of Hsu et al. in order to be useful where various transistor structures have nanowires/nanoribbons of different widths (i.e., channel widths or fin widths). In accordance with some embodiments, methodologies of the present disclosure enable uniform alignment of the cavity spacer with the gate structure. Such a feature is an advantage for nanowire transistors of different nanowire widths (Wsi) on the same chip or the same device. For example, techniques of the present disclosure may benefit an integrated circuit (IC) with various nanowire transistor structures, some of which are located in a first region of the IC and have a first channel width (e.g., nanowire transistors), and others located in a second region of the IC that have a second channel width that is different from the first channel width (e.g., nanoribbon transistors) (Hsu et al. ¶ [0032]).
Claims 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Peng, Cheng-Yi () “Peng et al.” in view of LEE, Hsiang-Chen (US 20130234252 A1) “LEE et al.” further in view of Sung, Min Gyu (US 10170484 B1) “Sung et al.”.
Regarding Claim 5, Peng et al. as modified by LEE et al. discloses the limitations of claim 1. However, Peng et al. does not disclose, wherein a number of semiconductor layers in the second portion of the first vertical structure is greater than a number of semiconductor layers in the fourth portion of the second vertical structure.
In the similar field of endeavor of transistors, Sung et al. Figs. 8B and 14B-14E discloses wherein a number of semiconductor layers in the second portion of the first vertical structure is greater than a number of semiconductor layers in the fourth portion of the second vertical structure (“gate-all-around-field effect transistors (GAAFETs) can be formed using these multi-layer fins (see process 110). The GAAFETs can be formed so as to include: a first GAAFET, which includes multiple first nanoshapes formed using the multiple layers of the first semiconductor material 204 in the first fin 211; a second GAAFET, which includes one or more second nanoshapes formed using the one or more layers of the first semiconductor material 204 in the second fin 212 such that it has a lesser number of channel regions than the first GAAFET; and, optionally, a third GAAFET, which includes one or more first nanoshapes formed using the one or more layers of the first semiconductor material 204 in the third fin 213 such that it has the same number or a lesser number of channel regions than the second GAAFET.” ).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the number of the semiconductor layers in the vertical structures of Peng et al. with the different number of the semiconductor layer in the vertical structures of Sung et al. in order have lesser channels in the second fin than the first fin. Since the second GAAFET has fewer channel regions than the first GAAFET, the second GAAFET will have a lower drive current than the first GAAFET (Sung et al. Column 10, Lines 17-20).
Regarding Claim 7, Peng et al. as modified by LEE et al. discloses the limitations of claim 1. Peng et al. Figs. 6-7 further discloses, wherein the second gate structure 310a comprises a gate dielectric layer 718 (“gate dielectric 718” ¶ [0036]) and a conductive electrode (“gate electrode 720” ¶ [0036]) over the gate dielectric layer 718, further comprising a capping layer (“hardmask layer 622” ¶ [0036]) over the second gate structure.
However, Peng et al. does not disclose, wherein the capping layer contacts the gate dielectric layer.
In the similar field of endeavor of transistors, Sung et al. Figs. 8B and 14B-14E discloses wherein the capping layer 263 contacts (Fig. 14 shows 263 contacts 261) the gate dielectric layer 261.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the vertical structures of Peng et al. with the vertical structures of Sung et al. in order have lesser channels in the second fin than the first fin. Since the second GAAFET has fewer channel regions than the first GAAFET, the second GAAFET will have a lower drive current than the first GAAFET (Sung et al. Column 10, Lines 17-20).
Claims 6 are rejected under 35 U.S.C. 103 as being unpatentable over Peng, Cheng-Yi () “Peng et al.” in view of LEE, Hsiang-Chen (US 20130234252 A1) “LEE et al.” further in view of Witters, Liesbeth (US 20170025314 A1) “Witters et al.”.
Regarding Claim 6, Peng et al. as modified by LEE et al. discloses the limitations of claim 1. However, Peng et al. does not disclose, wherein a top surface of the second semiconductor layers are parallel to a (100) crystal plane.
In the similar field of endeavor of transistors, Witters et al. ¶ [0092-0094] discloses removal of sacrificial layers in making nano-sheet device structures is dependent upon crystal plane etch rates and should be chosen based upon final device requirements), it would have been obvious to a person of ordinary skill in the art at the time of the invention to set the crystal orientation through routine experimentation in order to achieve desired transistor characteristics and manufacturability. It has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
wherein a top surface of the second semiconductor layers are parallel to a (100) crystal plane.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the top surface of Peng et al. incorporating the teachings of Witters et al. in order to take into account the crystal plane orientations, as the anisotropic process/etching is also dependent on the crystal plane. The skilled person will recognize that taking into account the crystal plane orientations of course need to be consistent with final device requirements (Witters et al., ¶ [0092]).
Claims 8 and 10-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sung, Min Gyu (US 10170484 B1) “Sung et al.” in view of LEE, Hsiang-Chen (US 20130234252 A1) “LEE et al.”.
Regarding Independent Claim 8, Sung et al. Fig. 14A-14E discloses a semiconductor device (“IC structure” Column 16, line 2) comprising:
a first transistor (“two first transistors 250a (i.e., the left-side and right-side N-type pull-down transistors PD-L and PD-R);” Column 16, Lines 3-4) comprising:
first source/drain regions (“first source/drain regions 241a” Column 16, Line 10);
a first channel region (“multiple first channel regions and, particularly, multiple horizontally oriented first nano-shapes 244a” Column 16, Lines 11-12) interposed between the first source/drain regions (“multiple first channel regions and, particularly, multiple horizontally oriented first nanoshapes 244a, which extend laterally between the first source/drain regions 241a”, Column 16, Lines 11-13), the first channel region comprising a first plurality of first semiconductor layers; and
a first gate structure over the first channel region, wherein the first gate structure extends between adjacent ones of the first plurality of first semiconductor layers (“a first gate 243a. The first gate 243a can wrap around the first nanoshapes 244a (e.g., filling the spaces between the substrate 201 and lowest first nanoshape, on the sides of the first nanoshapes, between the first nanoshapes and above the highest first nanoshape).” Column 16, Lines 20-24); and
a second transistor (“two second transistors 250b (i.e., left-side and right-side N-type pass-gate transistors PG-L and PG-R);” Column 16, Lines 5-6) comprising:
second source/drain regions (“Each second transistor 250b (e.g., PG-L and PG-R) can have second source/drain regions 241b” Column 16, Lines 25-26);
a second channel region interposed between the second source/drain regions, the second channel region comprising a second plurality of first semiconductor layers (“one or more horizontally oriented second nanoshapes 244b, which extend laterally between the second source/drain regions 241b.” Column 16, Lines 28-30); and
a second gate structure over the second channel region, wherein the second gate structure extends between adjacent ones of the second plurality of first semiconductor layers (“each second transistor 250b can further include a second gate 243b. The second gate 243b can wrap around each second nanoshape(s) 244b.” Column 16, Lines 43-45);
However, Sung et al. does not disclose, wherein a height of the first gate structure is different from a height of the second gate structure, wherein a lower surface of the first gate structure is level with a lower surface of the second gate structure.
In the similar field of endeavor of integrated circuit structure incorporating multiple gate field effect transistors LEE et al. Figs. 1K discloses wherein a height of the first gate structure is different (“The metal gate 150 is disposed on the second gate dielectric layer 110b with a second thickness h2 greater than the first thickness h1 of the poly-silicon gate 112a.” ¶ [0055]) from a height of the second gate structure 112a, wherein a lower surface of the first gate structure 150 is level with a lower surface of the second gate structure 112a.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the gate heights of the gate structures of Sung et al. with the different gate heights for two transistors in an integrated circuits of LEE et al. in order to increase the flexible of use of the integrated circuit. Furthermore, the method of the invention can simplify the process of forming two gates with different heights, so that the process cost and the consuming time can be decreased (LEE et al. ¶ [0065]).
Regarding Claim 10, Sung et al. as modified by LEE et al. discloses the limitations of claim 8. Sung et al. further discloses, wherein the first transistor and the second transistor have different drive current characteristics the second GAAFET has fewer channel regions than the first GAAFET, the second GAAFET will have a lower drive current than the first GAAFET (Column 10, Lines 17-20).
Regarding Claim 11, Sung et al. as modified by LEE et al. discloses the limitations of claim 8. Sung et al. Figs. 8B and 14B-14E further discloses, wherein a number of the first semiconductor layers of the first plurality of first semiconductor layers is different than a number of the first semiconductor layers of the second plurality of first semiconductor layers (“gate-all-around-field effect transistors (GAAFETs) can be formed using these multi-layer fins (see process 110). The GAAFETs can be formed so as to include: a first GAAFET, which includes multiple first nanoshapes formed using the multiple layers of the first semiconductor material 204 in the first fin 211; a second GAAFET, which includes one or more second nanoshapes formed using the one or more layers of the first semiconductor material 204 in the second fin 212 such that it has a lesser number of channel regions than the first GAAFET; and, optionally, a third GAAFET, which includes one or more first nanoshapes formed using the one or more layers of the first semiconductor material 204 in the third fin 213 such that it has the same number or a lesser number of channel regions than the second GAAFET.” ).
Regarding Claim 12, Sung et al. as modified by LEE et al. discloses the limitations of claim 8. Sung et al. Figs. 12A-12C and 14B-14E further discloses, wherein the first source/drain regions comprise alternating layers of the first plurality of first semiconductor layers and a plurality of second semiconductor layers (“the remaining portion of the first multi-layer fin 211, which is exposed in the first gate opening 242a in the PU-L Area, includes all the alternating layers of the second semiconductor material 203 and the first semiconductor material 204 that were originally present in the multi-layer stack 202;” Column 13, Lines 23-28).
Regarding Claim 13, Sung et al. as modified by LEE et al. discloses the limitations of claim 8. Sung et al. Figs. 12A-14E further discloses, wherein the second gate structure comprises a gate dielectric layer and a conductive electrode over the gate dielectric layer (“in each of the transistors 250a-250c described above, isolation regions 265 can provide electrical isolation between the gates 243a-243c and the adjacent source/drain regions 241a-241c, respectively. Specifically, the isolation regions 265 can be aligned below the gate sidewall spacers 261 and can be above and below the ends of the nanoshapes such that each source/drain region of a transistor has a side that abuts one end of each of the nanoshape(s) of that transistor as well as isolation regions 265 above and below those nanoshape(s).” Column 17, Lines 62-67, Colum 18, Lines 1-4), further comprising a capping layer 263 over the second gate structure PG-R, wherein the capping layer contacts the gate dielectric layer (Fig. 14 shows 263 contacts 261).
Regarding Claim 14, Sung et al. as modified by LEE et al. discloses the limitations of claim 8. Sung et al. Figs. 12A-14E further discloses, further comprising a third transistor PU-L, the third transistor PU-L comprising: a fin (“third transistor 250c” Column 16, Line 1); a third channel region in the fin (“one or more third channel regions and, particularly, one or more horizontally oriented third nanoshapes 244c, which extend laterally between the third source/drain regions 241c” Column 16, Lines 48-50); and a third gate structure over the third channel region of the fin (“ third gate 243c can wrap around each third nanoshape(s) 244c.” Column 16, Lines 66-67).
Regarding Independent Claim 15, Sung et al. Fig. 14A-14E discloses a semiconductor device (“IC structure” Column 16, line 2) comprising:
a first transistor (“two first transistors 250a (i.e., the left-side and right-side N-type pull-down transistors PD-L and PD-R);” Column 16, Lines 3-4) comprising:
first source/drain regions (“first source/drain regions 241a” Column 16, Line 10);
a first channel region (“multiple first channel regions and, particularly, multiple horizontally oriented first nano-shapes 244a” Column 16, Lines 11-12) interposed between the first source/drain regions, the first channel region comprising a plurality of first semiconductor layers (“multiple first channel regions and, particularly, multiple horizontally oriented first nanoshapes 244a, which extend laterally between the first source/drain regions 241a”, Column 16, Lines 11-13); and
a first gate structure over the first channel region, wherein the first gate structure extends between adjacent ones of the plurality of first semiconductor layers (“a first gate 243a. The first gate 243a can wrap around the first nanoshapes 244a (e.g., filling the spaces between the substrate 201 and lowest first nanoshape, on the sides of the first nanoshapes, between the first nanoshapes and above the highest first nanoshape).” Column 16, Lines 20-24); and
a second transistor (“two second transistors 250b (i.e., left-side and right-side N-type pass-gate transistors PG-L and PG-R);” Column 16, Lines 5-6) comprising:
second source/drain regions (“Each second transistor 250b (e.g., PG-L and PG-R) can have second source/drain regions 241b” Column 16, Lines 25-26);
a second channel region interposed between the second source/drain regions, the second channel region comprising a plurality of second semiconductor layers (“one or more horizontally oriented second nanoshapes 244b, which extend laterally between the second source/drain regions 241b.” Column 16, Lines 28-30); and
a second gate structure over the second channel region, wherein the second gate structure extends between adjacent ones of the plurality of second semiconductor layers (“each second transistor 250b can further include a second gate 243b. The second gate 243b can wrap around each second nanoshape(s) 244b.” Column 16, Lines 43-45);
However, Sung et al. does not disclose, wherein an upper surface of the first gate structure is not level with an upper surface of the second gate structure, wherein a lower surface of the first gate structure is level with a lower surface of the second gate structure.
In the similar field of endeavor of integrated circuit structure incorporating multiple gate field effect transistors LEE et al. Figs. 1K discloses wherein an upper surface of the first gate structure is not level with an upper surface of the second gate structure (“The metal gate 150 is disposed on the second gate dielectric layer 110b with a second thickness h2 greater than the first thickness h1 of the poly-silicon gate 112a.” ¶ [0055]), wherein a lower surface of the first gate structure 150 is level with a lower surface of the second gate structure 112a.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the gate heights of the gate structures of Sung et al. with the different gate heights for two transistors in an integrated circuits of LEE et al. in order to increase the flexible of use of the integrated circuit. Furthermore, the method of the invention can simplify the process of forming two gates with different heights, so that the process cost and the consuming time can be decreased (LEE et al. ¶ [0065]).
Regarding Claim 16, Sung et al. as modified by LEE et al. discloses the limitations of claim 15. Sung et al. Figs. 12A-14E further discloses, wherein the first semiconductor layers 204 (“the first semiconductor material 204 can be monocrystalline silicon” Column 7, Lines 48-49) and the second semiconductor layers are a same (Both 204 and 203 has same Silicon material) semiconductor material (“The second semiconductor material 203 can be monocrystalline silicon germanium” Column 7, Lines 49-50).
Regarding Claim 17, Sung et al. as modified by LEE et al. discloses the limitations of claim 15. Sung et al. Figs. 13A-14E further discloses, wherein an upper surface of an uppermost first semiconductor layer of the plurality of first semiconductor layers is higher than an upper surface of an uppermost second semiconductor layer of the plurality of second semiconductor layers (Fig. 13A-14E show an upper surface of an uppermost first semiconductor layer of the plurality of first semiconductor layers is higher than an upper surface of an uppermost second semiconductor layer of the plurality of second semiconductor layers).
Regarding Claim 18, Sung et al. as modified by LEE et al. discloses the limitations of claim 15. Sung et al. Figs. 13A-14E further discloses, wherein the plurality of first semiconductor layers has a first number of layers, wherein the plurality of second semiconductor layers has a second number of layers, wherein the first number of layers is greater than the second number of layers (Fig. 13A-14E show wherein the plurality of first semiconductor layers has a first number of layers, wherein the plurality of second semiconductor layers has a second number of layers, wherein the first number of layers is greater than the second number of layers).
.
Regarding Claim 19, Sung et al. as modified by LEE et al. discloses the limitations of claim 15. Sung et al. Figs. 13A-14E further discloses, wherein the first source/drain regions comprise an epitaxial region, wherein portions of the plurality of first semiconductor layers extend into the epitaxial regions (“source/drain regions can be formed, for example, by epitaxial deposition of in situ-doped semiconductor material (e.g., on the exposed surfaces of the first semiconductor material 204).” Column 12, Lines 37-40).
Regarding Claim 20, Sung et al. as modified by LEE et al. discloses the limitations of claim 15. Sung et al. Figs. 13A-14E further discloses, wherein the first source/drain regions comprise epitaxial regions, wherein the first source/drain regions comprise a stack of alternating layers of the plurality of first semiconductor layers and a plurality of third semiconductor layers, wherein the epitaxial regions extend along sidewalls of the stack (“source/drain regions can be formed, for example, by epitaxial deposition of in situ-doped semiconductor material (e.g., on the exposed surfaces of the first semiconductor material 204).” Column 12, Lines 37-40).
Claims 9 are rejected under 35 U.S.C. 103 as being unpatentable over Sung, Min Gyu (US 10170484 B1) “Sung et al.” in view of LEE, Hsiang-Chen (US 20130234252 A1) “LEE et al.” further in view of Hsu, William (US 20200006478 A1) “Hsu et al.”.
Regarding Claim 9, Sung et al. as modified by LEE et al. discloses the limitations of claim 8. However, Sung et al. does not disclose, wherein the first plurality of first semiconductor layers in the first channel region have a first width, wherein the second plurality of first semiconductor layers in the second channel region having a second width, the second width being different from the first width.
In the similar field of endeavor of transistors, Hsu et al. Figs. 5A-5B discloses wherein the first plurality of first semiconductor layers in the first channel region have a first width, wherein the second plurality of first semiconductor layers in the second channel region having a second width, the second width being different from the first width (Figs. 5A-5B show the first and second vertical structures have different width).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the widths of the vertical structures of Peng et al. with the vertical structures with different widths of Hsu et al. in order to be useful where various transistor structures have nanowires/nanoribbons of different widths (i.e., channel widths or fin widths). In accordance with some embodiments, methodologies of the present disclosure enable uniform alignment of the cavity spacer with the gate structure. Such a feature is an advantage for nanowire transistors of different nanowire widths (Wsi) on the same chip or the same device. For example, techniques of the present disclosure may benefit an integrated circuit (IC) with various nanowire transistor structures, some of which are located in a first region of the IC and have a first channel width (e.g., nanowire transistors), and others located in a second region of the IC that have a second channel width that is different from the first channel width (e.g., nanoribbon transistors) (Hsu et al. ¶ [0032]).
Conclusion
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/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893