DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-6, 12 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the terms “about” in line 2 of the claim, which are relative terms which renders the claim indefinite. The terms “about” are not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
For example, one of ordinary skill in the art could not make a clear determination of whether or not a specific value reasonably constitutes as being “about 10 angstroms” without clear upper and lower limits defined for the term “about”.
Claim 6 recites the terms “about” in lines 1-2 of the claim, which are relative terms which renders the claim indefinite. The terms “about” are not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
For example, one of ordinary skill in the art could not make a clear determination of whether or not a specific value reasonably constitutes as being “about 40 angstroms” without clear upper and lower limits defined for the term “about”.
Claim 12 recites the terms “about” in line 2 of the claim, which are relative terms which renders the claim indefinite. The terms “about” are not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
For example, one of ordinary skill in the art could not make a clear determination of whether or not a specific value reasonably constitutes as being “about 2.00%” without clear upper and lower limits defined for the term “about”.
Claim 19 recites the terms “about” in line 2 of the claim, which are relative terms which renders the claim indefinite. The terms “about” are not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
For example, one of ordinary skill in the art could not make a clear determination of whether or not a specific value reasonably constitutes as being “about 0.4nm” without clear upper and lower limits defined for the term “about”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 7-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cai et al. (US 2017/0092645 A1, hereinafter “Cai”).
Regarding independent claim 1, Cai discloses a method of forming a semiconductor device, the method comprising:
forming a first spacer layer 502 (“spacers”- ¶0065) over a fin structure 306a (“fins”- ¶0062) and a dummy gate stack 301a (“dummy gate stacks”- ¶0062), the dummy gate stack 301a being over the fin structure 306a, the dummy gate stack 301a comprising a dummy gate 308 (“polysilicon layer”- ¶0062) and a mask layer 310 (“capping layer”- ¶0062) over the dummy gate 308 (see Figs. 3A-5C);
depositing a sacrificial layer 702 (“insulator material layer”- ¶0066) over the first spacer layer 502 (see Figs. 7A-7C);
performing an etch process to expose portions (i.e., the exposed portions of 306a as shown in Fig. 8B) of the fin structure 306a while sidewalls of the dummy gate 308 remain completely covered by the sacrificial layer 702 and the first spacer layer 502 in a cross-sectional view, wherein at least a portion of a sidewall (i.e., top horizontal sidewall of 310) of the mask layer 310 is exposed (¶0067) (see Figs. 8A-8C);
growing source/drain regions 902a, 902b (“source/drain regions”- ¶0068) from the exposed portions of the fin structure 306a (¶0068) (see Figs. 9A-9C);
removing the sacrificial layer 702 to expose the first spacer layer 502 adjacent the dummy gate stack 301a (¶0072) (see Figs. 13A-13C); and
replacing the dummy gate stack 301a with a gate structure 1701a (“gate stacks”- ¶0076) (see Figs. 16A-17C).
Regarding claim 2, Cai discloses wherein the first spacer layer 502 comprises one or more low-k dielectric materials having a dielectric constant (k) less than 3.9, since layer 502 comprises SiOCN (¶0063) which has a dielectric constant in the claimed range (as evidenced by Bergendah et al. (US 2017/0229463 A1)- see paragraph [0052]- “the dielectric constant of SiOCN may range from 2.8 to 3”).
Regarding claim 7, Cai discloses wherein removing the sacrificial layer 702 is performed after growing the source/drain regions 902a, 902b (see Figs. 9A-13C).
Regarding claim 8, Cai discloses the method further comprising:
forming a third dielectric layer 1002 (“layer of insulator material”- ¶0069) on the first spacer layer 502, wherein the third dielectric layer 1002 directly contacts the first spacer layer 502 (see Figs. 10A-10C); and
removing a portion of the third dielectric layer 1002 (see Figs. 11A-12C).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable and obvious over Cai.
Regarding claim 5, Cai discloses wherein the first spacer layer 502 has a thickness (see Figs. 5A-5C).
Cai does not expressly disclose wherein the thickness is in a range from about 10 angstroms to about 30 angstroms.
However, it would have been obvious to form the thickness of the first spacer layer within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 6, Cai discloses wherein the sacrificial layer 702 has a thickness (see Figs. 7A-7C).
Cai does not expressly disclose wherein the thickness is in a range from about 40 angstroms to about 60 angstroms.
However, it would have been obvious to form the thickness of the sacrificial layer within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Cai in view of Kanakasabapathy et al. (US 2017/0162685 A1, hereinafter “Kanakasabapathy”).
Regarding claim 3, Cai discloses wherein the sacrificial layer 702 comprises an insulating material such as an oxide or carbide material (¶0066).
Cai does not expressly disclose wherein the insulating material is silicon carbide nitride, silicon oxide, or silicon oxynitride.
Kanakasabapathy discloses a method of forming a semiconductor device comprising forming an insulating layer 902 (“insulating layer”- ¶0050) comprised of an insulating material such as silicon oxynitride (¶0050).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cai such that the insulating material of the sacrificial layer is silicon oxynitride as taught by Kanakasabapathy for the purpose of utilizing a suitable and well-known type of dielectric material for the insulating material as known in the art (Kanakasabapathy ¶0050).
Regarding claim 4, Cai discloses wherein the first spacer layer 502 comprises silicon oxycarbide or silicon oxycarbonnitride (¶0063).
Allowable Subject Matter
Claims 9-11, 13-18 and 20 are allowed.
Regarding independent claim 9, Cai discloses a method of forming a semiconductor device, the method comprising:
forming a first dummy gate structure 301b (“dummy gate stacks”- ¶0062) over a first fin structure 306a (“fins”- ¶0062) and a second dummy gate structure 301a (“dummy gate stacks”- ¶0062) over a second fin structure 306b (“fins”- ¶0062), the first dummy gate structure 301b comprising a first dummy gate 308 (“polysilicon layer”- ¶0062) and a first mask layer 310 (“capping layer”- ¶0062) over the first dummy gate 308, the second dummy gate structure 301a comprising a second dummy gate 308 (“polysilicon layer”- ¶0062) and a second mask layer 310 (“capping layer”- ¶0062) over the second dummy gate 308 (see Figs. 3A-3C);
forming a first spacer layer 502 (“spacers”- ¶0065) over the first dummy gate structure 301b, the first fin structure 306a, the second dummy gate structure 301a, and the second fin structure 306b (see Figs. 5A-5B);
forming a first sacrificial layer 702 (“insulator material layer”- ¶0066) over the first spacer layer 502 (see Figs. 7A-7C);
forming first source/drain regions 902a, 902b (“source/drain regions”- ¶0068) adjacent the first dummy gate structure 301b (¶0068) (see Figs. 9A-9C);
after forming the first source/drain regions 902a, 902b, removing the first sacrificial layer 702 (¶0072) (see Figs. 13A-13C);
forming a second sacrificial layer 1002 (“layer of insulator material”- ¶0069) over the first spacer layer 502, the second dummy gate structure 301a, and the second fin structure 306b (see Figs. 10A-10C); and
forming second source/drain regions 1402a, 1402b (“fins”- ¶0073) adjacent the second dummy gate structure 3011 (¶0073) (see Figs. 14A-14C).
Cai does not expressly disclose removing portions of the first sacrificial layer and the first spacer layer to expose the first fin structure and at least a portion of the first mask layer, and removing portions of the second sacrificial layer and the first spacer layer to expose the second fin structure and at least a portion of the second mask layer.
Thus, regarding independent claim 9, the claim is allowed, because the prior art of record including Cai, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “removing portions of the first sacrificial layer and the first spacer layer to expose the first fin structure and at least a portion of the first mask layer” and “removing portions of the second sacrificial layer and the first spacer layer to expose the second fin structure and at least a portion of the second mask layer”
Claims 10-11 and 13-14 are allowed as being dependent on allowed claim 9.
Regarding independent claim 15, Cai discloses a semiconductor device, the method comprising:
forming a first dummy gate 301b (“dummy gate stacks”- ¶0062) over a first fin structure 306a (“fins”- ¶0062) and a second dummy gate 301a (“dummy gate stacks”- ¶0062) over a second fin structure 306b (“fins”- ¶0062) (see Figs. 3A-3C);
forming a first spacer layer 502 (“spacers”- ¶0065) over the first dummy gate 301b, the first fin structure 306a, the second dummy gate 301a, and the second fin structure 306b (see Figs. 5A-5B);
forming a first sacrificial layer 702 (“insulator material layer”- ¶0066) over the first spacer layer 502 (see Figs. 7A-7C);
forming first source/drain regions 902a, 902b (“source/drain regions”- ¶0068) on the first fin structure 306a (¶0068) (see Figs. 9A-9C);
removing the first sacrificial layer 702 from over the first dummy gate 301b and the second dummy gate 301a (see Figs. 8A-8C and 13A-13C);
forming a second sacrificial layer 1002 (“layer of insulator material”- ¶0069) over the first spacer layer 502, the first dummy gate 301b, the second dummy gate 301a, and the second fin structure 306b (see Figs. 10A-10C); and
forming second source/drain regions 1402a, 1402b (“fins”- ¶0073) on the second fin structure 306b (¶0073) (see Figs. 14A-14C).
Cai does not expressly disclose removing portions of the first sacrificial layer and the first spacer layer to expose an upper portion of the first fin structure, wherein the first sacrificial layer remains over the second dummy gate, and removing portions of the second sacrificial layer and the first spacer layer to expose an upper portion of the second fin structure, wherein, after removing portions of the second sacrificial layer and the first spacer layer to expose the second fin structure, portions of the first spacer layer remain along sidewalls of the second fin structure to form spacer portions, wherein the second sacrificial layer remains over the first dummy gate.
Thus, regarding independent claim 15, the claim is allowed, because the prior art of record including Cai, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “removing portions of the first sacrificial layer and the first spacer layer to expose an upper portion of the first fin structure, wherein the first sacrificial layer remains over the second dummy gate” and “removing portions of the second sacrificial layer and the first spacer layer to expose an upper portion of the second fin structure, wherein, after removing portions of the second sacrificial layer and the first spacer layer to expose the second fin structure, portions of the first spacer layer remain along sidewalls of the second fin structure to form spacer portions, wherein the second sacrificial layer remains over the first dummy gate”.
Claims 16-18 and 20 are allowed as being dependent on allowed claim 15.
Claims 12 and 19 (which depend from allowed claims 9 and 15, respectively) would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
JangJian et al. (US 2016/0322473 A1), which discloses a method of forming a semiconductor device comprising forming multiple layers on fins.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAY C CHANG/Primary Examiner, Art Unit 2817