Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 15-19 in the reply filed on 2/13/2026 is acknowledged.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 15 and 16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hsu (2020041149).
Regarding claim 15, Hsu teaches a method of making a package structure, the method comprising:
forming a first semiconductor die (fig. 4: 330s) including a backside metal film (fig. 10: CM; par. 26) on a backside of the first semiconductor die;
forming a lower package (fig. 8: 10) including the first semiconductor;
attaching an upper package (fig. 11: 20) to the lower package (fig. 11); and
forming a thermally conductive underfill layer (fig. 11: UF; par. 73 teaches UF can be material used form layer 140; par. 45 teaches materials for 140, these materials being thermally conductive e.g. silica) between the lower package and the upper package such that the thermally conductive underfill layer contacts the backside metal film in the lower package (please see fig .11).
Regarding claim 16, Hsu teaches a method of claim 15, wherein the backside metal film comprises a sintered metal film and the forming of the backside metal film () comprises:
forming a metal film material layer including a plurality of metal particles on a backside surface of the first semiconductor die (par. 26 teaches adding silver paste and solder paste to the diel); and
heating the metal film material layer to form the sintered metal film (par. 26 teaches adding silver paste and solder paste to the die; both paste involve sintering. Silver sintering paste utilizes a solidstate sintering process, where heat is applied to the paste, allowing silver particles to diffuse and create a robust bond, which is different from traditional soldering methods that form a mechanical bond. Soldering also involves sintering, but it typically refers to the melting and solidification of solder to create a mechanical).
Claims 21-27 and 29-34 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hsu (2020041149).
Regarding claim 21, Hsu teaches a method of making a package structure, the method comprising:
forming a lower package (fig. 11: 20) including a first semiconductor die (fig. 11: 220a) having a metal film (fig. 10: CM; par. 26);
attaching an upper package to the lower package (fig. 11); and
forming an underfill layer on the metal film between the lower package and the upper package ((fig. 11: UF; par. 73 teaches UF can be material used form layer 140; par. 45 teaches materials for 140, these materials being thermally conductive e.g. silica).
Regarding claim 22, Hsu teaches a method of claim 21, wherein the forming of the underfill layer is performed such that the underfill layer contacts an upper surface of the metal film (fig. 11).
Regarding claim 23, Hsu teaches a method of claim 21, wherein the forming of the lower package is performed such that the metal film comprises a backside metal film on a backside of the first semiconductor die (fig. 7).
Regarding claim 24, Hsu teaches a method of claim 23, wherein the forming of the lower package is performed such that the backside metal film covers an entirety of the backside of the first semiconductor die (fig. 7).
Regarding claim 25, Hsu teaches a method of claim 21, wherein the forming of the underfill layer is performed such that the underfill layer comprises a thermally conductive underfill layer (fig. 11: UF; par. 73 teaches UF can be material used form layer 140; par. 45 teaches materials for 140, these materials being thermally conductive e.g. silica).
Regarding claim 26, Hsu teaches a method of claim 21, wherein the forming of the underfill layer is performed such that the upper package is electrically coupled to the lower package through the underfill layer (please see fig. 11).
Regarding claim 27, Hsu teaches a method of claim 21, wherein the metal film comprises a sintered metal film and the forming of the lower package comprises:
forming a metal film material layer including a plurality of metal particles on a backside surface of the first semiconductor die; and
heating the metal film material layer to form the sintered metal film (par. 26 teaches adding silver paste and solder paste to the die; both paste involve sintering. Silver sintering paste utilizes a solidstate sintering process, where heat is applied to the paste, allowing silver particles to diffuse and create a robust bond, which is different from traditional soldering methods that form a mechanical bond. Soldering also involves sintering, but it typically refers to the melting and solidification of solder to create a mechanical).
Regarding claim 29, Hsu teaches a method of claim 21, further comprising:
forming the upper package to include a package substrate and a second semiconductor die attached to the package substrate, wherein the forming of the underfill layer is performed such that underfill material substantially fills a gap between the package substrate and the metal film (please see fig. 11).
Regarding claim 30, Hsu teaches a method of claim 29, wherein the attaching of the upper package to the lower package comprises electrically coupling the second semiconductor die to the lower package through the package substrate (please see fig. 11).
Regarding claim 31, Hsu teaches a method of claim 29, wherein the forming of the lower package comprises forming a through via adjacent the first semiconductor die and forming a frontside redistribution layer (RDL) structure (fig. 11: 150) on the first semiconductor die and the through via, and the forming of the upper package is performed such that the second semiconductor die comprises a dynamic random access memory (DRAM) die electrically coupled to the frontside RDL structure by the through via (par. 68).
Regarding claim 32, Hsu teaches a method of claim 21, wherein the forming of the underfill layer is performed such that the underfill layer has a thickness greater than a thickness of the metal film (please see fig. 11).
Regarding claim 33, Hsu teaches a method of claim 21, wherein the forming of the lower package comprises forming an encapsulation layer (fig. 11: 140) around the metal film.
Regarding claim 34, Hsu teaches a method of claim 33, wherein the forming of the lower package comprises forming a through via (fig. 11: 120) adjacent the first semiconductor die and forming the encapsulation layer between the metal film and the through via (please see fig. 11).
Claim 35 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hsu (2020041149).
Regarding claim 35, Hsu teaches a method of making a package structure, the method comprising:
forming a sintered metal layer (par. 26 teaches adding silver paste and solder paste to the die; both paste involve sintering. Silver sintering paste utilizes a solidstate sintering process, where heat is applied to the paste, allowing silver particles to diffuse and create a robust bond, which is different from traditional soldering methods that form a mechanical bond. Soldering also involves sintering, but it typically refers to the melting and solidification of solder to create a mechanical);
applying the sintered metal layer to a surface of a semiconductor layer (fig. 3) of a first semiconductor die (fig. 4: 330s; please see limitation above);
forming a lower package (fig. 8) including first semiconductor die on a first carrier substrate (fig. 8: 112) such that the sintered metal layer is attached to the carrier substrate (fig. 8);
detaching the lower package (fig. 9) from the carrier substrate and attaching an upper package (fig. 11: 20) to the lower package (fig. 11); and
forming an underfill layer (fig. 11: UF; par. 73 teaches UF can be material used form layer 140; par. 45 teaches materials for 140, these materials being thermally conductive e.g. silica) on the sintered metal layer between the lower package and the upper package.
Allowable Subject Matter
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 18 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 19 is objected to based on its dependency on claim 18.
Claim 28 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALEB E HENRY whose telephone number is (571)270-5370. The examiner can normally be reached Mon-Fri.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CALEB E HENRY/Primary Examiner, Art Unit 2818