Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 7-14 are rejected under 35 U.S.C. 103 as being unpatentable over HSU et al. [US 2016/0335386 A1].
As per claim 1, Hsu et al. teach a method, comprising:
forming a plurality of macros [0037 macro blocks MB] including a first macro [FIG. 10 MB1] and a second macros [FIG. 10 MB2] that extend in a first direction [as depicted in FIG. 10],
wherein the plurality of macros are formed around a logic boundary [0026 RTL describing the function performed, 0027 macro grouping procedure according to hierarchy information of the macro blocks, in other words macros are formed along logic boundaries such as a specific processor, a memory, and so on]; and
forming a first channel of a plurality of channels [0037 and FIG. 10 CH1], wherein the first channel is interposed between the first macro and the second macro [as depicted] and extend in the first direction [0027 the macro placement of all the macro blocks can provide an optimum blank space between the macro blocks to optimize routability and satisfy timing constraints for the IC, 0029 the processor dynamically adjusts a plurality of channel widths between the macro blocks].
However, Hsu et al. does not explicitly teach a first pin and a second pin. Yet, the reference does describe the pin locations of each macro block MB as layout information and constraints [0029], and adjusting the channel widths between macro blocks according to data flow control for the IC extracted from connections by EDA tools or input by designers [0032]. In other words, having a description of the pin locations of each MB and the function performed, including hierarchy information and constraints, to optimize routability, would obviously result in wherein a first pin of the first macro and a second pin of the second macro are separated along a second direction different from the first direction, and the second pin of the second macro is opposite of the logic boundary. Thus, the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains because the macro placement of all the macro blocks can provide an optimum blank space between the macro blocks to optimize routability and satisfy timing constraints for the IC [0027], and it is easy to perform routing [0037].
2. The method of claim 1, wherein forming the plurality of macros comprises: forming a first portion of the plurality of macros closer to a centroid of a core region than a second portion of the plurality of macros [in FIG. 7 MG7 appears to be closer to the center than MG3].
3. The method of claim 2, wherein a plurality of weights of the first portion of the plurality of macros are greater than a plurality of weights of the second portion of the plurality of macros [in paragraphs 0027 and 0033, to place the selected placements of the groups MG in the layout area according to a specific rule and to optimize routability and satisfy timing constraints for the IC is interpreted to involve weights that result in the first portion and second portion according to constraints of/in the data flow control].
4. The method of claim 2, further comprising: forming a plurality of registers coupled to the plurality of macros [0033 and FIG. 7 a register is implemented using standard cells], wherein on the basis of correlations between the plurality of macros and the plurality of registers, a first register of the plurality of registers and a third portion of the plurality of macros are placed in a first region, and a second register of the plurality of registers and a fourth portion of the plurality of macros are placed in a second region different from the first region [such an arrangement is interpreted to be dependent upon data flow control being implemented, for example, in FIG. 7. SG1 and MG1 are placed in a first region and SG5 and MG6 are placed in a second region different].
5. The method of claim 1, wherein the plurality of channels extend in the first direction and are separated from each other in the second direction [CH1-CH4 in FIG. 10 and 0037].
7. The method of claim 1, wherein the first pin of the first macro and the second pin of the second macro are coupled to the first channel [this follows from above for routing; alternatively such coupling can be interpreted as a design choice].
As per claim 8, Hsu et al. teach a method, comprising:
forming a plurality of macros [0037 macro blocks MB] having a plurality of pins [0029 the pin locations of each macro block MB]; and
forming a plurality of channels [CH1-CH4 in FIG. 10 and 0037] that are between a plurality of group boxes [0033the processor can further consider channel widths between the groups MG] including the plurality of macros and extend in a first direction [0027 macro grouping, divide the macro blocks MB pf the IC into a plurality of groups MG, whole chip APR, 0029 the processor dynamically adjusts a plurality of channel widths between the macro blocks MB into each rectangle],
wherein the plurality of macros are aligned with a plurality of boundaries of the plurality of group boxes [0029 rectangle optimization procedure for each group MG, the processor places the macro blocks MB of the group MG into each rectangle, a candidate placement CP is determined if all macro blocks MB align for the group MG].
However, Hsu et al. do not explicitly teach wherein the plurality of pins align to the plurality of channels and are separated from each other in a second direction different from the first direction. Yet, routing with the pin locations of each macro block MB requires the pins align to channels and are separated from each other in a different direction for the function to be performed by the IC. Thus, the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains because cost of a place and route (APR) procedure can be decreased [0027], and it is easy to perform routing [0037].
9. The method of claim 8, wherein forming the plurality of macros comprises: when a number of the plurality of macros is an odd number [this is interpreted as a design choice], forming a first macro, of the plurality of macros, adjacent a first boundary of the plurality of boundaries, wherein an orientation of a pin of the first macro is arranged opposite of first boundary [0026 RTL describing the function performed, 0027 macro grouping procedure according to hierarchy information of the macro blocks, in other words macros are formed along logic boundaries such as a specific processor, a memory, and so on with the pins oriented accordingly].
10. The method of claim 8, further comprising: forming a plurality of standard cells adjacent to the plurality of macros [0033 and FIG. 7].
11. The method of claim 8, wherein portions in the plurality of pins are coupled a corresponding channel in the plurality of channels [this follows from above for routing; alternatively such coupling can be interpreted as a design choice for the macro grouping and function performed].
12. The method of claim 8, wherein forming the plurality of macros comprises: forming a first portion of the plurality of macros in a first row and forming a second portion of the plurality of macros in a second row, wherein a number of the first portion of the plurality of macros is different from a number of the second portion of the plurality of macros [in 0027 according to the hierarchy information, the macros depicted in FIGS. 8 or 10 appear to depict these features; alternatively such forming can be interpreted as a design choice considering ICs, macros, standard cells are known to be arranged in columns and rows].
13. The method of claim 8, wherein forming the plurality of macros comprises: forming a first portion of the plurality of macros in a first row and forming a second portion of the plurality of macros in a second row, wherein a number of macros, in the first row [in 0027 according to the hierarchy information, the macros depicted in FIGS. 8 or 10 appear to depict these features; alternatively such forming can be interpreted as a design choice considering ICs, macros, standard cells are known to be arranged in columns and rows], having the pins facing a first boundary of the plurality of boundaries is less than a number of macros, in the second row, having the pins facing the first boundary [0026 RTL describing the function performed, 0027 macro grouping procedure according to hierarchy information of the macro blocks, in other words macros are formed along logic boundaries such as a specific processor, a memory, and so on with the pins oriented accordingly].
14. The method of claim 13, wherein the number of macros, in the second row, having the pins facing the first boundary is different from a number of macros, in the second row, having pins facing a second boundary of the plurality of boundaries [this follows the above reasoning; alternatively such can be interpreted as a design choice considering ICs, macros, standard cells are known to be arranged and in columns and rows].
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over HSU et al. [US 2016/0335386 A1] in view of Xiao et al. [CN110377922A].
As per claim 6, Hsu et al. teach the features from which the claim depends. However, Hsu et al. do not teach buffers. Xiao et al. teach a method for solving that there is not enough space to insert a buffer, generating a layout constraint according to the layout space corresponding to the buffer combination, to reserve layout space corresponding to the buffer combination [Summary of the invention paragraphs 1 and 5; see, also, Clock Tree on page 3, Embodiment 1 at page 5 Step S302 through page 6]. Thus, by combining teachings a channel width is associated buffers, wherein a channel width of the first channel is associated with a number of plurality of buffers interposed in the first channel in order to form a channel between macros. Therefore, the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains because reserving layout space for buffers does not affect the placement of the original unit, and does not add too much to routing resources, has minimal impact on the design, and can significantly reduce the iteration cycle of the design [page 2, paragraph before DRAWINGS].
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,853,675.
Although the claims at issue are not identical, they are not patentably distinct from each other because the examined application claims would have been obvious over the reference claims. The present claims do not appear to recite patently distinct subject matter but rather a rehashing of the patented claims, claim language is merely reworded or rearranged. The following table provides a matching of claimed subject matter.
Present Claims
Patented Claims
1.A method, comprising:
1. A method, comprising:
forming a plurality of macros including a first macro and a second macros that extend in a first direction, wherein a first pin of the first macro and a second pin of the second macro are separated along a second direction different from the first direction,
arranging, in accordance with a plurality of weights of a plurality of macros, a first portion of the plurality of macros closer to a centroid of a core region of an integrated circuit than a second portion of the plurality of macros; and arranging the plurality of macros on opposite sides of the plurality of channels, wherein the plurality of macros have a plurality of pins coupled to the plurality of channels interposed between the plurality of macros
wherein the plurality of macros are formed around a logic boundary, and the second pin of the second macro is opposite of the logic boundary;
arranging, in accordance with a plurality of weights of a plurality of macros, a first portion of the plurality of macros closer to a centroid of a core region of an integrated circuit than a second portion of the plurality of macros,
wherein the plurality of macros have a plurality of pins coupled to the plurality of channels interposed between the plurality of macros.
forming a first channel of a plurality of channels, wherein the first channel is interposed between the first macro and the second macro and extend in the first direction.
arranging a plurality of channels extending in a first direction,
arranging the plurality of macros on opposite sides of the plurality of channels,
wherein the plurality of macros have a plurality of pins coupled to the plurality of channels interposed between the plurality of macros
2. The method of claim 1, wherein forming the plurality of macros comprises:
1. A method, comprising:
forming a first portion of the plurality of macros closer to a centroid of a core region than a second portion of the plurality of macros.
arranging, in accordance with a plurality of weights of a plurality of macros, a first portion of the plurality of macros closer to a centroid of a core region of an integrated circuit than a second portion of the plurality of macros
3. The method of claim 2, wherein a plurality of weights of the first portion of the plurality of macros are greater than a plurality of weights of the second portion of the plurality of macros.
2. The method of claim 1, wherein the plurality of weights of the first portion of the plurality of macros are greater than the plurality of weights of the second portion of the plurality of macros.
4. The method of claim 2, further comprising: forming a plurality of registers coupled to the plurality of macros,
3. The method of claim 1, further comprising: arranging a plurality of registers coupled to the plurality of macros
wherein on the basis of correlations between the plurality of macros and the plurality of registers, a first register of the plurality of registers and a third portion of the plurality of macros are placed in a first region, and a second register of the plurality of registers and a fourth portion of the plurality of macros are placed in a second region different from the first region.
wherein on the basis of correlations between the plurality of macros and the plurality of registers, a first register of the plurality of registers and a third portion of the plurality of macros are placed in a first region, and a second register of the plurality of registers and a fourth portion of the plurality of macros are placed in a second region different from the first region.
5. The method of claim 1, wherein the plurality of channels extend in the first direction and are separated from each other in the second direction.
1. arranging a plurality of channels extending in a first direction
arranging a plurality of channels extending in a first direction
6. The method of claim 1, wherein a channel width of the first channel is associated with a number of plurality of buffers interposed in the first channel.
4. wherein each of the plurality of channels has a channel width, and the channel width is associated with a shortest channel path between one of the plurality of standard cells and one of the plurality of macros
7. The method of claim 1, wherein the first pin of the first macro and the second pin of the second macro are coupled to the first channel.
1. wherein the plurality of macros have a plurality of pins coupled to the plurality of channels interposed between the plurality of macros.
8. A method, comprising:
5. A method, comprising:
forming a plurality of macros having a plurality of pins;
forming a plurality of macros having a plurality of pins that face to each other
forming a plurality of channels that are between a plurality of group boxes including the plurality of macros and extend in a first direction, wherein the plurality of pins align to the plurality of channels and are separated from each other in a second direction different from the first direction,
forming a plurality of channels that are between a plurality of group boxes including the plurality of macros and extend in a first direction,
a plurality of macros having a plurality of pins that face to each other;
a plurality of channels that are between a plurality of group boxes including the plurality of macros and extend in a first direction, wherein the plurality of macros are aligned with a plurality of boundaries of the plurality of group boxes
wherein the plurality of macros are aligned with a plurality of boundaries of the plurality of group boxes.
wherein the plurality of macros are aligned with a plurality of boundaries of the plurality of group boxes
9. The method of claim 8, wherein forming the plurality of macros comprises:
6. The method of claim 5, wherein forming the plurality of macros comprises:
when a number of the plurality of macros is an odd number, forming a first macro, of the plurality of macros, adjacent a first boundary of the plurality of boundaries, wherein an orientation of a pin of the first macro is arranged opposite of first boundary.
when a number of the plurality of macros is an odd number, forming a first macro, of the plurality of macros, adjacent a first boundary of the plurality of boundaries, wherein an orientation of a pin of the first macro is arranged opposite of first boundary.
10. The method of claim 8, further comprising: forming a plurality of standard cells adjacent to the plurality of macros.
7. The method of claim 5, further comprising: forming a plurality of standard cells adjacent to the plurality of macros.
11. The method of claim 8, wherein portions in the plurality of pins are coupled a corresponding channel in the plurality of channels.
8. The method of claim 5, wherein a weight of the plurality of weights corresponding to one of the plurality of macros is associated with a number of a plurality of fan-in points and a number of a plurality of fan-out points that are of the one of the plurality of macros.
12. The method of claim 8, wherein forming the plurality of macros comprises:
forming a first portion of the plurality of macros in a first row and forming a second portion of the plurality of macros in a second row,
wherein a number of the first portion of the plurality of macros is different from a number of the second portion of the plurality of macros.
7. The method of claim 5, further comprising: forming a plurality of standard cells adjacent to the plurality of macros.
8. The method of claim 5, wherein a weight of the plurality of weights corresponding to one of the plurality of macros is associated with a number of a plurality of fan-in points and a number of a plurality of fan-out points that are of the one of the plurality of macros.
10. The method of claim 5, wherein forming the plurality of macros comprises: placing a centroid of the second portion of the plurality of macros a distance away from a closest boundary in the plurality of boundaries, wherein the distance is greater than about 50 micrometers.
11. The method of claim 10, wherein each macro of the second portion of the plurality of macros is at a spacing from the first portion of the plurality of macros, wherein the spacing is greater than about 2 micrometers.
13. The method of claim 8, wherein forming the plurality of macros comprises: forming a first portion of the plurality of macros in a first row and forming a second portion of the plurality of macros in a second row, wherein a number of macros, in the first row, having the pins facing a first boundary of the plurality of boundaries is less than a number of macros, in the second row, having the pins facing the first boundary.
7. The method of claim 5, further comprising: forming a plurality of standard cells adjacent to the plurality of macros.
9. The method of claim 5, wherein a weight of the plurality of weights corresponding to one of the plurality of macros is associated with a number of stages between the one of the plurality of macros and a register coupled thereto.
8. The method of claim 5, wherein a weight of the plurality of weights corresponding to one of the plurality of macros is associated with a number of a plurality of fan-in points and a number of a plurality of fan-out points that are of the one of the plurality of macros.
9. The method of claim 5, wherein a weight of the plurality of weights corresponding to one of the plurality of macros is associated with a number of stages between the one of the plurality of macros and a register coupled thereto.
10. The method of claim 5, wherein forming the plurality of macros comprises: placing a centroid of the second portion of the plurality of macros a distance away from a closest boundary in the plurality of boundaries, wherein the distance is greater than about 50 micrometers.
11. The method of claim 10, wherein each macro of the second portion of the plurality of macros is at a spacing from the first portion of the plurality of macros, wherein the spacing is greater than about 2 micrometers.
14. The method of claim 13, wherein the number of macros, in the second row, having the pins facing the first boundary is different from a number of macros, in the second row, having pins facing a second boundary of the plurality of boundaries.
7. The method of claim 5, further comprising: forming a plurality of standard cells adjacent to the plurality of macros.
9. The method of claim 5, wherein a weight of the plurality of weights corresponding to one of the plurality of macros is associated with a number of stages between the one of the plurality of macros and a register coupled thereto.
8. The method of claim 5, wherein a weight of the plurality of weights corresponding to one of the plurality of macros is associated with a number of a plurality of fan-in points and a number of a plurality of fan-out points that are of the one of the plurality of macros.
9. The method of claim 5, wherein a weight of the plurality of weights corresponding to one of the plurality of macros is associated with a number of stages between the one of the plurality of macros and a register coupled thereto.
15. A system comprising:
12. A system comprising:
one or more processing units;
one or more processing units;
a memory unit configured to store instructions that when executed by at least one of the one or more processing units perform operations, comprising:
a memory unit configured to store instructions that when executed by at least one of the one or more processing units perform operations, comprising
determine whether a first width of a first channel between a plurality of macros is wide enough for routing;
check a predicted routing result based on a first width of a first channel between a plurality of macros in an integrated circuit,
separate the plurality of macros based on a largest width of the channel widths of the plurality of channels
separate the plurality of macros by a corresponding one in predicted channel widths, wherein each of the predicted channel widths is associated with a height of the first channel and a total area of buffers adjacent to a corresponding one in the plurality of macros;
14. adjust a first portion of the plurality of macros in a first region closer to a first register of the plurality of registers, wherein the first register is coupled to the first portion of the macros.
15. adjust a second portion of the plurality of macros in a second region that is different from the first region and closer to a second register of the plurality of registers, wherein the second register is coupled to the second portion of the macros.
19. The system of claim 12, wherein the operations of predicting the channel widths further comprise: estimate a number of a plurality of buffers according to a predicted channel path for each of the plurality of macros, wherein the predicted channel path is between one of a plurality of standard cells and a corresponding one of the plurality of macros; and on the basis of the number of the plurality of buffers and an area of each of the plurality of buffers, calculate the channel width for the corresponding one of the plurality of macros.
13. The system of claim 12, wherein the operations further comprise: arrange a plurality of standard cells adjacent to the plurality of macros
arrange the plurality of macros based on a largest width of the predicted channel widths.
detect correlations between the plurality of macros and a plurality of registers; and adjust the plurality of macros according to the correlations.
18. The system of claim 17, wherein the weights of the first portion of the plurality of macros are greater than the weights of the second portion of the plurality of macros.
14. adjust a first portion of the plurality of macros in a first region closer to a first register of the plurality of registers, wherein the first register is coupled to the first portion of the macros.
15. adjust a second portion of the plurality of macros in a second region that is different from the first region and closer to a second register of the plurality of registers, wherein the second register is coupled to the second portion of the macros.
16. The system of claim 15, wherein the buffers include driver circuits configured to drive the plurality of macros.
19. The system of claim 12, wherein the operations of predicting the channel widths further comprise: estimate a number of a plurality of buffers according to a predicted channel path for each of the plurality of macros, wherein the predicted channel path is between one of a plurality of standard cells and a corresponding one of the plurality of macros; and on the basis of the number of the plurality of buffers and an area of each of the plurality of buffers, calculate the channel width for the corresponding one of the plurality of macros.
17. The system of claim 15, wherein the operations further comprise:
13. The system of claim 12, wherein the operations further comprise:
arrange a plurality of standard cells adjacent to the plurality of macros,
arrange a plurality of standard cells adjacent to the plurality of macros
wherein each of the predicted channel widths is associated with a shortest channel path between one of the plurality of standard cells and one of the plurality of macros.
16. The system of claim 12, wherein the operations further comprise: place a first portion of the plurality of macros closer to a centroid of a core region in a floor plan than a second portion of the plurality of macros according to a number of a plurality of fan-in points, a number of a plurality of fan-out points, and a number of stages between the one of the plurality of macros and the plurality of registers coupled thereto.
17. The system of claim 12, wherein the operations further comprise: place, according to a weight of each one in the plurality of macros, a first portion of the plurality of macros closer to a centroid of a core region in a floor plan than a second portion of the plurality of macros,
20. The system of claim 19, wherein the predicted channel path has a shortest distance between a start point on the corresponding one of the plurality of macros and a corresponding end point on the plurality of standard cells.
18. The system of claim 15, wherein the operations of separating the plurality of macros further comprise: estimate a number of the buffers according to a predicted channel path for each of the plurality of macros; on the basis of the number of the buffers and an area of each of the buffers, calculate the total area of the buffers.
19. The system of claim 12, wherein the operations of predicting the channel widths further comprise: estimate a number of a plurality of buffers according to a predicted channel path for each of the plurality of macros, wherein the predicted channel path is between one of a plurality of standard cells and a corresponding one of the plurality of macros; and on the basis of the number of the plurality of buffers and an area of each of the plurality of buffers, calculate the channel width for the corresponding one of the plurality of macros.
19. The system of claim 18, wherein the predicted channel path is between one of a plurality of standard cells and the corresponding one of the plurality of macros.
13. The system of claim 12, wherein the operations further comprise: arrange a plurality of standard cells adjacent to the plurality of macros, wherein each of the channel width is associated with a shortest channel path between one of the plurality of standard cells and one of the plurality of macros.
20. The system of claim 19, wherein the predicted channel path has a shortest distance between a start point on the corresponding one of the plurality of macros and a corresponding end point on the plurality of standard cells.
20. The system of claim 19, wherein the predicted channel path has a shortest distance between a start point on the corresponding one of the plurality of macros and a corresponding end point on the plurality of standard cells.
Taking present claim 1 as exemplary, an obvious change is reciting forming as opposed to the patented arranging, yet both methods provide for macros extending in a first direction, wherein pins are separated along a different direction; the logic boundary is interpreted as definitive of a macro, with channels between the macros. Regarding claim 6 it is interpreted that buffers are inherent to channels for connecting macros. Regarding claim 8, the matching above appears self-explanatory. Regarding claims 11-13, the portions are interpreted to relate to fan-in, fan-out, and stages for which weights correspond to result in the claimed features. Regarding claims 12-14, rows are known to standard cell design, thus, the matched features are interpreted to narrowly describe the broader subject matter. Regarding claim 15, the language is broadly rearranged yet results in a system that arranges the plurality of macros by adjusting according tot eh correlations in terms of predicted channel width associated with height and total buffer area as matched above. The remaining claims similarly follow, with claims 16-20 interpreted as very broadly reciting the subject matter of the matched claims, particularly patented claim 17 which very narrowly recites an equation that is broadly interpreted for use in placing macros as the invention entails. Thus, although the claims at issue are not identical, they are not patentably distinct from each other because the examined application claims would have been obvious over the reference claims as cited above. The present claims do not appear to recite patently distinct subject matter but rather a rehashing of the patented claims, claim language is merely reworded or rearranged. Therefore, the claims are rejected on the ground of nonstatutory double patenting.
Conclusion
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/LEIGH M GARBOWSKI/ Primary Examiner, Art Unit 2851
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