DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A, Claims 1-11 in the reply filed on 03/02/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/30/2025, 09/08/2025, 11/06/2024, and 12/01/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 11 are rejected under 35 U.S.C. 102 as being anticipated by Leipold et al. ( US 2018/0114801 A1; hereinafter Leipold )
Regarding claim 1, Leipold teaches a structure ( Fig. 3 RF switch 10 ) comprising: a semiconductor layer ( Fig. 3 elongated D/S diffusion regions 14, elongated gate structures 20, elongated source diffusion region 34, elongated drain diffusion region 40 ) including a switch area having a first portion ( Fig. 3 silicide region 26 ) and a second portion ( Fig. 3 second non-silicide region 52 ) adjacent to the first portion ( Fig. 3 #26 ); and a switch including series-connected transistors ( Fig. 3 D/S #14 and gate regions #20 ), wherein the series-connected transistors include: within the first portion ( Fig. 3 #26 ), source/drain regions ( Fig. 3 plurality of elongated D/S resistor regions 18 and 14 ) and channel regions ( Fig. 3 elongated channel regions 16; [0028] Each of the plurality of elongated gate structures 20 resides over corresponding ones of the plurality of elongated channel regions 16 ) positioned laterally between the source/drain regions; and gates ( Fig. 3 elongated gate structures 20 ) adjacent to the channel regions ( Fig. 3 #16 ), respectively, wherein the gates ( Fig. 3 #20 ) traverse the first portion ( Fig. 3 #24 ) and wherein the second portion ( Fig. 3 #28 or #50 ) extends beyond the gates ( Fig. 3 #20 ).
Regarding claim 2, Leipold teaches the structure of claim 1 ( as discussed above ), wherein the switch further includes resistive elements ( Fig. 3 body resistor regions 54 ) in the second portion ( Fig. 3 #52 ) connected in parallel with the series-connected transistors ( as shown in Fig. 3 ).
Regarding claim 3, Leipold teaches the structure of claim 1 ( as discussed above ), wherein the series-connected transistors further include raised source/drain regions ( Fig. 4 source contacts 36 and drain contacts 42 ) on the source/drain regions ( Fig. 4 source diffusion region 34 and drain diffusion region 40 ).
Regarding claim 11, Leipold teaches the structure of claim 1 ( as discussed above ), further comprising: a semiconductor substrate ( Fig. 4: substrate 12 ) ; a well region ( [0032] an active device layer 48 that includes the plurality of elongated D/S diffusion regions 14 and the plurality of elongated D/S resistor regions 18. As such, the plurality of elongated D/S diffusion regions 14 and the plurality of elongated D/S resistor regions 18 reside within a common plane. Moreover, the plurality of elongated D/S resistor regions 18 forms active well resistors ) in the semiconductor substrate ( Fig. 4 #12 ); an insulator layer ( Fig. 4: buried oxide layer 46 ) on the semiconductor substrate ( Fig. 4 #12 ), wherein the semiconductor layer ( Fig. 4 #48 ) is on the insulator layer ( Fig. 4 #46 ); and trench isolation regions ( Fig. 4 #14 ) extending through the semiconductor layer ( Fig. 4 #48 ) to define, above the well region ( Fig. 4 #24 ), boundaries of the switch area ( Fig. 4 #10 ).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-7 and 9 are rejected under U.S.C. 103 as being unpatentable over Leipold et al.; US 2018/0114801 A1; 10/2017 in view of Cho et al.; US 12,604,719 B2; 12/2022
Claim 4: Leipold discloses the structure of claim 3 ( as discussed above ), wherein the switch area includes a first end ( Fig 4 left end of substrate ) and a second end ( Fig. 4 right end of substrate ) opposite the first end ( as shown in Fig. 4 ), wherein the source/drain regions ( Fig. 4 #34 and #40 ) include outer source/drain regions at the first end ( Fig. 4 #34 ) and at the second end ( Fig. 4 #40 ) and at least one inner source/drain region, wherein the raised source/drain regions ( Fig. 4 #36 and #42 ) include outer raised source/drain regions ( Fig. 4 #36 and #42 ) on the outer source/drain regions ( Fig. 4 #34 and #40 )
Leipold does not appear to disclose an inner raised source/drain region on each inner source/drain region, and wherein the switch further includes silicide layers above and immediately adjacent to the outer raised source/drain regions only of the raised source/drain regions.
However, Cho teaches an inner raised source/drain region ( Fig. 2 source/drain regions 110 ) on each inner source/drain region ( Fig. 2 ACT 1 ), and wherein the switch further includes silicide layers ( Col. 6 lines 25 – 27 The contact structure 160 may further include a metal silicide layer disposed between the conductive barrier 162 and the source/drain regions 110 ) above and immediately adjacent to ( as shown in Fig. 2 ) the outer raised source/drain regions only of the raised source/drain regions ( Fig. 2 #110 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Cho with Leipold to implement an inner raised source/drain region on each inner source/drain region, and wherein the switch further includes silicide layers above and immediately adjacent to the outer raised source/drain regions only of the raised source/drain regions because this approach can optimize performance by improving switching speed, reducing parasitic resistance, and controlling short-channel effects while minimizing parasitic capacitance.
Claim 5: Leipold and Cho disclose the structure of claim 4 ( as discussed above ).
Leipold teaches the gates have main sections ( Fig. 4 #20 ) positioned laterally between the raised source/drain regions ( Fig. 4 #36 and #42 ) and end sections extending from the main sections ( Fig. 4 gate dielectric layer 22 ), respectively, beyond the raised source/drain regions ( Fig. 4 #36 and #42 ) toward the second portion, wherein the end sections include a first polysilicon gate conductor layer ( [0028] the plurality of elongated gate structures 20 is made of polysilicon, and the gate dielectric layer 22 is made of silicon dioxide ) and the main sections ( Fig. 4 #20 ) include the first polysilicon gate conductor layer ( Fig. 4 #22 ) and a second polysilicon gate conductor layer ( Fig. 4 silicide layer 24 ) on the first polysilicon gate conductor layer ( Fig. 4 #22 ), and wherein the end sections have a first height ( Fig. 4 top of #22 ) and the main sections have a second height that is greater than the first height ( Fig. 4 #20 is higher than #22 ).
Claim 6: Leipold and Cho disclose the structure of claim 5 ( as discussed above ), further comprising: a first dielectric layer ( Fig. 3: a plurality of STI regions 56 which is a dielectric layer ) above and immediately adjacent the second portion ( Fig. 3 #52 ), extending onto a transition area ( Fig. 3 body diffusion regions 50 ) of the first portion ( Fig. 3 #26 ) immediately adjacent to the second portion ( Fig. 3 #52 ), and further extending over the first polysilicon gate conductor layer ( Fig. 3 #20 ) of the end sections of the gates ( as shown in Fig. 3 );
Leipold does not appear to disclose a second dielectric layer, wherein the second dielectric layer is above each inner raised source/drain region over each inner source/drain region and further above and immediately adjacent to the second polysilicon gate conductor layer of the main sections of the gates.
However, Cho teaches a second dielectric layer ( Fig. 2: a second dielectric layer 271 ), wherein the second dielectric layer ( Fig. 2 #271 ) is above each inner raised source/drain region ( Fig. 2 ACT2 ) over each inner source/drain region ( Fig. 2: source/drain region 110 ) and further above and immediately adjacent to the second polysilicon gate conductor layer ( Fig. 2: gate electrode 145 ) of the main sections of the gates ( Fig. 2 gate structure GS ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Cho with Leipold to implement a second dielectric layer, wherein the second dielectric layer is above each inner raised source/drain region over each inner source/drain region and further above and immediately adjacent to the second polysilicon gate conductor layer of the main sections of the gates because this allows for isolation, reduction of parasitic capacitance, and the enablement of self-aligned structures.
Claim 7: Leipold and Cho disclose the structure of claim 6 ( as discussed above ).
Leipold does not appear to disclose the second dielectric layer extends laterally over outer gates of the gates and onto the outer raised source/drain regions.
However, Cho teaches the second dielectric layer ( Fig. 2 #271 ) extends laterally over outer gates of the gates ( Fig. 2: gate structure GS ) and onto the outer raised source/drain regions ( Fig. 2 ACT2 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Cho with Leipold to implement the second dielectric layer extends laterally over outer gates of the gates and onto the outer raised source/drain regions because this approach can reduce parasitic capacitance, suppress leakage currents, and protect the transistor structure during fabrication.
Claim 9: Leipold and Cho disclose the structure of claim 6 ( as discussed above ).
Leipold does not appear to disclose the second dielectric layer extends laterally partially over outer gates of the gates.
However, Cho teaches the second dielectric layer ( Fig. 7 #271 ) extends laterally partially over ( as shown in Fig. 7 #271 is not continuous over the GS region ) outer gates of the gates ( Fig. 7: GS ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Cho with Leipold to implement the second dielectric layer extends laterally partially over outer gates of the gates because this approach would engineer the electric field distribution, reduce parasitic capacitance, and ensure reliable electrical isolation between closely spaced electrodes.
Claim 8 and 10 are rejected under U.S.C. 103 as being unpatentable over Leipold et al.; US 2018/0114801 A1; 10/2017 in view of Cho et al.; US 12,604,719 B2; 12/2022 as it relates to claim 6 above and further in view of Wang et al.; US 12,369,388 B2; 07/2022
Claim 8: Leipold and Cho disclose the structure of claim 6 ( as discussed above ).
Leipold does not appear to disclose the second dielectric layer extends laterally over outer gates of the gates without extending further onto the outer raised source/drain regions.
However, Wang teaches the second dielectric layer ( Fig. 1C: second dielectric spacer layer 128 ) extends laterally over outer gates of the gates ( Fig. 1B: gate structures 112 ) without extending further ( as shown in Fig. 1B ) onto the outer raised source/drain regions ( Fig. 1B: epitaxial fin regions 110 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Wang with Leipold and Cho to implement the second dielectric layer extends laterally over outer gates of the gates without extending further onto the outer raised source/drain regions because this approach optimizes device performance by reducing parasitic capacitance while maintaining field modulation.
Claim 10: Leipold discloses the structure of claim 1 ( as discussed above ).
Leipold does not appear to disclose the series-connected transistors are N-channel field effect transistors, wherein the source/drain regions have N-type conductivity, and wherein the second portion has the N-type conductivity at a lower conductivity level than the source/drain regions.
Cho discloses the series-connected transistors are N-channel field effect transistors ( Col. 11 lines 28 – 37 the semiconductor device according to the present example embodiment may be implemented as a semiconductor device including a vertical FET (VFET) having an active region extending perpendicularly to the upper surface of the first semiconductor substrate 101 ), wherein the source/drain regions have N-type conductivity ( Col. 4 lines 11 – 13 For example, the source/drain region 110 may be formed of Si, SiGe, or Ge, and may have either an N-type or a P-type conductivity type ),
Cho does not appear to disclose the second portion has the N-type conductivity at a lower conductivity level than the source/drain regions.
However, Wang teaches the second portion ( Fig. 2A sub-regions 224A – 224C ) another has the N-type conductivity at a lower conductivity level than the source/drain regions ( Col. 12 lines 39 - 47 Sub-regions 224A-224C can have varying dopant concentrations with respect to each other, according to some embodiments. For example, sub-region 224A (e.g., closest to base region 120) can be undoped or can have a dopant concentration (e.g., dopant concentration less than about 8×10.sup.20 atoms/cm.sup.3) less than that (e.g., dopant concentration ranging from about 8×10.sup.20 to about 3×10.sup.22 atoms/cm.sup.3) of sub-regions 224B and 224C (e.g., farthest from base region 120)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Wang with Leipold and Cho to implement the second portion has the N-type conductivity at a lower conductivity level than the source/drain regions because this addresses high electric field effects, improves reliability, and increased the breakdown voltage.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIMBERLY N FREY whose telephone number is (571)272-5068. The examiner can normally be reached Monday - Friday 7:30 am - 5 pm.
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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