DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I, claims 1-19 in the reply filed on 8 June 2026 is acknowledged. The traversal is on the grounds that Group I is sufficiently related to the method of making the device of claim 20 of Group II along with the claims of Group I. This is not found persuasive because the product as claimed in claims 1-19 of Group I can be made by another and materially different process as outlined in the restriction requirement Specifically, the product as described in claim 1 can be made by a process that comprises forming a guard structure comprised of polycrystalline semiconductor materials and not the discontinuous pairs of N+ and P+ diffusions as required by the method of claim 20 and the product as described in claim 11 can be made by a process that forms the first and second discontinuous pairs substantially aligned to one another and not staggered as required by the method of claim 20. Furthermore, the groups listed are independent or distinct and there would be a serious search and/or examination burden if restriction were not required because the groupings require different classification searches in at least CPC H10W 10/30 (Group I) and CPC H10W 10/031 (Group II).
The requirement between Group I and Group II is still deemed proper and is therefore made FINAL.
Claim 20 is withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Group (II), there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 8 June 2026.
Applicant’s election of Species B in the telephone interview conducted with Keith Taboada on 17 August 2026 is acknowledged. Because Applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Applicant's election with traverse of Species C1 in the telephone interview conducted with Keith Taboada on 17 August 2026 is acknowledged. The traversal is on the grounds that there is no undue burden when searching between Species C1, C2 and C3 and that upon searching for one of the guard ring structures as outlined in the restriction requirement, the Examiner would find the ring structures as described in each of the Species C1, C2 and C3. The Examiner notices that upon conducting a search for Species C1, the Examiner was able to find prior art related to Species C2 and Species C3 and has therefore withdrawn the restriction requirement with respect to Species C1, C2 and C3.
The restriction requirement between Species C1, C2 and C3 has been withdrawn.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1 December 2023 has been considered by the examiner and made of record in the application file.
Claim Objections
Claim 19 is objected to because of the following informalities:
Claim 19 recites “first and second guard structures separated by a plurality of grounded vias, the first and second guard structures separated by a plurality of grounded vias” wherein the Examiner believes there is an antecedent basis error and claim 19 is interpreted by the Examiner to recite “first and second guard structures separated by a plurality of grounded vias, the first and second guard structures separated by the plurality of grounded vias”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 11, the claim recites in lines 9-10, “a first group of discontinuous pairs of N+ and P+ wells disposed along a first column” and further recites in lines 12-13, “a second group of discontinuous pairs of N+ and P+ wells disposed along a first column” wherein lines 12-13 appear to redefine a first column and it is unclear to one of ordinary skill in the art how a first group of discontinuous pairs of N+ and P+ wells of a first guard structure may be disposed along a same first column as a second group of discontinuous pairs of N+ and P+ wells of a second guard structure. For the purpose of Examination, the Examiner has interpreted lines 9-10 as “a first group of discontinuous pairs of N+ and P+ wells disposed along a first column of a first guard structure” and lines 12-13 as “a second group of discontinuous pairs of N+ and P+ wells disposed along a first column of a second guard structure”. Claims 12-19 are rejected due to their dependence on claim 11.
Claims 12-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 12, the claim recites in lines 3-4, “disposed along a second column that runs adjacent the first column” wherein it is unclear to one of ordinary skill in the art if “the first column” is the first column as described with respect to the first guard structure in claim 11 or the first column as described with respect to the second guard structure in claim 11. For the purpose of Examination, the Examiner has interpreted lines 3-4 as “disposed along a second column that runs adjacent the first column of the first guard structure”. Claims 13-15 are rejected due to their dependence on claim 12.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Chih-Hung Lu et al. (US 2013/0154048 A1; hereinafter “Lu”).
Regarding Claim 1, Lu teaches an electronic device, comprising:
a first circuit (FC, annotated Fig. 6, para [0013] describes electrically circuity 112 and annotated Fig. 6 depicts a first circuit FC of the electrical circuity 112) and a second circuit (SC, annotated Fig. 6, para [0013] describes electrically circuity 112 and annotated Fig. 6 depicts a second circuit SC of the electrical circuity 112) formed on a substrate (110, Fig. 6, para [0013] describes a substrate 110 upon which the first circuit FC and second circuit SC are formed on);
a first guard structure formed in the substrate and disposed between the first circuit and the second circuit (118, annotated Fig. 6, para [0016] describes guard wells 118 formed in the substrate 110 and disposed between the first circuit FC and second circuit SC); and
a plurality of vias formed through the substrate adjacent the first guard structure (330, Fig. 6, para [0020] describes a plurality of through vias 330 formed through the substrate 110 and adjacent to the first guard structures 118), the plurality of vias disposed between the first circuit and the second circuit (330, annotated Fig. 6 depicts the plurality of vias 330 disposed between the first circuit FC and second circuit SC).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-18 are rejected under 35 U.S.C. 103 as being unpatentable over Jing Jing et al. (US 2018/0083096 A1; hereinafter “Jing”) in view of Chia-Chung Chen et al. (US 2015/0104925 A1; hereinafter “Chen”).
Regarding Claim 1, Jing teaches an electronic device, comprising:
a first circuit (102, Fig. 1, para [0020] describes a noise source circuit 102) and a second circuit formed (104, Fig. 1, para [0020] describes a noise receiving circuit 104) on a substrate (101, Fig. 1, para [0020] describes a semiconductor substrate 101 upon which the first circuit 102 and second circuit 104 are formed);
a first guard structure formed in the substrate (106, Fig. 1, para [0022] describes a first guard structure 106 formed in the substrate 101) and disposed between the first circuit and the second circuit (106, Fig. 1, para [0023] describes wherein the first guard structure 106 is disposed between the first circuit 102 and second circuit 104).
Jing fails to explicitly disclose a plurality of vias formed through the substrate adjacent the first guard structure, the plurality of vias disposed between the first circuit and the second circuit.
However, Chen teaches a similar electronic device comprising a plurality of vias formed through the substrate (50, Fig. 1A, para [0009] describes a plurality of through substrate vias 50 formed through substrate 20) adjacent the first guard structure (26, Fig. 1A, para [0009] describes a guard ring 26 formed adjacent to the though substrate vias 50), the plurality of vias disposed between the first circuit and the second circuit (50 and 24, Fig. 1A and Fig. 1C, para [0009] describes the plurality of vias 50 are disposed surrounding a first circuit 24 and Fig. 1C depicts a first circuit 24 and a second circuit 24 on an opposite side of the through substrate vias 50 and further wherein upon combining Jing with Chen the plurality of vias of Chen, between the first guard structure 26 and a second guard structure 48, would be between the first circuit 102 and second circuit of Jing and are disposed in a location such as the another guard structure 602 of Jing disposed between the first guard structures 106-1 and a second guard structure 106-2 of Jing).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Jing with Chen to further disclose an electronic device comprising a plurality of vias formed through a substrate adjacent a first guard structure, the plurality of vias disposed between a first circuit and a second circuit in order to provide the advantage of providing grounded through substrate vias that may collect electrons leaked from devices preventing signal coupling and achieving a better signal isolation (Chen, para [0020]).
Regarding Claim 2, the combination of Jing and Chen teaches the electronic device of claim 1, wherein the first guard structure comprises:
a first group of discontinuous pairs of N+ and P+ wells disposed along a first column (Jing, 108-1, 202 and 204, Fig. 1, Fig. 2B and Fig. 4, para [0025] describes wherein the first guard structure 106 comprises a first group 108-1 of discontinuous N+ diffusion regions 202 and P+ diffusion regions 204 forming N-wells and P-wells as described in para [0029] and disposed along a first column 106-1).
Regarding Claim 3, the combination of Jing and Chen teaches the electronic device of claim 2, wherein the first guard structure comprises:
a second group of discontinuous pairs of N+ and P+ wells disposed along a second column that runs adjacent the first column (Jing, 108-2, 202 and 204, Fig. 1, Fig. 2B and Fig. 4, para [0025] describes wherein the first guard structure 106 comprises a second group 108-2 of discontinuous N+ diffusion regions 202 and P+ diffusion regions 204 forming N-wells and P-wells as described in para [0029] and disposed along a second column 106-2 adjacent to the first column).
Regarding Claim 4, the combination of Jing and Chen teaches the electronic device of claim 3, wherein the pairs of N+ and P+ wells comprising the first column are staggered relative to the pairs of N+ and P+ wells comprising the second column (Jing, 106-1 and 106-2, Fig. 1, para [0023] describes wherein the pairs of N+ and P+ wells 108-1 comprising the first column 106-1 are staggered relative to the pairs of N+ and P+ wells 108-2 comprising the second column 108-2).
Regarding Claim 5, the combination of Jing and Chen teaches the electronic device of claim 4, wherein at least one of the pairs of N+ and P+ wells comprising the first column (Jing, FP and 106-1, annotated Fig. 3C depicts wherein at least one pair FP of the pairs of N+ and P+ wells comprising the first column 106-1) is overlapped with at least one of the pairs of N+ and P+ wells comprising the second column in a direction perpendicular to a direction of the first column (Jing, SP and 106-2, annotated Fig. 3C depicts wherein at least one pair SP of the pairs of N+ and P+ wells comprising the second column 106-2 overlaps with a pair FP of the pairs of N+ and P+ wells comprising the first column 106-1 in an X direction perpendicular to a Y direction of the first column 106-1).
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Regarding Claim 6, the combination of Jing and Chen teaches the electronic device of claim 4, wherein a first pair of the pairs of N+ and P+ wells comprising the first column (Jing, FP and 106-1, annotated Fig. 3C depicts wherein a first pair FP of the pairs of N+ and P+ wells comprising the first column 106-1) is overlapped with two of the pairs of N+ and P+ wells comprising the second column in a direction perpendicular to a direction of the first column (Jing, SP and TP and 106-2, annotated Fig. 3C depicts two pairs SP and TP of the pairs of N+ and P+ wells comprising the second column 106-2 overlapping with a first pair FP of N+ and P+ wells comprising the first column 106-1 in an X direction perpendicular to a Y direction of the first column 106-1).
Regarding Claim 7, the combination of Jing and Chen teaches the electronic device of claim 1, wherein the plurality of vias formed through the substrate comprises:
a first column of vias formed in an un-doped region of the substrate (Chen, Fig. 1B, para [0009] describes wherein a first column of vias 50 on a left side of integrated circuit device 24 may be formed in a bulk substrate 20 that may be comprised of silicon).
Regarding Claim 8, the combination of Jing and Chen teaches the electronic device of claim 1, wherein the plurality of vias formed through the substrate comprises:
a plurality of via columns formed through the substrate between the first and second circuits (Chen, 50 and 24, Fig. 1A and Fig. 1C, para [0009] describes the plurality of through substrate vias 50 are disposed surrounding a first circuit 24 including a plurality of via columns as shown in Fig. 1A and Fig. 1C depicts a first circuit 24 and a second circuit 24 on an opposite side of the through substrate vias 50 comprising a plurality of columns and further wherein upon combining Jing with Chen the plurality of vias of Chen, between the first guard structure 26 and a second guard structure 48, would be between the first circuit 102 and second circuit of Jing and are disposed in a location such as the another guard structure 602 of Jing disposed between the first guard structures 106-1 and a second guard structure 106-2 of Jing).
Regarding Claim 9, the combination of Jing and Chen teaches the electronic device of claim 1 further comprising:
a second guard structure (Jing, Fig. 5, para [0030] describes a further embodiment of Fig. 1 wherein a second guard structure 506-2 may be disposed in a guard ring structure surrounding a first guard structure 506-1 and Chen para [0011] describes a second guard ring 48) circumscribing both the plurality of vias and the first guard structure (Jing, para [0032] describes wherein the guard rings 506 of Fig. 5 can be separated by a guard structure 602 wherein upon combining Jing with Chen, the plurality of vias may replace the guard structure 602 to provide a through via grounding guard structure resulting in a second guard structure 506-2 circumscribing both the plurality of vias 214 of Chen and the first guard structure 506-1 of Jing and further wherein Chen teaches in para [0011] the second guard structure 48 may encircle the first guard structure 26 and the plurality of vias 50 as shown in Fig. 1B).
Regarding Claim 10, the combination of Jing and Chen teaches the electronic device of claim 1 further comprising:
a front end of the line (FEOL) region formed on the substrate and containing a least a portion of the first circuit and the second circuit (Jing, 102 and 104, Fig. 1, para [0020] describes a first circuit 102 and second circuit 104 and metal layers that interconnect the transistors to form the first circuit 102 and second circuit 104 formed on the first substrate 101 wherein the first circuit 102, second circuit 104 and their respective interconnect structures would form an FEOL region and Chen further depicts in Fig. 1C wherein a first integrated circuit 24 and a second integrated circuit 24 are formed on a front surface of substrate 20 at a front end of the line (FEOL) region at an ILD layer);
a back end of the line (BEOL) region formed on the FEOL region (Chen, M1, M2, M3 and M4, Fig. 1C, para [0015] describes an interconnect structure formed on the FEOL region comprising metallization layers M1, M2, M3 and M4); and
a via stack formed through the FEOL and BEOL regions, the via stack electrically connected to one of the plurality of vias formed through the substrate (Chen, 52 and 54, Fig. 1C, para [0015] describes a via stack comprising metal lines 54 and vias 52 formed through the FEOL and BEOL regions wherein the via stack is electrically connected at least one of the plurality of vias 50 formed through the substrate 20).
Regarding Claim 11, Jing teaches an electronic device, comprising:
a first substrate (101, Fig. 1, para [0020] describes a semiconductor substrate 101);
a front end of the line (FEOL) region formed on the first substrate and containing a least a portion of a first circuit and a second circuit (102 and 104, Fig. 1, para [0020] describes a first circuit 102 and second circuit 104 and metal layers that interconnect the transistors to form the first circuit 102 and second circuit 104 formed on the first substrate 101 wherein the first circuit 102, second circuit 104 and their respective interconnect structures would form an FEOL region);
a first guard structure formed in the first substrate and disposed between the first circuit and the second circuit (106-1 and 106-2, Fig. 1 and Fig. 3B, para [0022] describes a first guard structure 106 comprising guard structures 106-1 and 106-2 between the first circuit 102 and second circuit 104), the first guard structure comprising a first group of discontinuous pairs of N+ and P+ wells disposed along a first column (106-1, 202 and 204, Fig. 1, Fig. 2B and Fig. 3B, para [0025] describes wherein the first guard structure 106 comprises a first group 108-1 of discontinuous N+ diffusion regions 202 and P+ diffusion regions 204 forming N-wells and P-wells as described in para [0029] and shown in Fig. 2B and disposed along a first column 106-1 as shown in Fig. 3B);
a second guard structure formed in the first substrate and disposed between the first circuit and the second circuit (106-3, Fig. 1 and Fig. 3B, para [0022] describes a second guard structure 106-3 between the first circuit 102 and second circuit 104), the second guard structure comprising a second group of discontinuous pairs of N+ and P+ wells disposed along a first column (106-3, 202 and 204, Fig. 1, Fig. 2B and Fig. 3B, para [0027] describes wherein the second guard structure 106-3 comprises a second group 108-3 of discontinuous N+ diffusion regions 202 and P+ diffusion regions 204 forming N-wells and P-wells as described in para [0029] and shown in Fig. 2B and disposed along a first column of the second guard structure 106-3 as shown in Fig. 3B).
Jing fails to explicitly disclose a back end of the line (BEOL) region formed on the FEOL region, the first substrate, the FEOL region and the BEOL region comprising at least a portion of a first integrated circuit (IC) die; a plurality of vias formed through the first substrate, the plurality of vias disposed between the first guard structure and the second guard structure, the first guard structure, the second guard structure, and the plurality of vias forming a first noise isolation structure; and a via stack formed through the FEOL and BEOL regions, the via stack electrically connected to one of the plurality of vias formed through the first substrate.
However, Chen teaches a similar electronic device comprising:
a back end of the line (BEOL) region formed on the FEOL region (M1, M2, M3 and M4, Fig. 1C, para [0015] describes an interconnect structure formed on the FEOL region comprising metallization layers M1, M2, M3 and M4), the first substrate, the FEOL region and the BEOL region comprising at least a portion of a first integrated circuit (IC) die (20, Fig. 1A and Fig. 1C, para [0009] describes a first substrate 20 and an integrated circuit structure 24 and Fig. 1C further depicts wherein a first integrated circuit 24 and a second integrated circuit 24 are formed on a front surface of substrate 20 at a front end of the line (FEOL) region at an ILD layer and the BEOL region comprising the interconnect structure form at least a portion of a first integrated circuit die as shown in Fig. 1C)
a plurality of vias formed through the first substrate (50, Fig. 1A, para [0009] describes a plurality of through substrate vias 50 formed through substrate 20), the plurality of vias disposed between the first guard structure and the second guard structure (50, 26 and 48, Fig. 1A and Fig. 1B, para [0009] and para [0010] describes wherein the plurality of through substrate vias 50 are disposed between a first guard structure 48 and a second guard structure 26), the first guard structure, the second guard structure, and the plurality of vias forming a first noise isolation structure (50, 26 and 48, Fig. 1A and Fig. 1B, para [0009] and para [0010] describe wherein a first guard structure 48, a second guard structure 26 and the plurality of vias 50 form a noise decoupling structure); and
a via stack formed through the FEOL and BEOL regions, the via stack electrically connected to one of the plurality of vias formed through the first substrate (52 and 54, Fig. 1C, para [0015] describes a via stack comprising metal lines 54 and vias 52 formed through the FEOL and BEOL regions wherein the via stack is electrically connected at least one of the plurality of vias 50 formed through the first substrate 20).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Jing with Chen to further disclose an electronic device comprising a plurality of vias formed through a first substrate, the plurality of vias disposed between a first guard structure and a second guard structure, the first guard structure, the second guard structure, and the plurality of vias forming a first noise isolation structure in order to provide the advantage of providing grounded through substrate vias that may collect electrons leaked from devices preventing signal coupling and achieving a better signal isolation (Chen, para [0020]) and to further disclose a back end of the line (BEOL) region formed on an FEOL region, the first substrate, the FEOL region and the BEOL region comprising at least a portion of a first integrated circuit (IC) die and a via stack formed through the FEOL and BEOL regions, the via stack electrically connected to one of the plurality of vias formed through the first substrate in order to provide the advantage of enabling an electrical pathway between the through substrate vias and an overlying metallization structure to enabling the through substrate vias to be connected to overlying integrated circuit die components so that they may collect electrons leaked from devices preventing signal coupling and achieving a better signal isolation (Chen, para [0020]).
Regarding Claim 12, the combination of Jing and Chen teaches the electronic device of claim 11, wherein the first guard structure comprises:
a second group of discontinuous pairs of N+ and P+ wells disposed along a second column that runs adjacent the first column (Jing, 106-2, 202 and 204, Fig. 1, Fig. 2B and Fig. 3B, para [0025] describes wherein the first guard structure 106 comprises a second group 108-2 of discontinuous N+ diffusion regions 202 and P+ diffusion regions 204 forming N-wells and P-wells as described in para [0029] and shown in Fig. 2B and disposed along a second column 106-2 adjacent to the first column 106-1 as shown in Fig. 3B).
Regarding Claim 13, the combination of Jing and Chen teaches the electronic device of claim 12, wherein the pairs of N+ and P+ wells comprising the first column are staggered relative to the pairs of N+ and P+ wells comprising the second column (Jing, 106-1, 106-2, 108-1 and 108-2, Fig. 3B, para [0027] describes wherein the N+/P+ pairs 108-1 comprising the first column 106-1 are staggered relative to the N+/P+ pairs 108-2 comprising the second column 106-2).
Regarding Claim 14, the combination of Jing and Chen teaches the electronic device of claim 13, wherein at least one of the pairs of N+ and P+ wells comprising the first column (Jing, 108-1, Fig. 3B, para [0027] describes pairs of N+ and P+ wells 108-1 of the first column 106-1 wherein at least one of the pairs can be seen in box 108-1 in Fig. 3B) is overlapped with at least one of the pairs of N+ and P+ wells comprising the second column in a direction perpendicular to a direction of the first column (Jing, 108-2, 108-1, Fig. 3B, para [0027] describes pairs of N+ and P+ wells 108-2 of the second column 106-2 wherein at least one of the pairs can be seen in box 108-2 in Fig. 3B overlapping with the at least one of the pairs of N+ and P+ wells 108-1 of the first column 106-1 seen in box 108-1 in Fig. 3B in an X direction perpendicular to a Y direction of the first column 106-1).
Regarding Claim 15, the combination of Jing and Chen teaches the electronic device of claim 13, wherein a first pair of the pairs of N+ and P+ wells comprising the first column (Jing, FP and 106-1, annotated Fig. 3B depicts a first pair FP of the pairs of N+ and P+ wells 108-1 comprising the first column 106-1) is overlapped with two of the pairs of N+ and P+ wells comprising the second column in a direction perpendicular to a direction of the first column (Jing, FP, SP, 106-2 and 106-1, annotated Fig. 3B depicts second pairs SP of the pairs of N+ and P+ wells 108-2 comprising the second column 106-2 overlapped with the first pair FP in an X direction perpendicular to a Y direction of the first column 106-1).
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Regarding Claim 16, the combination of Jing and Chen teaches the electronic device of claim 11, wherein the plurality of vias formed through the first substrate comprises:
a first column of ground vias circumscribed by the first guard structure (Chen, 50 and 26, Fig. 1A and Fig. 1B depicts wherein a first column of ground vias 50 on a left side of the integrated circuit device 24 in Fig. 1B is circumscribed by the first guard structure 48).
Regarding Claim 17, the combination of Jing and Chen teaches the electronic device of claim 16, wherein the plurality of vias formed through the first substrate comprises:
a first column of ground vias (Chen, 50 and FC, annotated Fig. 1B depicts a first column of ground vias FC) and a second column of ground vias (Chen, 50 and SC, annotated Fig. 1B depicts a second column of ground vias SC), the first and second columns of ground vias disposed between the first guard structure and the second guard structure (FC, SC, 26 and 48, annotated Fig. 1B depicts wherein the first column of ground vias FC and the second column of ground vias SC are disposed between the first guard structure 48 and the second guard structure 26).
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Chen fails to explicitly disclose in the embodiment of Fig. 1B wherein the first and second columns of ground vias disposed between the first circuit and the second circuit.
However, Chen teaches a further embodiment wherein the first (FC2, annotated Fig. 2 depicts a first column FC2 of ground vias 50) and second columns of ground vias (SC2, annotated Fig. 2 depicts a second column SC2 of ground vias 50) disposed between the first circuit and the second circuit (24, annotated Fig. 2 depicts the first column FC2 of ground vias 50 and the second column SC2 of ground vias 50 wherein upon combining the embodiment of annotated Fig. 2 with the embodiment of Fig. 1C the first column FC2 of ground vias 50 and the second column SC2 of ground vias 50 would be between the first device FD and the second device SD from annotated Fig. 1C).
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Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Jing and Chen with the further embodiments taught by Chen to further disclose an electronic device wherein a first and a second columns of ground vias are disposed between a first circuit and a second circuit in order to provide the well-known advantage of increasing a density of grounded vias thus increasing the signal isolation between adjacent circuits preventing undesirable characteristics in each of the devices.
Regarding Claim 18, the combination of Jing and Chen teaches the electronic device of claim 17, wherein the vias comprising the second column of vias are offset relative to the vias comprising the first column of vias (Chen, FC2 and SC2, annotated Fig. 2 depicts wherein the second column of ground vias SC2 are offset relative to the vias comprising the first column of ground vias FC2).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Jing Jing et al. (US 2018/0083096 A1; hereinafter “Jing”) in view of Chia-Chung Chen et al. (US 2015/0104925 A1; hereinafter “Chen”) in further view of Clinton Chao et al. (US 2008/0073747 A1; hereinafter “Chao”).
Regarding Claim 19, the combination of Jing and Chen discloses all the limitations of claim 11.
Jing and Chen fail to explicitly disclose the electronic device of claim 11 further comprising: a second IC die stacked on the first IC die, the second IC die comprising: a second noise isolation structure disposed between first and second circuits of the second IC die, the second noise isolation structure comprising: first and second guard structures separated by a plurality of grounded vias, the first and second guard structures separated by a plurality of grounded vias, the plurality of grounded vias of the second IC die electrically connected to the plurality of grounded vias and via stack of the first IC die.
However, Chao discloses a similar electronic device further comprising:
a second IC die stacked on the first IC die (27 and 28, Fig. 5A, para [0034] describes a second IC die 28 stacked on a first IC die 27), the second IC die comprising:
a second noise isolation structure disposed between first and second circuits of the second IC die (12, 14 and 32, Fig. 5A, para [0034] describes through-silicon vias 32 forming a noise isolation structure between first circuit 12 and second circuit 14 of the second IC die 28), the second noise isolation structure comprising:
a plurality of grounded vias of the second IC die electrically connected to the plurality of grounded vias and via stack of the first IC die (32 and 16, annotated Fig. 5A, para [0034] describes wherein the plurality of grounded vias 32 of the second IC die SIC are electrically connected to the plurality of grounded vias 16 of the first integrated circuit die 27 through a via stack including contact plugs 26 wherein the plurality of vias 32 and 16 are grounded through conductive layer 20 as described in para [0028]).
Chao fails to explicitly disclose first and second guard structures separated by a plurality of grounded vias, the first and second guard structures separated by a plurality of grounded vias.
However, Chen teaches a similar IC die as the second IC comprising first and second guard structures separated by a plurality of grounded vias (50, 26 and 48, Fig. 1A and Fig. 1B, para [0009] and para [0010] describes wherein a plurality of through substrate vias 50 are disposed between a first guard structure 48 and a second guard structure 26), the first and second guard structures separated by a plurality of grounded vias (50, 26 and 48, Fig. 1A and Fig. 1B, para [0009] and para [0010] describes wherein the plurality of through substrate vias 50 separate the first guard structure 48 and a second guard structure 26).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Jing and Chen with Chao to further disclose an electronic device comprising a second IC die stacked on a first IC die, the second IC die comprising: a second noise isolation structure disposed between first and second circuits of the second IC die, the second noise isolation structure comprising: a plurality of grounded vias of the second IC die electrically connected to the plurality of grounded vias and a via stack of the first IC die in order to provide the well-known advantage of enabling an electronic device to comprise a die stack with an interconnected isolation structure thus increasing device density in a smaller form factor to keep up with Moore’s law and to simplify the manufacturing process and to further incorporate the isolation structure of Chen in the second IC die of Chao wherein such an isolation structure comprises first and second guard structures separated by a plurality of grounded vias, the first and second guard structures separated by a plurality of grounded vias in order to provide the advantage of providing grounded through substrate vias and well regions that may collect electrons leaked from devices preventing signal coupling and achieving a better signal isolation (Chen, para [0020]).
Conclusion
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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