Attorney Docket Number: 22RO0368US01/50649-01967
Filing Date: 12/01/2023
Claimed Foreign Priority Date: 12/02/2022 (FR2212707)
Inventors: Rivero et al.
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the application filed 12/01/2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the
first inventor to file provisions of the AIA . In the event the determination of the status of the
application as to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis
(i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of
rejection if the prior art relied upon, and the rationale supporting the rejection, would be the
same under either status.
Claim Objections
Claim 1 is objected to because of the following informalities: “…a second portion prolonging said first portion…”, is improper. For the purposes of examination, the limitation will be construed as “…a second portion prolonging from said first portion”. Appropriate correction is required.
Claim 1 is objected to because of the following informalities: “…a second portion prolonging said first portion…”, is improper. For the purposes of examination, the limitation will be construed as “…a second portion prolonging from said first portion”. Appropriate correction is required.
Claim 13 is objected to because of the following informalities: “…a control gate over the floating gate and extending adjacent side edges of the control gate and over the drain and the source…” is unclear. For the purposes of examination, the limitation will be construed as “… a control gate over the floating gate, wherein the control gate extends to comprise side edges over the drain and the source…”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, 11-12, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Nazarian (US 20160268341 A1) in view of Konrath (US 20200066857 A1).
Regarding claim 1, Nazarian (see, e.g., fig. 4) shows most aspects of the instant invention, including an integrated circuit comprising:
A semiconductor substrate (e.g., substrate 410 + paragraph 65 “Substrate 410 can be a suitable semiconductor material…”);
At least one capacitor transistor (e.g., transistor 406 + paragraph 41 “…deep trench transistor employed for low capacitor 406…” or paragraph 64 “…transistor 406 (e.g., a lower capacitor)”) supported by said semiconductor substrate (e.g., substrate 410 + paragraph 65 “Substrate 410 can be a suitable semiconductor material…”) and including:
A drain (e.g., drain 414) and a source (e.g., source 412) disposed in the semiconductor substrate (e.g., substrate 410 + paragraph 65 “Substrate 410 can be a suitable semiconductor material…”);
A gate (e.g., gate 408) having a first portion (e.g., gate portion extending into substrate 410) extending in depth in the semiconductor substrate (e.g., substrate 410 + paragraph 65 “Substrate 410 can be a suitable semiconductor material…”), and a second portion (e.g., expanded portion over substrate 410) prolonging from said first portion (e.g., gate portion extending into substrate 410) and extending over the semiconductor substrate (e.g., substrate 410 + paragraph 65 “Substrate 410 can be a suitable semiconductor material…”);
An insulating layer (e.g., insulating film 420) extending between the gate (e.g., gate 408) and the semiconductor substrate (e.g., substrate 410 + paragraph 65 “Substrate 410 can be a suitable semiconductor material…”)
While Nazarian (see, e.g., fig. 4) fails to explicitly show etching a trench in the semiconductor substrate and depositing an electrically conductive layer in the current embodiment, an alternate embodiment (see, e.g., figs. 6-9) teaches etching (see, e.g., paragraph 70) that the insulating layer extending between the gate and the semiconductor substrate is a dielectric layer.
Konrath (see, e.g., fig. 1A), in a similar device to Nazarian, teaches forming a dielectric layer (e.g., gate dielectric 104) extending between a gate (e.g., gate electrode 106) and a semiconductor substrate (e.g., SiC semiconductor body 102).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the dielectric properties of Konrath within the insulating film of Nazarian, in order to achieve the expected result of providing dielectric properties and an oxide (see paragraph 26 of Konrath) adjacent to the gate structure within the transistor setup.
Regarding claim 5, Konrath (see, e.g., paragraph 26) teaches wherein the dielectric layer (e.g., gate dielectric 104) is an oxide layer (see, e.g., paragraph 26 “The gate dielectric may include or consist of one layer or a combination of layers, e.g. a layer stack of dielectric layers, for example oxide layers…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the oxide of Konrath within the dielectric layer of Nazarian in view of Konrath, as oxide was a well-known material at the time of filing the invention to include within a gate dielectric, as taught by Konrath.
Regarding claim 11, the current embodiment of Nazarian (see, e.g., fig. 4) fails to show wherein said at least one capacitive transistor further comprises two dielectric strips extending completely over lateral borders of the second portion of the gate.
An alternate embodiment of Nazarian, however (see, e.g., fig. 5), teaches wherein a transistor (e.g., deep trench transistor 502) further comprises two dielectric strips (e.g., dielectric spacers 512A + 512B) extending completely over lateral borders of a second portion (see, e.g., gate 511 portion over trench) of a gate (e.g., gate 511).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the dielectric strips of the alternate embodiment of Nazarian (e.g., fig. 5) within the current embodiment of Nazarian (e.g., fig. 4), in order to provide additional dielectric protection between the gate structure and other electronic components or devices, as desired.
Regarding claim 12, the current embodiment of Nazarian (see, e.g., fig. 4) fails to show wherein said at least one capacitive transistor further comprises two dielectric strips extending over lateral borders of the second portion of the gate.
An alternate embodiment of Nazarian, however (see, e.g., fig. 5), teaches wherein a transistor (e.g., deep trench transistor 502) further comprises two dielectric strips (e.g., dielectric spacers 512A + 512B) extending over lateral borders of a second portion (see, e.g., gate 511 portion over trench) of a gate (e.g., gate 511) and over a semiconductor substrate (e.g., substrate 501).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the dielectric strips of the alternate embodiment of Nazarian (e.g., fig. 5) within the current embodiment of Nazarian (e.g., fig. 4), in order to provide additional dielectric protection between the gate structure and other electronic components or devices, as desired.
Regarding claim 15, Nazarian (see, e.g., fig. 4) shows wherein a part of the first portion (e.g., gate portion extending into substrate 410) of the gate (e.g., gate 408) of the capacitive transistor (e.g., transistor 406 + paragraph 41 “…deep trench transistor employed for low capacitor 406…” or paragraph 64 “…transistor 406 (e.g., a lower capacitor)”) extends beyond an outer perimeter (see, e.g., annotated fig. 1 below) of the second portion (e.g., expanded portion over substrate 410) of the gate (e.g., gate 408) of the capacitive transistor (e.g., transistor 406 + paragraph 41 “…deep trench transistor employed for low capacitor 406…” or paragraph 64 “…transistor 406 (e.g., a lower capacitor)”).
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Annotated Fig. 1
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Nazarian in view of Konrath further in view of Lee (US 20220231028 A1).
Regarding claim 2, Nazarian in view of Konrath fails to teach wherein the first portion of the gate of said at least one capacitive transistor extends in depth in the substrate over a distance comprised between 300 and 1200 nanometers.
Lee (see, e.g., fig. 4A), in a similar device to Nazarian in view of Konrath, teaches a gate structure (e.g., conductive layer 203 of gate trench 103) extends in depth (e.g., gate trench 103) into a substrate (e.g., substrate 100), wherein the depth of the gate structure (e.g.., gate structure 203) is approximately 300 nm (see, e.g., claim 5 “…a depth of the gate trench is 100 nm to 300 nm…” – note that conductive layer 203 fills out a substantially large part of the gate trench, so the length is substantially close to 300 nm).
With regards to the particular range claimed, i.e. 300 nanometers to 1200 nanometers, it is noted that the specification fails to provide teachings about the criticality of the claimed range, and the courts have held that differences in lengths (or ranges thereof) will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such lengths are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph below) of the claimed length ranges, and since Lee teaches a gate structure substantially close to the 300 nanometer length, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to use these length values within the gate depth extension of Nazarian in view of Konrath into the substrate, in order to achieve the expected result of providing a limited but distinct gate extension depth into the substrate as desired.
CRITICALITY: The specification contains no disclosure of either the critical nature of the claimed length ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 3, Nazarian (see, e.g., fig. 4) shows wherein the first portion (e.g., gate portion extending into substrate 410) of the gate (e.g., gate 408) of said at least one capacitive transistor (e.g., transistor 406 + paragraphs 41 or 64) has width comprised between 100 nanometers and 300 nanometers (see, e.g., paragraph 64 “the gate 408 can be a low-profile gate having a width substantially equal to a width or a p-well…In some embodiments, the width of the p-well (and approximate width of gate 408) can be about 100 nanometers…”).
Regarding claim 4, Nazarian (see, e.g., fig. 4) shows the second portion (e.g., expanded portion over substrate 410) of the gate (e.g., gate 408) of said at least one capacitive transistor (e.g., transistor 406 + paragraph 41 “…deep trench transistor employed for low capacitor 406…” or paragraph 64 “…transistor 406 (e.g., a lower capacitor)”) has a thickness substantially comprised between 100 nanometers and 200 nanometers (see, e.g., paragraph 64 “In some embodiments, the width of the p-well (and approximate width of gate 408) can be about 100 nanometers…” ).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Nazarian in view of Konrath further in view of Wang (US 20220271131 A1).
Regarding claim 6, Nazarian in view of Konrath fails to teach wherein the dielectric layer of said at least one capacitive transistor has a thickness comprised between 8 nanometers and 40 nanometers.
Wang (see, e.g., fig. 4), in a similar device to Nazarian in view of Konrath teaches a dielectric layer (e.g., gate oxide layer 111) has a thickness comprised between 8 nanometers and 40 nanometers (see, e.g., paragraph 35 “…the thickness of the first gate oxide layer 111 is 3 nm-10nm…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the thickness profile of Wang within the dielectric layer of Nazarian in view of Konrath, in order to achieve the expected result of providing a thin gate oxide layer profile, limiting the cost of manufacturing, while still maintaining the necessary gate oxide properties.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Nazarian in view of Konrath further in view of Kansagra (US 20240088014 A1).
Regarding claim 7, Nazarian in view of Konrath fails to teach a first contact connected to the second portion of the gate of said at least one capacitive transistor and a second contact connected to the source or to the drain of said at least one capacitive transistor.
Kansagra (see, e.g., fig. 1), in a similar device to Nazarian in view of Konrath, teaches a first contact (e.g., gate contact 135) connected to a gate (e.g., gate 115) and a second contact (e.g., first source/drain contact 130-1) connected to the source or to the drain (e.g., source/drain 120-1).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the gate contact and source/drain contact of Kansagra onto the gate and source or drain of Nazarian in view of Konrath, in order to achieve the expected result of providing direct connection to the source/drain region for electrical current flow, as well as providing gate flow and electrical connectivity to other portions of the device as necessary.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Nazarian in view of Konrath further in view of Chowdhury (US 20170229569 A1).
Regarding claim 8, Nazarian in view of Konrath fails to teach the gate of said at least one capacitive transistor is made of polysilicon.
Chowdhury (see, e.g., fig. 2), in a similar device to Nazarian in view of Konrath, teaches a gate (e.g., gate 22) is made of polysilicon (see, e.g., paragraph 74 “Examples of suitable gate materials include, but are not limited to, …polysilicon…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the polysilicon of Chowdhury within the gate of Nazarian in view of Konrath, as polysilicon was a well-known material at the time of filing the invention to include within a gate, as taught by Chowdhury.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Nazarian in view of Konrath further in view of Jacek (EP 2880688 B1).
Regarding claim 9, Nazarian in view of Konrath fails to teach comprising several capacitive transistors, the second portion of the gate of capacitive transistor being common for said several capacitive transistors.
Jacek (see, e.g., fig. 8), in a similar device to Nazarian in view of Konrath, teaches a shared portion (e.g., upper polysilicon material 810) among numerous gate trench structure (e.g., trenches 806).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include numerous trench and shared gate portion configuration of Jacek within the device of Nazarian in view of Konrath, in order to expand the gate configuration and connect the vertical channel structure within the substrate, enhancing current density within the device.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Nazarian in view of Konrath further in view of Jacek and Itokazu (US 20220085216 A1).
Regarding claim 10, Jacek (see, e.g., fig. 8) teaches wherein first portions (e.g., polysilicon material 810 within trenches 806) of the gates (e.g., polysilicon material 810) extend in depth (see, e.g., fig. 8) and are spaced apart from each other.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the spacing configuration of Jace with the device to Nazarian in view of Konrath further in view of Lu, in order to in order to expand the gate configuration and connect the vertical channel structure within the substrate, enhancing current density within the device.
Nazarian in view of Konrath further in view of Lu and Jacek, however, fail to teach the trenches are spaced apart from each other by a distance comprised between .1 micrometers and 1.5 micrometers.
Itokazu (see, e.g., figs. 1A-1B), in a similar device to Nazarian in view of Konrath further in view of Lu and Jacek, teaches gate trenches (e.g., trenches of electrodes 30) are spaced apart from each other by a distance substantially close to 1.5 micrometers (see, e.g., paragraph 27 “…the spacing between the adjacent trenches AT…are 1.6 micrometers…”).
With regards to the particular spacing distance claimed, i.e. .1 micrometers and 1.5 micrometers, it is noted that the specification fails to provide teachings about the criticality of the claimed range, and the courts have held that differences in lengths (or ranges thereof) will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such lengths are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph below) of the claimed length ranges, and since Itokazu teaches a spacing of 1.6 micrometers, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to slightly modify these spacing values between the gate trenches of Nazarian in view of Konrath further in view of Lu and Jacek, in order to provide additional spacing or connectivity requirements as desired within the device.
CRITICALITY: The specification contains no disclosure of either the critical nature of the claimed distance ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Nazarian in view of Konrath further in view of Toh (US 20160268387 A1).
Regarding claim 13, Nazarian in view of Konrath fails to teach at least one planar transistor including: a drain and a source disposed in the semiconductor substrate; a floating gate extending over the semiconductor substrate and having a same thickness as the second portion of the gate of said at least one capacitive transistor; a control gate over the floating gate, wherein the control gate extends to comprise side edges over the drain and the source in the semiconductor substrate; a first dielectric layer extending between the floating gate and the semiconductor substrate, and being of a same nature as the dielectric layer of said at least one capacitive transistor which extends between the gate of the capacitive transistor and the semiconductor substrate; and a second dielectric layer extending between the floating gate and the control gate.
Toh (see, e.g., fig. 3B), in a similar device to Nazarian in view of Konrath, teaches at least one planar transistor including a drain (e.g., drain 317) and a source (e.g., source 317) disposed in the semiconductor substrate (e.g., substrate 301) a floating gate (e.g., floating gate 311) extending over the semiconductor substrate (e.g., substrate 301), a control gate (e.g., control gate 307) over the floating gate (e.g., floating gate 311), wherein the control gate (e.g., control gate 307) extends to comprise side edges (e.g., side edges of control gate 307) and over the drain (e.g., drain 317) and the source (e.g., source 317) in the semiconductor substrate (e.g., substrate 301); a first dielectric layer (e.g., tunneling oxide layer 313) extending between the floating gate (e.g., floating gate 311) and the semiconductor substrate (e.g., substrate 301), and a second dielectric layer (e.g., interpoly dielectric layer 309) extending between the floating gate (e.g., floating gate 311) and the control gate (e.g., control gate 307).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the transistor of Toh within the device of Nazarian in view of Konrath, in order to achieve the expected result of providing additional performance within the device with the inclusion of additional transistor setups for additional memory and circuit capabilities. Note that the first dielectric layer of Toh is the same material as the dielectric layer between the gate and the semiconductor substrate of Nazarian in view of Konrath (both are made of oxide).
With regards to the particular range claimed, i.e. 100 nanometers (the same thickness as the second portion of the gate of said at least one capacitive transistor), it is noted that the specification fails to provide teachings about the criticality of the claimed range, and the courts have held that differences in lengths (or ranges thereof) will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such lengths are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph below) of the claimed length ranges, and since Toh teaches a gate width of a 50 nanometer length, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to use these width values within the gate depth extension of Nazarian in view of Konrath into the substrate, in order to achieve the expected result of providing a limited but distinct gate extension depth into the substrate as desired.
CRITICALITY: The specification contains no disclosure of either the critical nature of the claimed length ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 14, Toh (see, e.g., fig. 3B) teaches wherein a portion of the floating gate (e.g., floating gate 311) extends beyond (e.g., note that floating gate 311 and control gate 307 bodies are distinct and do not have overlapping perimeters) on an outer perimeter of the control gate (e.g., control gate 307).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the non-overlapping perimeter extension of Toh within the configuration of Nazarian in view of Konrath further in view of Toh, in order to allow distinct yet functional control gate and floating gate bodies within the planar transistor.
Claims 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Nazarian in view of Konrath further in view of Lu (US 20190035792 A1).
Regarding claim 16, Nazarian (see, e.g., fig. 4) shows most aspects of the instant invention, including a method for manufacturing an integrated circuit comprising:
Manufacturing at least one capacitor transistor (e.g., transistor 406 + paragraphs 41 or 64) over a semiconductor substrate (e.g., substrate 410 + paragraph 65 “Substrate 410 can be a suitable semiconductor material…”); wherein manufacturing said at least one capacitive transistor (e.g., transistor 406 + paragraphs 41 or 64) comprises:
Forming a drain (e.g., drain 414) and a source (e.g., source 412) of said at least one capacitive transistor (e.g., transistor 406 + paragraphs 41 or 64) in the semiconductor substrate (e.g., substrate 410 + paragraph 65 “Substrate 410 can be a suitable semiconductor material…”);
Forming a gate (e.g., gate 408) having a first portion (e.g., gate portion extending into substrate 410) extending in depth in the semiconductor substrate (e.g., substrate 410 + paragraph 65 “Substrate 410 can be a suitable semiconductor material…”), and a second portion (e.g., expanded portion over substrate 410) prolonging from said first portion (e.g., gate portion extending into substrate 410) and extending over the semiconductor substrate (e.g., substrate 410 + paragraph 65 “Substrate 410 can be a suitable semiconductor material…”);
Forming an insulating layer (e.g., insulating film 420) extending between the gate (e.g., gate 408) and the semiconductor substrate (e.g., substrate 410 + paragraph 65 “Substrate 410 can be a suitable semiconductor material…”)
Nazarian (see, e.g., fig. 4), however, fails to explicitly show that the insulating layer extending between the gate and the semiconductor substrate is a dielectric layer, while also failing to show etching into the substrate and depositing the conductive layer in order to form the gate.
Konrath (see, e.g., fig. 1A), in a similar device to Nazarian, teaches a dielectric layer (e.g., gate dielectric 104) extending between a gate (e.g., gate electrode 106) and a semiconductor substrate (e.g., SiC semiconductor body 102).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the dielectric properties of Konrath within the insulating film of Nazarian, in order to achieve the expected result of providing dielectric properties and an oxide (see paragraph 26 of Konrath) adjacent to the gate structure within the transistor setup.
Nazarian in view of Konrath, however, fails to teach etching into the substrate and depositing a conductive layer to form the gate structure.
Lu (see, e.g., figs. 3-5), in a similar device to Nazarian in view of Konrath, teaches etching (see, e.g., paragraph 29 “the etching is continued to etch the semiconductor substrate so as to form a lower trench 220”) into a substrate and depositing a conductive layer (e.g., gate tungsten layer 301) to form a gate structure (e.g., gate 300).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the etching and deposition step of Lu within the method of Nazarian in view of Konrath, as etching into a substrate and depositing a conductive layer within the etched portion was a well-known step at the time of filing the invention to form a gate trench structure within a semiconductor substrate, as taught by Lu.
Regarding claim 20, Konrath (see, e.g., paragraph 26) teaches wherein the dielectric layer (e.g., gate dielectric 104) is an oxide layer (see, e.g., paragraph 26 “The gate dielectric may include or consist of one layer or a combination of layers, e.g. a layer stack of dielectric layers, for example oxide layers…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the oxide of Konrath within the dielectric layer of Nazarian in view of Konrath, as oxide was a well-known material at the time of filing the invention to include within a gate dielectric, as taught by Konrath.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Nazarian in view of Konrath further in view of Lu and Wang.
Regarding claim 21, Nazarian in view of Konrath further in view of Lu fails to teach wherein the dielectric layer of said at least one capacitive transistor has a thickness comprised between 8 nanometers and 40 nanometers.
Wang (see, e.g., fig. 4), in a similar device to Nazarian in view of Konrath further in view of Lu teaches a dielectric layer (e.g., gate oxide layer 111) has a thickness comprised between 8 nanometers and 40 nanometers (see, e.g., paragraph 35 “…the thickness of the first gate oxide layer 111 is 3 nm-10 nm…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the thickness profile of Wang within the dielectric layer of Nazarian in view of Konrath further in view of Lu, in order to achieve the expected result of providing a thin gate oxide layer profile, limiting the cost of manufacturing, while still maintaining the necessary gate oxide properties.
Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Nazarian in view of Konrath further in view of Lu and Lee.
Regarding claim 17, Nazarian in view of Konrath further in view of Lee fails to teach wherein the first portion of the gate of said at least one capacitive transistor extends in depth in the substrate over a distance comprised between 300 and 1200 nanometers.
Lee (see, e.g., fig. 4A), in a similar device to Nazarian in view of Konrath further in view of Lee, teaches a gate structure (e.g., conductive layer 203 of gate trench 103) extends in depth (e.g., gate trench 103) into a substrate (e.g., substrate 100), wherein the depth of the gate structure (e.g.., gate structure 203) is approximately 300 nm (see, e.g., claim 5 “…a depth of the gate trench is 100 nm to 300 nm…” – note that conductive layer 203 fills out a substantially large part of the gate trench, so the length is substantially close to 300 nm).
With regards to the particular range claimed, i.e. 300 nanometers to 1200 nanometers, it is noted that the specification fails to provide teachings about the criticality of the claimed range, and the courts have held that differences in lengths (or ranges thereof) will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such lengths are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph below) of the claimed length ranges, and since Lee teaches a gate structure substantially close to the 300 nanometer length, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to use these length values within the gate depth extension of Nazarian in view of Konrath into the substrate, in order to achieve the expected result of providing a limited but distinct gate extension depth into the substrate as desired.
CRITICALITY: The specification contains no disclosure of either the critical nature of the claimed length ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 18, Nazarian (see, e.g., fig. 4) shows wherein the first portion (e.g., gate portion extending into substrate 410) of the gate (e.g., gate 408) of said at least one capacitive transistor (e.g., transistor 406 + paragraphs 41 or 64) has width comprised between 100 nanometers and 300 nanometers (see, e.g., paragraph 64 “the gate 408 can be a low-profile gate having a width substantially equal to a width or a p-well…In some embodiments, the width of the p-well (and approximate width of gate 408) can be about 100 nanometers…”).
Regarding claim 19, Nazarian (see, e.g., fig. 4) shows the second portion (e.g., expanded portion over substrate 410) of the gate (e.g., gate 408) of said at least one capacitive transistor (e.g., transistor 406 + paragraph 41 “…deep trench transistor employed for low capacitor 406…” or paragraph 64 “…transistor 406 (e.g., a lower capacitor)”) has a thickness substantially comprised between 100 nanometers and 200 nanometers (see, e.g., paragraph 64 “In some embodiments, the width of the p-well (and approximate width of gate 408) can be about 100 nanometers…” ).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Nazarian in view of Konrath further in view of Lu and Kansagra.
Regarding claim 22, Nazarian in view of Konrath further in view of Lu fails to teach a first contact connected to the second portion of the gate of said at least one capacitive transistor and a second contact connected to the source or to the drain of said at least one capacitive transistor.
Kansagra (see, e.g., fig. 1), in a similar device to Nazarian in view of Konrath further in view of Lu, teaches a first contact (e.g., gate contact 135) connected to a gate (e.g., gate 115) and a second contact (e.g., first source/drain contact 130-1) connected to the source or to the drain (e.g., source/drain 120-1).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the gate contact and source/drain contact of Kansagra onto the gate and source or drain of Nazarian in view of Konrath further in view of Lu, in order to achieve the expected result of providing direct connection to the source/drain region for electrical current flow, as well as providing gate flow and electrical connectivity to other portions of the device as necessary.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Nazarian in view of Konrath further in view of Lu and Chowdhury.
Regarding claim 8, Nazarian in view of Konrath further in view of Lu fails to teach the gate of said at least one capacitive transistor is made of polysilicon.
Chowdhury (see, e.g., fig. 2), in a similar device to Nazarian in view of Konrath further in view of Lu, teaches a gate (e.g., gate 22) is made of polysilicon (see, e.g., paragraph 74 “Examples of suitable gate materials include, but are not limited to, …polysilicon…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the polysilicon of Chowdhury within the gate of Nazarian in view of Konrath further in view of Lu, as polysilicon was a well-known material at the time of filing the invention to include within a gate, as taught by Chowdhury.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Nazarian in view of Konrath further in view of Lu and Jacek.
Regarding claim 24, Nazarian in view of Konrath further in view of Lu fails to teach comprising several capacitive transistors, the second portion of the gate of capacitive transistor being common for said several capacitive transistors.
Jacek (see, e.g., fig. 8), in a similar device to Nazarian in view of Konrath further in view of Lu, teaches a shared portion (e.g., upper polysilicon material 810) among numerous gate trench structure (e.g., trenches 806).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include numerous trench and shared gate portion configuration of Jacek within the device of Nazarian in view of Konrath further in view of Lu, in order to expand the gate configuration and connect the vertical channel structure within the substrate, enhancing current density within the device.
Claims 25-27 are rejected under 35 U.S.C. 103 as being unpatentable over Nazarian in view of Konrath further in view of Lu, Jacek, Itokazu.
Regarding claim 25, Jacek (see, e.g., fig. 8) teaches wherein first portions (e.g., polysilicon material 810 within trenches 806) of the gates (e.g., polysilicon material 810) extend in depth (see, e.g., fig. 8) and are spaced apart from each other.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the spacing configuration of Jace with the device to Nazarian in view of Konrath further in view of Lu, in order to in order to expand the gate configuration and connect the vertical channel structure within the substrate, enhancing current density within the device.
Nazarian in view of Konrath further in view of Lu and Jacek, however, fail to teach the trenches are spaced apart from each other by a distance comprised between .1 micrometers and 1.5 micrometers.
Itokazu (see, e.g., figs. 1A-1B), in a similar device to Nazarian in view of Konrath further in view of Lu and Jacek, teaches gate trenches (e.g., trenches of electrodes 30) are spaced apart from each other by a distance substantially close to 1.5 micrometers (see, e.g., paragraph 27 “…the spacing between the adjacent trenches AT…are 1.6 micrometers…”).
With regards to the particular spacing distance claimed, i.e. .1 micrometers and 1.5 micrometers, it is noted that the specification fails to provide teachings about the criticality of the claimed range, and the courts have held that differences in lengths (or ranges thereof) will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such lengths are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph below) of the claimed length ranges, and since Itokazu teaches a spacing of 1.6 micrometers, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to slightly modify these spacing values between the gate trenches of Nazarian in view of Konrath further in view of Lu and Jacek, in order to provide additional spacing or connectivity requirements as desired within the device.
CRITICALITY: The specification contains no disclosure of either the critical nature of the claimed distance ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 26, the current embodiment of Nazarian (see, e.g., fig. 4) fails to show forming two dielectric strips extending completely over lateral borders of the second portion of the gate.
An alternate embodiment of Nazarian, however (see, e.g., fig. 5), teaches wherein a transistor (e.g., deep trench transistor 502) further comprises two dielectric strips (e.g., dielectric spacers 512A + 512B) extending completely over lateral borders of a second portion (see, e.g., gate 511 portion over trench) of a gate (e.g., gate 511).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to form the dielectric strips of the alternate embodiment of Nazarian (e.g., fig. 5) within the current embodiment of Nazarian (e.g., fig. 4), in order to provide additional dielectric protection between the gate structure and other electronic components or devices, as desired.
Regarding claim 27, the current embodiment of Nazarian (see, e.g., fig. 4) fails to show forming two dielectric strips extending over lateral borders of the second portion of the gate.
An alternate embodiment of Nazarian, however (see, e.g., fig. 5), teaches wherein a transistor (e.g., deep trench transistor 502) further comprises two dielectric strips (e.g., dielectric spacers 512A + 512B) extending over lateral borders of a second portion (see, e.g., gate 511 portion over trench) of a gate (e.g., gate 511) and over a semiconductor substrate (e.g., substrate 501).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to form the dielectric strips of the alternate embodiment of Nazarian (e.g., fig. 5) within the current embodiment of Nazarian (e.g., fig. 4), in order to provide additional dielectric protection between the gate structure and other electronic components or devices, as desired.
Claims 28 is rejected under 35 U.S.C. 103 as being unpatentable over Nazarian in view of Konrath further in view of Lu, Toh, and Chowdhury.
Regarding claim 28, Nazarian in view of Konrath fails to teach at least one planar transistor including: a drain and a source disposed in the semiconductor substrate; a floating gate extending over the semiconductor substrate and having a same thickness as the second portion of the gate of said at least one capacitive transistor; a control gate over the floating gate, wherein the control gate extends to comprise side edges over the drain and the source in the semiconductor substrate; a first dielectric layer extending between the floating gate and the semiconductor substrate, and being of a same nature as the dielectric layer of said at least one capacitive transistor which extends between the gate of the capacitive transistor and the semiconductor substrate; and a second dielectric layer extending between the floating gate and the control gate.
Toh (see, e.g., fig. 3B), in a similar device to Nazarian in view of Konrath, teaches forming a drain (e.g., drain 317) and a source (e.g., source 317) disposed in the semiconductor substrate (e.g., substrate 301), forming a floating gate (e.g., floating gate 311) extending over the semiconductor substrate (e.g., substrate 301), forming a control gate (e.g., control gate 307) extending over the floating gate (e.g., floating gate 311) and over the semiconductor substrate (e.g., substrate 301) between the drain (e.g., drain 317) and the source (e.g., source 317), forming a first dielectric layer (e.g., tunneling oxide layer 313) extending between the floating gate (e.g., floating gate 311) and the semiconductor substrate (e.g., substrate 301), and forming a second dielectric layer (e.g., interpoly dielectric layer 309) extending between the floating gate (e.g., floating gate 311) and the control gate (e.g., control gate 307).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the transistor of Toh within the device of Nazarian in view of Konrath, in order to achieve the expected result of providing additional performance within the device with the inclusion of additional transistor setups for additional memory and circuit capabilities. Note that the first dielectric layer of Toh is the same material as the dielectric layer between the gate and the semiconductor substrate of Nazarian in view of Konrath (both are made of oxide).
Nazarian in view of Konrath further in view of Lu and Toh, however, fail to teach that the gate of said at least one capacitive transistor and the floating gate of the planar transistor are of the same nature.
Chowdhury (see, e.g., fig. 2), in a similar device to Nazarian in view of Konrath further in view of Lu and Toh, teaches a gate (e.g., gate 22) is made of polysilicon (see, e.g., paragraph 74 “Examples of suitable gate materials include, but are not limited to, …polysilicon…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the polysilicon of Chowdhury within both the gate and the floating gate of Nazarian in view of Konrath further in view of Lu and Toh, as polysilicon was a well-known material at the time of filing the invention to include as a gate material, as taught by Chowdhury.
Conclusion
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/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814