Attorney Docket Number: 22RO0368US01/50649-01967
Filing Date: 12/01/2023
Claimed Foreign Priority Date: 12/02/2022 (FR2212707)
Inventors: Rivero et al.
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the amendments filed 5/01/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the
first inventor to file provisions of the AIA . In the event the determination of the status of the
application as to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis
(i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of
rejection if the prior art relied upon, and the rationale supporting the rejection, would be the
same under either status.
Acknowledgement
The Amendment filed on 5/01/2026, responding to the Office action mailed 2/02/2026, has been entered. Applicant amended claims 1, 5-6, 8, 16, 20-21, and 23, and cancelled claims 13 and 28. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this application are claims 1-12 and 14-27.
Response to Arguments/Amendment
Applicant’s amendments to the claims have overcome the claim objections and claim rejections under 35 U.S.C. 103 as previously formulated in the Non-Final Office action mailed on 2/02/2026. The Applicant’s response filed 5/01/2026 argues that Toh fails to disclose the dielectric layer 313 and the dielectric layer 327 are a same nature of material, but Toh explicitly discloses the dielectric layer 313 is an oxide and that dielectric layer 327 can also be an oxide (see, e.g., paragraph 28), and hence teaches that oxide is a well-known material to be included within a gate dielectric layer. New grounds of rejections are presented below, however, as necessitated by applicant’s amendments to the claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, 8, 11-12, and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Nazarian (US 20160268341 A1) in view of Konrath (US 20200066857 A1) further in view of Toh (US 20160268387 A1), Chowdhury (US 20170229569 A1), Müller (US 20220376114 A1), and Huang (US 20210226027 A1).
Regarding claim 1, Nazarian (see, e.g., fig. 4) shows most aspects of the instant invention, including an integrated circuit comprising:
A semiconductor substrate (e.g., substrate 410 + paragraph 65 “Substrate 410 can be a suitable semiconductor material…”);
At least one capacitor transistor (e.g., transistor 406 + paragraph 41 “…deep trench transistor employed for low capacitor 406…” or paragraph 64 “…transistor 406 (e.g., a lower capacitor)”) supported by said semiconductor substrate (e.g., substrate 410 + paragraph 65 “Substrate 410 can be a suitable semiconductor material…”) and including:
A drain (e.g., drain 414) and a source (e.g., source 412) disposed in the semiconductor substrate (e.g., substrate 410 + paragraph 65 “Substrate 410 can be a suitable semiconductor material…”);
A gate (e.g., gate 408) having a first portion (e.g., gate portion extending into substrate 410) extending in depth in the semiconductor substrate (e.g., substrate 410 + paragraph 65 “Substrate 410 can be a suitable semiconductor material…”), and a second portion (e.g., expanded portion over substrate 410) prolonging from said first portion (e.g., gate portion extending into substrate 410) and extending over the semiconductor substrate (e.g., substrate 410 + paragraph 65 “Substrate 410 can be a suitable semiconductor material…”);
An insulating layer (e.g., insulating film 420) extending between the gate (e.g., gate 408) and the semiconductor substrate (e.g., substrate 410 + paragraph 65 “Substrate 410 can be a suitable semiconductor material…”)
While Nazarian (see, e.g., fig. 4) fails to explicitly show that the insulating layer extending between the gate and the semiconductor substrate is a dielectric layer, while it also fails to show at least one planar transistor including: a drain and a source disposed in the semiconductor substrate; a floating gate extending over the semiconductor substrate; a control gate over the floating gate and extending adjacent to side edges of the floating gate and further extending over the drain and the source in the semiconductor substrate; a first dielectric layer extending between the floating gate and the semiconductor substrate; and a second dielectric layer extending between the floating gate and the control gate; wherein a same nature of material is used for the gate of the at least one capacitive transistor and the floating gate of the at least one planar transistor, the floating gate having a same thickness as the second portion of the gate; wherein a same nature of material is used for the dielectric layer extending between the gate and the semiconductor substrate and the first dielectric layer extending between the floating gate and the semiconductor substrate, the dielectric layer having a same thickness as the first dielectric layer.
Konrath (see, e.g., fig. 1A), in a similar device to Nazarian, teaches forming a dielectric layer (e.g., gate dielectric 104 + paragraph 26) extending between a gate (e.g., gate electrode 106) and a semiconductor substrate (e.g., SiC semiconductor body 102).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the dielectric properties of Konrath within the insulating film of Nazarian, in order to achieve the expected result of providing dielectric properties and an oxide (see paragraph 26 of Konrath) adjacent to the gate structure within the transistor setup.
Nazarian in view of Konrath fails to teach at least one planar transistor including: a drain and a source disposed in the semiconductor substrate; a floating gate extending over the semiconductor substrate; a control gate over the floating gate and extending adjacent to side edges of the floating gate and further extending over the drain and the source in the semiconductor substrate; a first dielectric layer extending between the floating gate and the semiconductor substrate; and a second dielectric layer extending between the floating gate and the control gate; wherein a same nature of material is used for the gate of the at least one capacitive transistor and the floating gate of the at least one planar transistor, the floating gate having a same thickness as the second portion of the gate; wherein a same nature of material is used for the dielectric layer extending between the gate and the semiconductor substrate and the first dielectric layer extending between the floating gate and the semiconductor substrate, the dielectric layer having a same thickness as the first dielectric layer.
Toh (see, e.g., fig. 3B-3G), in a similar device to Nazarian in view of Konrath, teaches at least one planar transistor including a drain (e.g., drain 317) and a source (e.g., source 317) disposed in the semiconductor substrate (e.g., substrate 301) a floating gate (e.g., floating gate 311) extending over the semiconductor substrate (e.g., substrate 301), a control gate (e.g., control gate 307) over the floating gate (e.g., floating gate 311), wherein the control gate (e.g., control gate 307) extends to comprise side edges (e.g., side edges of control gate 307) and over the drain (e.g., drain 317) and the source (e.g., source 317) in the semiconductor substrate (e.g., substrate 301); a first dielectric layer (e.g., tunneling oxide layer 313) extending between the floating gate (e.g., floating gate 311) and the semiconductor substrate (e.g., substrate 301), and a second dielectric layer (e.g., interpoly dielectric layer 309) extending between the floating gate (e.g., floating gate 311) and the control gate (e.g., control gate 307), wherein a same nature of material (see, e.g., paragraph 28) is used for a dielectric layer (e.g., gate dielectric layer 327) extending between a gate (e.g., word gate 325) and the semiconductor substrate (e.g., substrate 301) and the first dielectric layer (e.g., tunneling oxide layer 313) extending between the floating gate (e.g., floating gate 311) and the semiconductor substrate (e.g., substrate 301).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the transistor of Toh within the device of Nazarian in view of Konrath, in order to achieve the expected result of providing additional performance within the device with the inclusion of additional transistor setups for additional memory and circuit capabilities. It also would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the dielectric material (oxide) of Toh within the device of Nazarian in view of Konrath further in view of Toh, as oxide was a well-known material to include within the first dielectric layer at the time of filing the invention, as taught by Toh. Note that the dielectric layer of Nazarian in view of Konrath is oxide, hence the nature of materials are the same.
With regards to the particular range claimed, i.e. 100 nanometers (the same thickness as the second portion of the gate of said at least one capacitive transistor), it is noted that the specification fails to provide teachings about the criticality of the claimed range, and the courts have held that differences in lengths (or ranges thereof) will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such lengths are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph below) of the claimed length ranges, and since Toh teaches a gate width of a 50 nanometer length, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to use these width values within the gate depth extension of Nazarian in view of Konrath into the substrate, in order to achieve the expected result of providing a limited but distinct gate extension depth into the substrate as desired.
CRITICALITY: The specification contains no disclosure of either the critical nature of the claimed length ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Nazarian in view of Konrath further in view of Toh, however, fails to explicitly teach wherein a same nature of material is used for the gate of said at least one capacitive transistor and the floating gate of the at least one planar transistor, while it also fails to teach the dielectric layer having a same thickness as the first dielectric layer.
Chowdhury (see, e.g., fig. 2), in a similar device to Nazarian in view of Konrath further in view of Toh, teaches a gate (e.g., gate 22) is made of polysilicon (see, e.g., paragraph 74 “Examples of suitable gate materials include, but are not limited to, …polysilicon…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the polysilicon of Chowdhury within the gate of Nazarian in view of Konrath and Toh, as polysilicon was a well-known material at the time of filing the invention to include within a gate, as taught by Chowdhury.
Nazarian in view of Konrath further in view of Toh and Chowdhury, however, fails to explicitly teach the floating gate is made of a same nature of material (i.e., polysilicon), while it also fails to teach the dielectric layer having a same thickness as the first dielectric layer.
Müller (see, e.g., fig. 3A), in a similar device to Nazarian in view of Konrath further in view of Toh and Chowdhury, teaches a floating gate (e.g., floating gate 306) comprising polysilicon (see, e.g., paragraph 46 “The floating gate 306 may include any suitable electrically conductive material, e.g.,…polysilicon…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the polysilicon material of Müller within the floating gate of Nazarian in view of Konrath further in view of Toh and Chowdhury, as polysilicon was a well-known material to be included within a floating gate at the time of filing the invention, as taught by Müller.
Nazarian in view of Konrath further in view of Toh, Chowdhury, and Müller, however, fails to teach the dielectric layer having a same thickness as the first dielectric layer.
Huang (see, e.g., fig. 23B), in a similar device to Nazarian in view of Konrath further in view of Toh, Chowdhury, and Müller, teaches a dielectric layer (e.g., select gate dielectric 156) having a same thickness (see, e.g., paragraph 22 “…at least two of the select gate dielectrics 156, floating gate dielectrics 158…the same thickness as one another…”) as a first dielectric layer (e.g., floating gate dielectric 158).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the same thickness configuration of Huang between the dielectric layer and first dielectric layer setup of Nazarian in view of Konrath further in view of Toh, Chowdhury, and Müller, in order to achieve the expected result of providing a uniform geometry between the dielectric layers and gate structures. In addition, the particular thicknesses claimed are an optimization of the dielectric layer to adapt to the general layout of the transistor device, and no new or non-obvious results arise from that particular thickness limitation, other than enabling a consistent dielectric layout onto the substrate, allowing a planar/uniform layout of the gate and dielectric structures across the span of the device.
Regarding claim 5, Konrath (see, e.g., paragraph 26) teaches wherein the dielectric layer (e.g., gate dielectric 104) is an oxide layer (see, e.g., paragraph 26 “The gate dielectric may
include or consist of one layer or a combination of layers, e.g. a layer stack of dielectric layers, for example oxide layers…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the oxide of Konrath within the dielectric layer of Nazarian in view of Konrath further in view of Chowdhury, Toh, Müller, and Huang, as oxide was a well-known material at the time of filing the invention to include within a gate dielectric, as taught by Konrath.
Toh (see, e.g., figs. 3B-3F) teaches the first dielectric layer (e.g., tunneling oxide layer 313) is an oxide layer.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the oxide of Toh within the first dielectric layer of Nazarian in view of Konrath further in view of Chowdhury, Toh, Müller, and Huang, as oxide was a well known material at the time of filing the invention to include within a dielectric layer, as taught by Toh.
Regarding claim 8, Chowdhury (see, e.g., fig. 2) teaches a gate (e.g., gate 22) is made of polysilicon (see, e.g., paragraph 74 “Examples of suitable gate materials include, but are not limited to, …polysilicon…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the polysilicon of Chowdhury within the gate of Nazarian in view of Konrath further in view of Nazarian in view of Konrath further in view of Chowdhury, Toh, Müller, and Huang, as polysilicon was a well-known material at the time of filing the invention to include within a gate, as taught by Chowdhury.
Müller (see, e.g., fig. 3A), in a similar device to Nazarian in view of Konrath further in view of Chowdhury, Toh, Müller, and Huang, teaches a floating gate (e.g., floating gate 306) is made of (see, e.g., paragraph 46 “The floating gate 306 may include any suitable electrically conductive material, e.g.…polysilicon…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the polysilicon material of Müller within the floating gate of Nazarian in view of Konrath further in view of Chowdhury, Toh, Müller, and Huang, as polysilicon was a well-known material to be included within a floating gate at the time of filing the invention, as taught by Müller.
Regarding claim 11, the current embodiment of Nazarian (see, e.g., fig. 4) fails to show wherein said at least one capacitive transistor further comprises two dielectric strips extending completely over lateral borders of the second portion of the gate.
An alternate embodiment of Nazarian, however (see, e.g., fig. 5), teaches wherein a transistor (e.g., deep trench transistor 502) further comprises two dielectric strips (e.g., dielectric spacers 512A + 512B) extending completely over lateral borders of a second portion (see, e.g., gate 511 portion over trench) of a gate (e.g., gate 511).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the dielectric strips of the alternate embodiment of Nazarian (e.g., fig. 5) within the current embodiment of Nazarian (e.g., fig. 4), in order to provide additional dielectric protection between the gate structure and other electronic components or devices, as desired.
Regarding claim 12, the current embodiment of Nazarian (see, e.g., fig. 4) fails to show wherein said at least one capacitive transistor further comprises two dielectric strips extending over lateral borders of the second portion of the gate.
An alternate embodiment of Nazarian, however (see, e.g., fig. 5), teaches wherein a transistor (e.g., deep trench transistor 502) further comprises two dielectric strips (e.g., dielectric spacers 512A + 512B) extending over lateral borders of a second portion (see, e.g., gate 511 portion over trench) of a gate (e.g., gate 511) and over a semiconductor substrate (e.g., substrate 501).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the dielectric strips of the alternate embodiment of Nazarian (e.g., fig. 5) within the current embodiment of Nazarian (e.g., fig. 4), in order to provide additional dielectric protection between the gate structure and other electronic components or devices, as desired.
Regarding claim 14, Toh (see, e.g., fig. 3B) teaches wherein a portion of the floating gate (e.g., floating gate 311) extends beyond (e.g., note that floating gate 311 and control gate 307 bodies are distinct and do not have overlapping perimeters) on an outer perimeter of the control gate (e.g., control gate 307).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the non-overlapping perimeter extension of Toh within the configuration of Nazarian in view of Konrath further in view of Chowdhury, Toh, Müller, and Huang, in order to allow distinct yet functional control gate and floating gate bodies within the planar transistor.
Regarding claim 15, Nazarian (see, e.g., fig. 4) shows wherein a part of the first portion (e.g., gate portion extending into substrate 410) of the gate (e.g., gate 408) of the capacitive transistor (e.g., transistor 406 + paragraph 41 “…deep trench transistor employed for low capacitor 406…” or paragraph 64 “…transistor 406 (e.g., a lower capacitor)”) extends beyond an outer perimeter (see, e.g., annotated fig. 1 below) of the second portion (e.g., expanded portion over substrate 410) of the gate (e.g., gate 408) of the capacitive transistor (e.g., transistor 406 + paragraph 41 “…deep trench transistor employed for low capacitor 406…” or paragraph 64 “…transistor 406 (e.g., a lower capacitor)”).
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Annotated Fig. 1
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Nazarian in view of Konrath further in view of Toh, Chowdhury, Müller, Huang, and Lee (US 20220231028 A1).
Regarding claim 2, Nazarian in view of Konrath further in view of Toh, Chowdhury, Müller, and Huang fails to teach wherein the first portion of the gate of said at least one capacitive transistor extends in depth in the substrate over a distance comprised between 300 and 1200 nanometers.
Lee (see, e.g., fig. 4A), in a similar device to Nazarian in view of Konrath further in view of Toh, Chowdhury, Müller, and Huang, teaches a gate structure (e.g., conductive layer 203 of gate trench 103) extends in depth (e.g., gate trench 103) into a substrate (e.g., substrate 100), wherein the depth of the gate structure (e.g.., gate structure 203) is approximately 300 nm (see, e.g., claim 5 “…a depth of the gate trench is 100 nm to 300 nm…” – note that conductive layer 203 fills out a substantially large part of the gate trench, so the length is substantially close to 300 nm).
With regards to the particular range claimed, i.e. 300 nanometers to 1200 nanometers, it is noted that the specification fails to provide teachings about the criticality of the claimed range, and the courts have held that differences in lengths (or ranges thereof) will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such lengths are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph below) of the claimed length ranges, and since Lee teaches a gate structure substantially close to the 300 nanometer length, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to use these length values within the gate depth extension of Nazarian in view of Konrath further in view of Toh, Chowdhury, Müller, and Huang into the substrate, in order to achieve the expected result of providing a limited but distinct gate extension depth into the substrate as desired.
CRITICALITY: The specification contains no disclosure of either the critical nature of the claimed length ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 3, Nazarian (see, e.g., fig. 4) shows wherein the first portion (e.g., gate portion extending into substrate 410) of the gate (e.g., gate 408) of said at least one capacitive transistor (e.g., transistor 406 + paragraphs 41 or 64) has width comprised between 100 nanometers and 300 nanometers (see, e.g., paragraph 64 “the gate 408 can be a low-profile gate having a width substantially equal to a width or a p-well…In some embodiments, the width of the p-well (and approximate width of gate 408) can be about 100 nanometers…”).
Regarding claim 4, Nazarian (see, e.g., fig. 4) shows the second portion (e.g., expanded portion over substrate 410) of the gate (e.g., gate 408) of said at least one capacitive transistor (e.g., transistor 406 + paragraph 41 “…deep trench transistor employed for low capacitor 406…” or paragraph 64 “…transistor 406 (e.g., a lower capacitor)”) has a thickness substantially comprised between 100 nanometers and 200 nanometers (see, e.g., paragraph 64 “In some embodiments, the width of the p-well (and approximate width of gate 408) can be about 100 nanometers…”).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Nazarian in view of Konrath further in view of Toh, Chowdhury, Müller, Huang, and Wang (US 20220271131 A1).
Regarding claim 6, Nazarian in view of Konrath further in view of Toh, Chowdhury, Müller, and Huang fails to teach wherein the dielectric layer of said at least one capacitive transistor and the first dielectric layer of the at least one planar transistor has a thickness comprised between 8 nanometers and 40 nanometers.
Wang (see, e.g., fig. 4), in a similar device to Nazarian in view of Konrath further in view of Toh, Chowdhury, Müller, and Huang, teaches a dielectric layer (e.g., gate oxide layer 111) has a thickness comprised between 8 nanometers and 40 nanometers (see, e.g., paragraph 35 “…the thickness of the first gate oxide layer 111 is 3 nm-10nm…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the thickness profile of Wang within the dielectric layer of Nazarian in view of Konrath further in view of Toh, Chowdhury, Müller, and Huang, in order to achieve the expected result of providing a thin gate oxide layer profile, limiting the cost of manufacturing, while still maintaining the necessary gate oxide properties.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Nazarian in view of Konrath further in view of Toh, Chowdhury, Müller, Huang, and Kansagra (US 20240088014 A1).
Regarding claim 7, Nazarian in view of Konrath further in view of Toh, Chowdhury, Müller, and Huang fails to teach a first contact connected to the second portion of the gate of said at least one capacitive transistor and a second contact connected to the source or to the drain of said at least one capacitive transistor.
Kansagra (see, e.g., fig. 1), in a similar device to Nazarian in view of Konrath further in view of Toh, Chowdhury, Müller, and Huang, teaches a first contact (e.g., gate contact 135) connected to a gate (e.g., gate 115) and a second contact (e.g., first source/drain contact 130-1) connected to the source or to the drain (e.g., source/drain 120-1).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the gate contact and source/drain contact of Kansagra onto the gate and source or drain of Nazarian in view of Konrath further in view of Toh, Chowdhury, Müller, and Huang, in order to achieve the expected result of providing direct connection to the source/drain region for electrical current flow, as well as providing gate flow and electrical connectivity to other portions of the device as necessary.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Nazarian in view of Konrath further in view of Toh, Chowdhury, Müller, Huang and Jacek (EP 2880688 B1).
Regarding claim 9, Nazarian in view of Konrath further in view of Toh, Chowdhury, Müller, and Huang fails to teach comprising several capacitive transistors, the second portion of the gate of capacitive transistor being common for said several capacitive transistors.
Jacek (see, e.g., fig. 8), in a similar device to Nazarian in view of Konrath further in view of Toh, Chowdhury, Müller, and Huang, teaches a shared portion (e.g., upper polysilicon material 810) among numerous gate trench structure (e.g., trenches 806).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include numerous trench and shared gate portion configuration of Jacek within the device of Nazarian in view of Konrath further in view of Toh, Chowdhury, Müller, and Huang, in order to expand the gate configuration and connect the vertical channel structure within the substrate, enhancing current density within the device.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Nazarian in view of Konrath further in view of Chowdhury, Toh, Müller, Huang, Jacek and Itokazu (US 20220085216 A1).
Regarding claim 10, Jacek (see, e.g., fig. 8) teaches wherein first portions (e.g., polysilicon material 810 within trenches 806) of the gates (e.g., polysilicon material 810) extend in depth (see, e.g., fig. 8) and are spaced apart from each other.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the spacing configuration of Jacek with the device to Nazarian in view of Konrath further in view of Toh, Chowdhury, Müller, and Huang, in order to in order to expand the gate configuration and connect the vertical channel structure within the substrate, enhancing current density within the device.
Nazarian in view of Konrath further in view of Chowdhury, Toh, Müller, Huang, and Jacek, however, fails to teach the trenches are spaced apart from each other by a distance comprised between .1 micrometers and 1.5 micrometers.
Itokazu (see, e.g., figs. 1A-1B), in a similar device to Nazarian in view of Konrath further in view of Toh, Chowdhury, Müller, Huang, and Jacek, teaches gate trenches (e.g., trenches of electrodes 30) are spaced apart from each other by a distance substantially close to 1.5 micrometers (see, e.g., paragraph 27 “…the spacing between the adjacent trenches AT…are 1.6 micrometers…”).
With regards to the particular spacing distance claimed, i.e. .1 micrometers and 1.5 micrometers, it is noted that the specification fails to provide teachings about the criticality of the claimed range, and the courts have held that differences in lengths (or ranges thereof) will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such lengths are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph below) of the claimed length ranges, and since Itokazu teaches a spacing of 1.6 micrometers, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to slightly modify these spacing values between the gate trenches of Nazarian in view of Konrath further in view of Toh, Chowdhury, Müller, Huang, and Jacek, in order to provide additional spacing or connectivity requirements as desired within the device.
CRITICALITY: The specification contains no disclosure of either the critical nature of the claimed distance ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Allowable Subject Matter
Claims 16-27 are allowed.
Regarding claim 16, Nazarian (US 20160268341 A1) in view of Konrath (US 20200066857 A1) further in view of Toh (US 20160268387 A1) teaches most aspects of the method for manufacturing the integrated circuit.
However, Nazarian in view of Konrath further in view of Toh fails to disclose or suggest wherein manufacturing comprises: forming the trench in the semiconductor substrate; depositing a layer of dielectric material in the trench and over the semiconductor substrate, wherein said layer of dielectric material provides both the dielectric layer in the trench for the at least one capacitive transistor and the first dielectric layer for the at least one planar transistor, the dielectric layer and the first dielectric layer having a same thickness; depositing a layer of conductive material over the layer of dielectric material in the trench and over the semiconductor substrate, wherein said layer of conductive material provides both the gate in the trench for the at least one capacitive transistor and the floating gate for the at least one planar transistor, second portion of the gate and the floating gate having a same thickness; and removing portions of the layer of dielectric material and layer of conductive material over the semiconductor substrate to define the second portion of the gate for the at least one planar transistor and the floating gate for the at least one planar transistor.
34. Therefore, the above limitations in the entirety of the claim are neither anticipated nor
rendered obvious over the prior art of record.
35. Any comments considered necessary by applicant must be submitted no later than the
payment of the issue fee, and, to avoid processing delays, should preferably accompany the
issue fee. Such admissions should be clearly labeled “Comments on Statement of Reasons
for Allowance”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THOMAS WILSON MCCOY whose telephone number is (571) 272-0282. The examiner can normally be reached 9:30-6:30 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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