DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 12/01/2023, 01/09/2024 and 01/23/2024 were filed before the first action on the merits. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 8-10 and 12-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (2019/0103304).
Re claim 8, Lin teaches a device (Figs. 30A-B) comprising: a first fin structure (52, “left side” of wide element 60”) comprising a first semiconductor fin (52, “left”) and a second semiconductor fin (52, “middle”); a first source/drain region (82) in the first semiconductor fin (52, “left”) and the second semiconductor fin (52, “middle”); a dielectric fin (60, “narrow”) adjacent the first source/drain region (82) and the first fin structure (52, “left side” of wide element 60”); a first isolation region (58) between the dielectric fin (60, “narrow”) and the first fin structure (52, “left side” of wide element 60”), the first isolation region (58) having a first height (Fig. 30B); and a second isolation region (204) between the first semiconductor fin (52, “left”) and the second semiconductor fin (52, “right”), the second isolation region (204) having a second height (Fig. 30B), the second height less than the first height (Fig. 30B).
Re claim 9, Lin teaches the device of claim 8, further comprising: a second fin structure (52, “immediate left and right sides of wide element 60”) comprising a third semiconductor fin (52, “immediate left side of wide element 60”) and a fourth semiconductor fin (52, “immediate right side of wide element 60”), the first isolation region (58) being between the dielectric fin (60, “narrow”) and the second fin structure (52, “immediate left and right sides of wide element 60”).
Re claim 10, Lin teaches the device of claim 9, further comprising: a second source/drain region (82, “immediate left and right sides of wide element 60”) in the third semiconductor fin (52, “immediate left side of wide element 60”) and the fourth semiconductor fin (52, “immediate right side of wide element 60”), the dielectric fin (60, “narrow”) separating the first source/drain region (82) from the second source/drain region (82). Re claim 12, Lin teaches the device of claim 8, wherein a top surface of the first source/drain region (82) is disposed above a top surface (Fig. 30B) of the dielectric fin (60, “narrow”).
Re claim 13, Lin teaches the device of claim 8, wherein the dielectric fin (60, “narrow”) comprises a void (61).
Re claim 14, Lin teaches the device of claim 8, further comprising: a first fin spacer (56) between the dielectric fin (60, “narrow”) and the first fin structure (52, “left side” of wide element 60”), the first fin spacer (56) having a first height (“height on either side of element 60 “narrow”); and a second fin spacer (56) between the first semiconductor fin (52, “left”) and the second semiconductor fin (52, “middle”), the second fin spacer (56) having a second height (“height below element 60 “narrow”).
Claim(s) 15-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (2019/0103304).
Re claim 15, Lin teaches a method (Figs. 1-30B) comprising: forming a first fin structure (52, “left side” of wide element 60”) and a second fin structure (52, “immediate left and right sides of wide element 60”) extending from a substrate (50), the first fin structure comprising first semiconductor fins (52, “left and middle”), the second fin structure comprising second semiconductor fins (52, “immediate left and right sides of wide element 60”); forming an insulation material (56, 60) around the first fin structure (52, “left side” of wide element 60”) and the second fin structure (52, “immediate left and right sides of wide element 60”), a first portion of the insulation material (56) disposed in a first trench between the first semiconductor fins (Figs. 30A-B), a second portion (56) of the insulation material (56) disposed in a second trench between the second semiconductor fins (52, “immediate left and right sides of wide element 60”), a third portion of the insulation material (60) disposed in a third trench between the first fin structure and the second fin structure (Figs. 29-30A-B); and recessing the first portion, the second portion, and the third portion of the insulation material (56, 60) to form a first isolation region (56, “sidewalls”), a second isolation region (56, “bottom portion”), and a third isolation region (60, Fig. 29), respectively, the first portion and the second portion (56) of the insulation material recessed by a greater depth (Fig. 29) than the third portion (60) of the insulation material (56, 60).
Re claim 16, Lin teaches the method of claim 15, wherein the insulation material (56, 60) comprises silicon oxide [60], and recessing the insulation material comprises: performing a dry etch with hydrofluoric acid and ammonia while generating a plasma [27-29].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (2020/0105583) in view of the following reasons.
Re claim 1, Wang teaches a device (Figs. 21A-B) comprising: a first semiconductor fin (52, “left side”, “device 50A”) extending from a substrate (50); a second semiconductor fin (52, “left side”, “device 50B”) extending from the substrate (50); a dielectric fin (61, “device 50B”) over the substrate (50), the second semiconductor fin (52, “left side”, “device 50B”) disposed between the first semiconductor fin (52, “left side”, “device 50A”) and the dielectric fin (61, “device 50B”); a first isolation region (56) between the first semiconductor fin (52, “left side”, “device 50A”) and the second semiconductor fin (52, “left side”, “device 50B”); and a second isolation region (64) between the second semiconductor fin (52, “left side”, “device 50B”) and the dielectric fin (61, “device 50B”), a top surface (Fig. 21A) of the second isolation region (64) disposed above a top surface (Fig. 21A) of the first isolation region (56). Wang does not explicitly teach a bottom surface of the second isolation region disposed below a bottom surface of the first isolation region. However, Applicant has not shown wherein a bottom surface of the second isolation region disposed below a bottom surface of the first isolation region has a specific, disclosed criticality that is unexpected and would not have been determined through routine experimentation of one having ordinary skill in the art. Therefore, it would have been obvious to adjust the surface of the isolation layers so as to customize, optimize, or otherwise meet customer space and design requirements, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Re claim 2, Wang teaches the device of claim 1, wherein a top surface (Fig. 21A) of the dielectric fin (61) is level with a top surface (Fig. 21A) of the first semiconductor fin (52, “left side”, “device 50A”) and with a top surface (Fig. 21A) of the second semiconductor fin (52, “left side”, “device 50B”).
Re claim 3, Wang teaches the device of claim 1, further comprising: a gate structure (96) on the first isolation region (56), the gate structure extending (Fig. 21A) between the first semiconductor fin (52, “left side”, “device 50A”) and the second semiconductor fin (52, “left side”, “device 50B”).
Re claim 4, Wang teaches the device of claim 1, further comprising: a gate structure (96) on the second isolation region (64), the gate structure extending (Fig. 21A) between the second semiconductor fin (52, “left side”, “device 50B”) and the dielectric fin (61, “device 50B”). Re claim 6, Wang teaches the device of claim 1, wherein the top surface of the first isolation region (56) is flat (Fig. 21A), and the top surface of the second isolation region (64) is flat (Fig. 21A).
Allowable Subject Matter
Claims 5, 7, 11 and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Re claim 5, Wang teaches the device of claim 1, yet remains explicitly silent to wherein the second isolation region has a first portion and a second portion, the first portion disposed between the second semiconductor fin and the dielectric fin, the second portion disposed between the substrate and the dielectric fin. Re claim 7, Wang teaches the device of claim 1, yet remains explicitly silent to wherein the top surface of the first isolation region is concave, and the top surface of the second isolation region is concave. Re claim 11, Lin teaches the device of claim 9, yet remains explicitly silent to wherein the first fin structure has a different quantity of semiconductor fins than the second fin structure.
Re claim 17, Lin teaches the method of claim 15, wherein the third trench is deeper than the first trench and the second trench.
Re claim 18, Lin teaches the method of claim 15, yet remains explicitly silent to wherein the insulation material completely fills the first trench and the second trench, and the insulation material partially fills the third trench.
Re claim 19, Lin teaches the method of claim 15, yet remains explicitly silent to further comprising: depositing a dielectric layer in portions of the third trench unoccupied by the insulation material.
Re claim 20, Lin teaches the method of claim 15, yet remains explicitly silent to further comprising: before recessing the insulation material, planarizing the insulation material, the first fin structure, and the second fin structure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM S BOWEN whose telephone number is (571)272-3984. The examiner can normally be reached M-F 9-5.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/ADAM S BOWEN/Examiner, Art Unit 2897