DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/06/2026 has been entered.
Response to Amendments
3. The Amendments filed July 6th, 2026 in response to the Final Office Action mailed 04/29/2026 are noted.
Applicant’s amendment(s) to the claims have overcome the 35 U.S.C. § 112 rejection(s)
previously set forth in the Non-Final Office Action mailed 04/29/2026, so the 35 U.S.C. § 112
rejection(s) have been withdrawn.
Applicant’s amendment(s) to the Drawings have overcome the Objection(s) to the Drawings
previously set forth in the Non-Final Office Action mailed 04/29/2026, so the Drawing Objection(s) have been withdrawn.
Applicant’s amendments to the claims are noted.
4. Claims 6-8 are now canceled; Claim 1 is amended; Claims 1-5 remain pending in the application.
5. Claims 1-5 have been fully considered in examination.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nishizawa (U.S. Patent No 5,323,028) (of record).
Regarding claim 1, Nishizawa teaches a silicon controlled rectifier (1) fig. 3 [col 8, lines 58-67] comprising:
a first P region (21) fig. 3 [col 9, lines 1-2, lines 49-50] coupled to an anode (211) fig. 3 [col 9, lines 16-18, 49-50];
an N- region (22) fig. 3 [col 9, lines 1-2] adjacent the first P region (21);
a second P region (51) fig. 3 [col 9, lines 1-5] adjacent the N- region (22), wherein the N- region (22) is (vertically) sandwiched between the first P region (21) and the second P region (51); and
a plurality of N+ regions (23, 52) fig. 3 [col 10, lines 25-27] disposed within the second P region (51), wherein:
a first N+ region (52) fig. 3 [col 10, lines 25-27] of the plurality of N+ regions (23, 52) is coupled to (in mechanical contact with) a cathode (231) fig. 3 [col 9, lines 16-18] (see annotated fig. 3 below); and
a second N+ region (23) fig. 3 [col 10, lines 25-27] of the plurality of N+ regions (23, 52) is coupled to a gate (251) fig. 3 [col 9, line 45] such that the silicon controlled rectifier (1) is turned on by a negative gate bias (Vgk becomes negative [col 9, lines 19-54], [col 9, lines 40-44] gate area 31 and cathode area 23 become forward-biased, which means that large current can now flow from "A" to "K") remains inactive with a positive gate bias (positive gate voltage less than threshold value) [col 9, lines 19-54] (see annotated fig. 3 of Nishizawa below).
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Annotated fig. 3 of Nishizawa
Regarding claim 2, Nishizawa teaches the silicon controlled rectifier (1) fig. 3 [col 8, lines 58-67] of claim 1. Nishizawa also teaches further comprising:
a first junction (interface of 21 and 22) between the first P region (21) fig. 3 [col 9, lines 1-2, lines 49-50] and the N- region (22) fig. 3 [col 9, lines 1-2].
Regarding claim 3, Nishizawa teaches the silicon controlled rectifier (1) fig. 3 [col 8, lines 58-67] of claim 2. Nishizawa also teaches further comprising:
a second junction (interface of 22 and 51) between the N- region (22) fig. 3 [col 9, lines 1-2] and the second P region (51) fig. 3 [col 9, lines 1-5].
Regarding claim 4, Nishizawa teaches the silicon controlled rectifier (1) fig. 3 [col 8, lines 58-67] of claim 3. Nishizawa also teaches further comprising:
a third junction (interface of 51 and 52) between the second P region (51) fig. 3 [col 9, lines 1-5] and the plurality of N+ regions (23, 52) fig. 3 [col 10, lines 25-27].
Regarding claim 5, Nishizawa teaches the silicon controlled rectifier (1) fig. 3 [col 8, lines 58-67] of claim 4. Nishizawa also teaches further comprising:
a fourth junction (interface of 23 and 51) between the second N+ region (23) fig. 3 [col 10, lines 25-27] and the second P region (51) fig. 3 [col 9, lines 1-5].
Response to Arguments
Applicant's arguments filed 07/06/2026 have been fully considered but they are not persuasive:
With respect to Applicant’s argument(s) that “Independent Claim 1 requires, inter alia, that "a second N+ region of the plurality of N+ regions is coupled to a gate such that the silicon controlled rectifier is turned on by a negative gate bias” and that:
Nishizawa fails to teach or suggest this limitation for two distinct reasons:
“First, Nishizawa does not teach an N+ region coupled to a gate. As clearly depicted in Figure 3 of Nishizawa, the element identified by the Examiner as the gate (251) is a Metal-Oxide-Semiconductor (MOS) gate electrode. This gate electrode (251) is physically separated and electrically insulated from the underlying N+ region (23) by a dielectric oxide layer (26). Because Nishizawa utilizes an insulated gate structure, the gate (251) is not "coupled to" the N+ region (23) in a manner capable of injecting electrons across a junction as required by the claims” it is noted that the claim merely requires that the N+ region be “coupled to a gate” --- it is Examiner’s view that Applicant appears to be relying on (or requiring) a narrow interpretation of "coupled" in the limitation, "a second N+ region...is coupled to a gate...". Broadly, the N+ region 23 and the gate 251 of the same transistor of Nishizawa are coupled to each other in that they electrically interact during transistor device operation(s) [col 9, lines 45-55 Nishizawa].
In discussing physical separation in their Remarks in relation to the term “coupled”, Applicant is apparently asserting that “coupling” as presently claimed requires direct, physical contact/coupling between the aforementioned components; one of ordinary skill in the art would recognize that there are a variety of manners in which two objects may be reasonably considered to be “coupled” with one another without direct, physical contact between the two. However, if claim 1 were amended to recite, "a second N+ region...in direct contact with a gate...", Examiner agrees that this would overcome the rejection of record in the manner reflected in the Remarks.
` With respect to Applicant’s argument(s) that “Second, the Examiner's assertion that Nishizawa is "turned on by a negative gate bias" relies on a fundamental misreading of the reference. The Examiner conflates the internal node voltage (Vgk) with the actual bias applied to the gate terminal (251)… While Nishizawa explains that the internal voltage Vgk becomes negative as a result of this operation, the bias physically applied to the gate electrode 251 to trigger the device is unequivocally positive. This directly contradicts Claim 1, which requires the rectifier itself to be "turned on by a negative gate bias” – likewise, it appears that Applicant is requiring a narrower interpretation in their Remarks than what is claimed.
With respect to the underlined portions of Applicant’s argument(s) above, claim 1 does not in any way require "a negative gate bias" to be "the" gate bias applied to gate terminal (251). Vgk is "a negative gate bias" that turns on the SCR (e.g., see Col. 9, lines 40-44, i.e., as Vgk become negative, gate area 31 and cathode area 23 become forward-biased, which means that large current can now flow from "A" to "K"). Thus, because claim 1 does not require that “a negative bias” specifically be “physically applied” at the gate itself – as Applicant asserts in their Remarks – and the Vgk becoming negative is an essential aspect of the SCR becoming forward biased [see col 9, lines 40-44 Nishizawa], Examiner maintains the rejection of record on the basis that claim 1 remains broad enough for the negative Vgk associated with the SCR becoming ‘on’ still reads on the claimed ‘negative gate bias’.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
References made available on the PTO-892 form (of record) are considered relevant to the present disclosure because they all feature silicon-controlled rectifiers with N-type region(s) coupled to gates.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN AYERS WINTERS whose telephone number is (571)270-3308. The examiner can normally be reached Monday - Friday 10:30 am - 7:00 pm (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 07/23/2026
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