DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 15-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (PG Pub. No. US 2021/0028112 A1).
Regarding claim 15, Kim teaches a semiconductor device (fig. 2 among others) comprising:
a first transistor and a second transistor (¶ 0026 & fig. 2: plurality of MOS transistors) electrically interposed between a front side interconnect structure and a back side interconnect structure (¶¶ 0045, 0048 & fig. 2: MOS transistors interposed between interconnect structures ML1 and ML2), the back side interconnect structure comprising a power rail (¶ 0049: ML2 comprises power lines), wherein the back side interconnect structure is configured to electrically couple the power rail to an external power source (implicit: ML2 suitable for connecting power lines to a non-illustrated power source);
a first via (¶ 0046 & fig. 2: first V1) electrically coupling the first transistor to the front side interconnect structure (fig. 2: first V1 electrically couples first MOS transistor to ML1);
a second via (second V1) electrically coupling the second transistor to the front side interconnect structure (fig. 2: second V1 electrically couples second MOS transistor to ML1);
a third via (¶ 0051: first V2) electrically coupling the first transistor to the back side interconnect structure (fig. 2: V2 electrically couples first MOS transistor to ML2); and
a fourth via (second V2) electrically coupling the second transistor to the back side interconnect structure (fig. 2: second V2 electrically couples second MOS transistor to ML2).
Regarding claim 16, Kim teaches the semiconductor device of claim 15, wherein the first transistor and the second transistor are electrically connected to one another through the front side interconnect structure and through the back side interconnect structure (fig. 2: first and second MOS transistors connected together through ML1 and ML2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Beyne et al. (PG Pub. No. US 2018/0145030 A1) in view of Sasaki et al. (PG Pub. No. US 2020/0365509 A1).
Regarding claim 1, Beyne teaches a semiconductor device (fig. 9 among others) comprising:
a power rail (¶ 0058: power line 68) embedded in a first dielectric layer (¶ 0019);
a conductive signal line (¶ 0059: 73) embedded in the first dielectric layer (figs. 7, 9: 73 embedded in dielectric layer of PDN 12);
a second dielectric layer (¶¶ 0051, 0057: 31 and/or 55) disposed over the first dielectric layer (fig. 9: 31/55 disposed over 12);
a first backside via (¶ 0058: 66) disposed over and electrically connected to the power rail (fig. 9: 66 over and electrically connected to 68);
a first transistor (device in left region of figs. 7, 9) disposed over and electrically connected to the first backside via (¶ 0047 & figs. 7, 9: device over 66, and at least electrically connected to 66 through elements 60/62/16/8);
a first gate electrode of the first transistor (¶¶ 0046, 0052: each transistor comprises gate strips 1);
a second backside via (¶ 0059: 72) disposed over and electrically connected to the conductive signal line (fig. 9: 72 disposed over and electrically connected to 73); and
a second transistor (second device of figs. 7, 9 including interconnect 71) disposed over and electrically connected to the second backside via (fig. 9: 71 disposed over and electrically connected to 71 through element 70).
Beyne fails to explicitly teach a first gate contact disposed over and electrically connected to the first gate electrode.
Sasaki teaches a semiconductor device (figs. 1-2 among others) including a first gate contact (¶ 0039: GC) disposed over and electrically connected to a first gate electrode (fig. 2C: GC disposed over and electrically connected to gate electrode GE).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor device of Beyne to include a gate contact, as a means to provide an electrical signal or voltage the gate electrode during device operation.
Regarding claim 2, Beyne in view of Sasaki teaches the semiconductor device of claim 1, comprising a first backside via (Beyne, 66) and a first source/drain region of the first transistor (Beyne, ¶ 0046: each transistor comprises source/drain areas 2).
Beyne in view of Sasaki as applied to claim 1 does not explicitly teach wherein the first backside via (Beyne, 66) is electrically connected to a first source/drain region of the first transistor.
However, Sasaki does teach a first backside via (¶ 0042: UVI) electrically connected to a first source/drain region (¶ 0026: SD1) of a first transistor (¶ 0024 & fig. 2B among others: UVI electrically connected to SD1 of a transistor in region PR).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to electrically connect the first backside via of Beyne in view of Sasaki with the first transistor source/drain region, as a means to provide voltage, ground and/or signals to a source/drain region of the first transistor, enabling and/or ensuring proper circuit functionality.
Regarding claim 3, Beyne in view of Sasaki teaches the semiconductor device of claim 1, comprising a second backside via (Beyne, 72) and a second source/drain region of the second transistor (Beyne, ¶ 0046: each transistor comprises source/drain areas 2).
Beyne in view of Sasaki as applied to claim 1 above does not explicitly teach wherein the second backside via is electrically connected to a second source/drain region of the second transistor.
However, Sasaki does teach a second backside via (¶ 0042: UVI) electrically connected to a second source/drain region (¶ 0026: SD2) of a second transistor (¶ 0024 & fig. 2B among others: UVI electrically connected to SD2 of a transistor in region NR).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to electrically connect the second backside via of Beyne in view of Sasaki with the second transistor source/drain region, as a means to provide voltage, ground and/or signals to a source/drain region of the second transistor, enabling and/or ensuring proper circuit functionality.
Regarding claim 4, Beyne in view of Sasaki teaches the semiconductor device of claim 1, comprising a conductive signal line (Beyne, 73) and a third transistor (Beyne, fig. 9: device comprises at least three transistors).
Beyne in view of Sasaki as applied to claim 1 above does not explicitly teach the semiconductor device further comprising:
a third backside via disposed over and electrically connected to the conductive signal line; and
a third transistor disposed over and electrically connected to the third backside via.
However, Sasaki does teach a semiconductor device comprising:
a third backside via (¶¶ 0039, 0042: GC and/or UVI) disposed over and electrically connected to a conductive signal line (fig. 2C: GC/UVI disposed over and electrically connected to UML1 and/or UML2; since UML1 and UML2 are configured to conduct electrical signals such as voltage, they meet the broadest reasonable interpretation of “conductive signal line”); and
a third transistor (¶ 0018: additional MOSFET in region NR or PR) disposed over and electrically connected to the third backside via (fig. 2C: NR/PR transistors disposed over and electrically connected to GC/UVI).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the device of Beyne in view of Sasaki with a third backside via electrically connected to the third transistor, as a means to provide voltage, ground and/or signals to a gate region of the third transistor, enabling and/or ensuring proper circuit functionality.
Regarding claim 5, Beyne in view of Sasaki teaches the semiconductor device of claim 4, comprising a second dielectric layer (Beyne, 31/55) and a conductive signal line (Beyne, 73).
Beyne in view of Sasaki fails to explicitly teach the semiconductor device further comprising:
a third via embedded in the second dielectric layer, the third via disposed over and electrically connected to the conductive signal line; and
a third conductive line electrically coupling the third via and the third backside via.
However, Sasaki does teach a semiconductor device including
a third via (¶ 0042: UVI) embedded in a second dielectric layer (fig. 2B: UVI embedded in dielectric layer UIL3), the third via disposed over and electrically connected to a conductive signal line (fig. 2B: UVI disposed over and electrically connected to UML2; since UML2 is configured to conduct electrical signals such as voltage, the broadest reasonable interpretation of “conductive signal line” is met); and
a third conductive line (¶ 0042: UML1) electrically coupling the third via and a third backside via (fig. 2B: UML1 electrically connects UVI in UIL3 to UVI in UIL4).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the device of Beyne in view of Sasaki with a third via and a third conductive line, as a means to provide voltage, ground and/or signals to a source/drain region of transistor circuit elements, enabling and/or ensuring proper circuit functionality.
Claims 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Beyne in view of Sasaki as applied to claim 4 above, and further in view of Huynh Bao et al. (PG Pub. No. US 2018/0174642 A1, hereinafter referenced as ‘Bao’).
Regarding claim 6, Beyne in view of Sasaki teaches the semiconductor device of claim 4, comprising a source/drain region (Beyne, 2) of a first transistor and a gate electrode (Beyne, 1) of a third transistor (fig. 2 among others: a first transistor comprises a first source/drain region, and a third transistor comprises a gate strip).
Beyne in view of Sasaki does not teach wherein the source/drain region of the first transistor is electrically connected to the gate electrode of the third transistor.
Bao teaches a semiconductor device (fig. 1 among others), wherein a source/drain region of a first transistor is electrically connected to a gate electrode of a third transistor (¶ 0077 & fig. 1: source/drain of PD1 electrically connected to a gate electrode of PD2).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor device of Beyne in view of Sasaki with the connectivity of Bao, as a means to provide circuits such as a memory cell and/or an inverter (Bao, ¶ 0075), improving device functionality.
Regarding claim 7, Beyne in view of Sasaki teaches the semiconductor device of claim 4, comprising a source/drain region (Beyne, 2) of a first transistor and a source/drain region (Beyne, 2) of a third transistor (fig. 2 among others: a first and third transistors each comprises source/drain regions).
Beyne in view of Sasaki does not teach wherein a source/drain region of the first transistor is electrically connected to a source/drain region of the third transistor.
Bao teaches a semiconductor device (fig. 1 among others), wherein a source/drain region of a first transistor is electrically connected to a source/drain region of a third transistor (¶ 0077 & fig. 1: source/drain of PD1 electrically connected to a source/drain of PU1).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor device of Beyne in view of Sasaki with the connectivity of Bao, as a means to provide circuits such as a memory cell and/or an inverter (Bao, ¶ 0075), improving device functionality.
Regarding claim 8, Beyne in view of Sasaki and Bao teaches the semiconductor device of claim 7, wherein the source/drain region of the first transistor and the source/drain region of the third transistor are on opposite sides of the conductive signal line (Bao, fig. 1: source/drains of PD1 and PU1 are arranged on opposite sides of signal line QB).
Claims 9-14 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Sasaki.
Regarding claim 9, Kim teaches a semiconductor device (figs. 1-2 among others) comprising:
a first transistor and a second transistor (¶ 0026 & figs. 1-2: left and right transistors in active well region(s)) disposed over a first interconnect structure (figs. 1-2: transistors disposed over wiring structure ML1);
a first via (¶ 0046: first V1) disposed over and electrically connected to the first transistor (fig. 2: first V1 electrically connected to a portion of left transistor);
a second via (second V1) disposed over and electrically connected to the second transistor (fig. 2: second V1 electrically connected to a portion of right transistor); and
a second interconnect structure (¶ 0048: ML2) disposed over the first transistor and the second transistor (fig. 2: ML2 disposed over transistor structures), the second interconnect structure comprising:
a first conductive line (¶ 0051: first M2) embedded in a first dielectric layer (fig. 2: M2 embedded in dielectric layer 272), the first conductive line electrically connected to the first via (fig. 2: M2 electrically connected to first V1);
a second conductive line (¶ 0051: second M2) embedded in the first dielectric layer (fig. 2: second M2 embedded in 272), the second conductive line electrically connected to the second via (fig. 2: second M2 electrically connected to second V1);
a second dielectric layer (¶ 0051: 275) disposed over the first dielectric layer (fig. 2: 275 disposed over 272);
a power rail embedded in the second dielectric layer (¶ 0049: power lines included in wiring portion ML2); and
a conductive signal line embedded in the second dielectric layer (¶ 0049: signal lines included in ML2).
Kim does not explicitly teach the power rail electrically connected to the first conductive line, or the conductive signal line electrically connected to the second conductive line.
Sasaki teaches a semiconductor device (figs. 2A-2C among others) including a power rail (¶ 0020: POR1) electrically connected to a first conductive line (¶ 0045 & fig. 2B: POR1 electrically connected to LML1), and a conductive signal line (¶ 0020: POR2; since POR is configured to conduct electrical signals such as voltage, the broadest reasonable interpretation of “conductive signal line” is met) electrically connected to a second conductive line (fig. 2B: POR2 electrically connected to second portion of LML1).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor device of Kim with the connectivity of Sasaki, as a means to provide power and/or signals to each of the first and second transistors, enabling finctionality of the transistors in circuits such as logic, memory, and/or hybrid circuits (Kim, ¶ 0003 & Sasaki, ¶ 0003).
Regarding claims 10-11, Kim in view of Sasaki teaches the semiconductor device of claim 9, including a first dielectric layer (Kim, 272) and a conductive signal line (Kim, second M2).
Kim in view of Sasaki as applied to claim 9 above does not teach the further comprising:
a third transistor;
a third via disposed over and electrically connected to the third transistor;
a third conductive line embedded in the first dielectric layer, the third conductive line electrically connected to the conductive signal line;
a fourth transistor;
a fourth via disposed over and electrically connected to the fourth transistor; and
a fourth conductive line embedded in the first dielectric layer, the fourth conductive line electrically connected to the conductive signal line.
However, Sasaki does teach a semiconductor device including:
a third transistor (¶ 0018 & figs. 2A-2C: at least three transistors);
a third via (¶ 0045 & figs. 2A-2C: LVI) disposed over and electrically connected to the third transistor (fig. 2B: LVI over and electrically connected to a third transistor);
a third conductive line (fig. 2A: at least three portions of LML1, and/or LML2) embedded in the first dielectric layer (fig. 2A: LML1 embedded in LIL1, and/or LML2 embedded on LIL2), the third conductive line electrically connected to the conductive signal line (figs. 1, 2A-2C: LML1 electrically connected to LML2);
a fourth transistor (figs. 2A-2C: at least four transistors);
a fourth via (second LVI) disposed over and electrically connected to the fourth transistor (figs. 2A-2C: second LVI over and electrically connected to a fourth transistor; and
a fourth conductive line (additional LIL1) embedded in the first dielectric layer, the fourth conductive line electrically connected to the conductive signal line (figs. 1, 2A-2C: LML1 electrically connected to LML2).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor device of Kim in view of Sasaki to further include third and fourth transistors, third and fourth vias, and third and fourth conductive lines, as a means to facilitate circuits such as logic, memory and hybrid circuits (Sasaki, ¶ 0003), increasing functionality of the device.
Furthermore, it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St Regis Paper Co. v. Bemis Co., 193 USPQ 8. In the instant case, the third and fourth transistors, vias, and conductive lines represent nothing more than duplication of essential work parts of the invention recited in claim 9.
Regarding claim 12, Kim in view of Sasaki teaches the semiconductor device of claim 11, comprising a first source/drain region of a first transistor, a source/drain region of a third transistor, and a source/drain region of a fourth transistor (Sasaki, SD1/SD2 of transistors in PR and NR regions).
Kim in view of Sasaki as applied to claim 11 above does not explicitly teach wherein source/drain regions of the first, second and third transistors are electrically connected to one another.
However, Sasaki does teach first, second a third source/drain regions of respective transistors are electrically connected together (fig. 1: source/drain regions of at least three transistors are electrically connected to POR1 and/or POR2 through contact structures EP).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to electrically connect the first, second and third source/drain regions of Kim in view of Sasaki together, as a means to facilitate circuits such as logic, memory and hybrid circuits (Sasaki, ¶ 0003), increasing functionality of the device.
Regarding claim 13, Kim in view of Sasaki teaches the semiconductor device of claim 12, including a second source/drain region of the first transistor and a source/drain region of the second transistor (Sasaki, ¶ 0026 & fig. 1: each of the first and second transistors includes at least two source/drain regions SD1 and/or SD2).
Kim in view of Sasaki as applied to claim 12 above does not explicitly teach wherein a second source/drain region of the first transistor is electrically connected to a source/drain region of the second transistor.
However, Sasaki teaches at least one embodiment (fig. 1 or fig. 6) wherein a second source/drain region of a first transistor is electrically connected to a source/drain region of a second transistor (fig. 1: right source/drain region of upper NR transistor electrically connected to left source/drain region of lower NR transistor through conductive element POR2).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to electrically connect the second source/drain region of the first transistor to a source/drain region of a second transistor, as a means to facilitate circuits such as logic, memory and hybrid circuits (Sasaki, ¶ 0003), increasing functionality of the device.
Regarding claim 14, Kim in view of Sasaki teaches the semiconductor device of claim 9, further comprising a first external connector (Kim, ¶ 0051: first M3) and a second external connector (Kim, second M3) disposed over the second interconnect structure (Kim, figs. 2, 11E: M3 disposed over a portion of ML2), wherein the first external connector is electrically connected to the first transistor, and wherein the second external connector is electrically connected to the second transistor (figs. 2, 11E: each portion of M3 connected to respective first and second transistor source/drain regions 110).
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claim 15 above, and further in view of Sasaki.
Regarding claim 17, Kim teaches the semiconductor device of claim 15, comprising first and second vias (V1) electrically connected to first and second transistors (each V1 electrically connected to respective first and second MOS transistors),
wherein the third via is electrically connected to a source/drain region of the first transistor (fig. 2: first V2 electrically connected to a source/drain 110 of first MOS transistor).
Kim does not teach wherein the first via is electrically connected to a gate of the first transistor.
Sasaki teaches a semiconductor device (figs. 1 and 2A-2B among others) including a first via (¶ 0039: GC) electrically connected to a gate of a first transistor (fig. 2C: GC electrically connected to gate electrode GE of at least one transistor).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to connect the first via of Kim to a gate of the first transistor, as a means to facilitate circuits such as logic, memory and hybrid circuits (Sasaki, ¶ 0003), increasing functionality of the device.
Regarding claim 18, Kim in view of Sasaki teaches the semiconductor device of claim 17, wherein the fourth via is electrically connected to a source/drain region of the second transistor (Kim, fig. 2: second V2 electrically coupled to source/drain region 110 of second MOS transistor).
Kim does not teach wherein a first conductive line directly electrically couples the third via to the fourth via.
Sasaki teaches a semiconductor device (figs. 1, 2A-2C) including a first conductive line (¶ 0045: LML1) directly electrically couples a third via to a fourth via (fig. 2B: LML1 directly electrically couples third and fourth vias LV1).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to directly electrically couple the third and fourth vias of Kim with a conductive line, as a means to facilitate circuits such as logic, memory and hybrid circuits (Sasaki, ¶ 0003), increasing functionality of the device.
Regarding claim 19, Kim in view of Sasaki teaches the semiconductor device of claim 17, wherein the third via and the fourth via are electrically connected to the power rail (Kim, ¶ 0049 & fig. 2: V2 vias electrically connected to power rail of M2 layer).
Regarding claim 20, Kim teaches the semiconductor device of claim 15, comprising a front side interconnect structure (ML1) and a back side interconnect structure (ML2), wherein a second conductive line of the back side interconnect structure (¶ 0051: M3) is connected to a source/drain region of each of the first transistor and the second transistor (fig. 2: M3 connected to source/drain regions 110 of first and second transistors).
Kim does not teach the semiconductor device further comprising a third transistor interposed between the front side interconnect structure and the back side interconnect structure,
wherein a second conductive line of the back side interconnect structure is connected to a source/drain region of each of the first transistor, the second transistor, and the third transistor.
Sasaki teaches a semiconductor device (figs. 1, 2A-2C) including a third transistor (second MOS transistor in PR or NR regions) interposed between a front side interconnect structure and a back side interconnect structure (fig. 2B: second MOS transistor interposed between UIL2/3/4 and LIL1/2),
wherein a second conductive line of the back side interconnect structure (second portion of LML1 and/or LML2) is connected to a source/drain region of each of a first transistor, a second transistor, and a third transistor (figs.1, 2B: at least a portion of LML1 or LML2 connected to at least through transistor source/drain regions).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to connect the back side interconnect structure of Kim to a source/drain region of each of a first transistor, a second transistor, and a third transistor, as a means to facilitate circuits such as logic, memory and hybrid circuits (Sasaki, ¶ 0003), increasing functionality of the device.
Conclusion
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/BRIAN TURNER/ Examiner, Art Unit 2818
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