DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions & Claims’ Status
Applicant’s election without traverse of Group I (Claims 1-18) in the reply filed on 4/17/2026 is acknowledged.
Claim 19 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 4/17/2026.
Claims 1-19 are currently pending, with Claim 19 withdrawn from further consideration due to restriction requirement (see above). No claims have been amended, cancelled, or newly added.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) were submitted on 7/29/2024, 1/7/2025, and 8/27/2025. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Objections
Claims 1 and 18 are objected to because of the following informalities:
Re Claims 1 and 18, reference is made to “the substrate layer” in each respective line 3, which should instead be “the substrate silicon layer” to maintain proper antecedent basis.
Re Claim 18, a second reference is made to “at least a portion of the middle silicon layer” in lines 9-10, so it should be preceded by “the” for clarity, so that it reads “the at least a portion of the middle silicon layer”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Konig et al (US 2019/0378896 A1, hereafter Konig).
Re Claim 1, Konig discloses an apparatus (FIG. 3; [0043]-[0051]), comprising:
a substrate silicon layer (7; [0043]);
a middle silicon layer (6; [0043]) coupled to the substrate layer (7; [0043]);
an upper silicon layer (at least 5, for now referred to as 5 for simplicity; [0045], upper with apparatus flipped) coupled to the middle silicon layer (6; [0045]);
a cathode terminal (14; [0041]) coupled to the substrate silicon layer (7; [0041]);
an anode terminal (12; [0041]) coupled to the upper silicon layer (5; [0041]); and
one or more trench termination layers (22, 23; [0049]) formed in the substrate silicon layer (7; [0049]) and at least a portion of the middle silicon layer (6; [0049]).
Re Claim 2, Konig discloses the apparatus according to Claim 1, while further disclosing wherein the substrate silicon layer (7) is at least one of the following: an n-type layer ([0045]), a p-type layer, and any combination thereof.
Re Claim 3, Konig discloses the apparatus according to Claim 1, while further disclosing wherein the middle silicon layer (6) is a n-type silicon layer ([0045]).
Re Claim 4, Konig discloses the apparatus according to Claim 3, while further disclosing wherein the middle silicon layer (6) is a N- silicon layer ([0045], see FIG. 3).
Re Claim 5, Konig discloses the apparatus according to Claim 1, while further disclosing wherein the upper silicon layer (5) is a p-type silicon layer ([0045]).
Re Claim 6, Konig discloses the apparatus according to Claim 5, while further disclosing wherein the upper silicon layer (5) is a P+ silicon layer ([0045]).
Re Claim 7, Konig discloses the apparatus according to Claim 6, while further disclosing wherein the middle silicon layer (6) is configured to be encapsulated in one or more silicon side portions (60; [0043], at least in part) configured to extend from the upper silicon layer (5; [0043]).
Re Claim 8, Konig discloses the apparatus according to Claim 1, while further disclosing the apparatus comprises a p-n junction formed between the upper silicon layer (5) and the middle silicon layer (6; [0045], opposite conductivity types for a diode).
Re Claim 9, Konig discloses the apparatus according to Claim 1, while further disclosing wherein the one or more trench termination layers (22, 23) include two trench termination layers (22, 23) formed on at least one side of the substrate silicon layer (7; [0047], [0050]) and the at least a portion of the middle silicon layer (6; [0047], [0050]).
Re Claim 10, Konig discloses the apparatus according to Claim 9, while further disclosing wherein at least one portion of each of the one or more trench termination layers (22, 23) is configured to be substantially parallel to at least one of the following: the substrate silicon layer (7), the middle silicon layer (6), the upper silicon layer (5), the cathode terminal (14), the anode terminal (12), and any combination thereof ([0047], [0050], at least horizontal portions).
Re Claim 11, Konig discloses the apparatus according to Claim 10, while further disclosing wherein at least another portion of each of the one or more trench termination layers (22, 23) is configured to be substantially perpendicular to at least one of the following: the substrate silicon layer (7), the middle silicon layer (6), the upper silicon layer (5), the cathode terminal (14), the anode terminal (12), and any combination thereof ([0047], [0050], vertical portions).
Re Claim 12, Konig discloses the apparatus according to Claim 11, while further disclosing wherein a height of at least one of the one or more trench termination layers (height of 22, vertical portion; [0047]) is configured to be greater than or equal to a thickness of the substrate silicon layer (7; [0047]).
Re Claim 13, Konig discloses the apparatus according to Claim 11, while further disclosing wherein a height of at least one of the one or more trench termination layers (height of 22, horizontal portion; [0047]) is configured to be less than or equal to a thickness of the substrate silicon layer (7; [0047]).
Re Claim 14, Konig discloses the apparatus according to Claim 11, while further disclosing wherein at least one of the one or more trench termination layers (22, 23) is configured to extend substantially vertically into the middle silicon layer (6; [0047], [0050]).
Re Claim 15, Konig discloses the apparatus according to Claim 11, while further disclosing wherein at least one of the one or more trench termination layers (22, 23) is configured to increase a size of a p-n junction formed between the upper silicon layer (5, now including 60, 5 and 60 being different zones of a p-type semiconductor layer) and the middle silicon layer (6; [0044], by variation of t1/height of termination layer 22).
Re Claim 16, Konig discloses the apparatus according to Claim 15, while further disclosing wherein at least one of the one or more trench termination layers (22, 23) is configured to increase a power density of the apparatus (6; [0044], by variation of t1/height of termination layer 22 resulting in change in p-n junction size).
Re Claim 17, Konig discloses the apparatus according to Claim 1, while further disclosing wherein the apparatus is a high power density rectifier diode ([0046]).
Re Claim 18, Konig discloses a high power density rectifier diode (FIG. 3; [0043]-[0051]), comprising:
a substrate silicon layer (7; [0043]);
a middle silicon layer (6; [0043]) coupled to the substrate layer (7; [0043]);
an upper silicon layer (5; [0045], upper with apparatus flipped) coupled to the middle silicon layer (6; [0045]);
a cathode terminal (14; [0041]) coupled to the substrate silicon layer (7; [0041]);
an anode terminal (12; [0041]) coupled to the upper silicon layer (5; [0041]); and
one or more trench termination layers (22, 23; [0049]) formed in the substrate silicon layer (7; [0049]) and at least a portion of the middle silicon layer (6; [0049]), the one or more trench termination layers are configured to be formed on at least one side of the substrate silicon layer (7; [0049]) and at least a portion of the middle silicon layer (6; [0049]);
wherein the substrate silicon layer (7) is at least one of the following: an n-type layer ([0045]), a p-type layer, and any combination thereof.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLIN RUSSELL MCCUTCHEON whose telephone number is (703)756-1897. The examiner can normally be reached Monday-Friday, 12:30-9:30 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DREW N RICHARDS can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/COLIN RUSSELL MCCUTCHEON/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
Prosecution Insights