Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 02/12/2026 is acknowledged. Claims 15-20 are cancelled. Claims 1-14, 21-26 are examined below.
Examiner’s Note
For clarity of the record and ease of examination, the teachings relied upon from Su (CN114678328A) are cited in this Office Action using the corresponding U.S family publication Su (US20220271139A1) solely as a convenient location for pinpoint citations (e.g. paragraph numbering and consistent figures/element labeling). The CN publication and the cited U.S family publication describes the same disclosure, and US20220271139A1 is referenced only to identify the specific passages that correspond to the teachings being applied from CN 114678328 A. The prior art relied upon for statutory purposes remains CN114678328A, and the rejection is based on CN114678328A as the applicable reference. US20220271139A1 is not relied upon as a separate or independent prior art reference and is not the basis of the rejection, including because US20220271139A1 may not qualify as prior art in view of potential applicability of a 35 U.S.C. 102(b)(1) exception.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 23 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 23 recites “wherein the reducing the height of the gate dielectric and the height of the gate spacers reduces a thickness of the interlayer dielectric layer”. This is unclear what thickness is being reduced, e.g., total thickness across the wafer, or, local thickness above the gate region, or remaining thickness after CMP/recess. For the purpose of examination, claim 23 is interpretated as the ILD has a reduced thickness in the region over the recessed gate structure.
Also, the phrasing of claim 23 (“reducing the height of the gate dielectric and the height of the gate spacers reduces a thickness of the interlayer dielectric layer”) is mechanically ambiguous- because ILD thickness is usually a chosen deposition target, not automatically caused by recessing other features.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Su (CN 114678328 A).
Re: Independent Claim 1, Su discloses a method comprising:
forming a gate stack over a semiconductor layer (Su teaches, in Figs. 8-9 and ¶ [0029], gate structure 250 which is later replaced by replacement gate structure 250’ (described in ¶ [0040]) formed over semiconductor/channel members 208), wherein the gate stack includes a gate electrode (Fig. 17 and ¶ [0038], gate electrode layer 255) disposed over a gate dielectric (Fig. 17 and ¶ [0038], gate dielectric layer 254; also, gate electrode layer 255 is formed on and wrapping around the gate dielectric layer 254 and therefore “gate electrode is disposed over gate dielectric” ), wherein the gate stack is disposed between a first epitaxial source/drain and a second epitaxial source/drain (source/drain features 245 formed by epitaxial process and are on both sides of gate structure 250’);
etching the gate dielectric to expose sidewalls of the gate electrode (Block/frame 146 of Fig. 1C, Fig. 22A-22B and ¶ [0050], etching/removing portions of the gate dielectric, thereby exposing sidewall surfaces of the underlying gate electrode 255 in the gate cut openings 286);
forming a gate isolation liner along the exposed sidewalls of the gate electrode (Block 152 of Fig. 1C, Fig. 25A to Fig. 25C and Fig. 25B-1 to Fig. 25C-1, and ¶ [0055], gate cut feature 288 includes dielectric liner 288A along the gate cut opening 286 adjacent the gate electrode 255); and
forming a source/drain contact to the first epitaxial source/drain (¶ [0044], source/drain contact 260 contacting the epitaxial source/drain feature 245 described as “source/drain feature 245 vertically sandwiched between the contact 260 and backside dielectric 270”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-10, 1-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su (CN 114678328 A).
Re: Claim 2, Su discloses all the limitations of claim 1 on which this claim depends.
Su further discloses,
further comprising: forming gate spacers along sidewalls of the gate stack (Su, Fig. 8 and ¶ [0029], teaches forming gate spacers 234 around the top and sidewall surfaces of the dummy gate stack 230, where the gate spacers 234 and dummy gate stack 230 together form original gate structure 250. (Note: even though gate stack in claim 1 is properly mapped to the replacement gate structure 250’, claim 2’s added step “forming gate spacers along sidewalls of the gate stack…” is taught at the earlier stage where spacers 234 are actually formed (original gate structure 250), and Su, in Fig. 17 and ¶ [0040], confirms those same spacers 234 remain and are part of the replacement gate structure 250’ of claim 1)), wherein the gate dielectric is between the gate spacers and the sidewalls of the gate electrode ( Su teaches, in Fig. 17, gate spacer 234 is disposed laterally outside the replacement gate stack, and the gate dielectric layer 254 is positioned between the gate spacer 234 and the gate electrode layer 255 (i.e., the gate dielectric is between the gate spacers and sidewalls of the gate electrode).
With respect of “etching the gate spacers while etching the gate dielectric”, Su teaches that the gate cut opening 286 is extended through the gate structure 250’ by a multi-step etching process. In this multi-etching etching process, Su teaches, in ¶ [0050], block/frame 146 removes the gate dielectric layer 254. Su further teaches, in ¶ [0054], that operations at block/frame 150 expose the gate spacer 234 in the lower portion of the gate cut opening 286 and that the gate spacer 234 may be further removed by selecting etching in the same gate-cut-opening formation sequence. While Su describes these as steps within the same opening-formation flow, Su does not expressly state that the spacer removal occurs concurrently in the same etch step as the gate dielectric removal. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to integrate/overlap the disclosed etch backs such that gate spacers 234 are etched while the gate dielectric 254 is etched, because Su already teaches etching both films in the same localized opening-formation region to achieve the desired opening profile, and overlapping adjacent dielectric etches (via a combined etch and/or over-etch that attacks both materials) is a routine process-integration choice to reduce the number of units process steps and more reliably achieve the target opening geometry/clearance with predictable results.
Re: Claim 3, Su discloses all the limitations of claim 2 on which this claim depends.
Su further discloses,
wherein the etching of the gate dielectric and the etching of the gate spacers forms a gap (Su teaches, in ¶ [0049], forming a gate cut opening 286, and expressly characterizes the opening as having a gap width (t1). Su further teaches, in ¶ [0050], that the method proceeds to extend the cut opening 286 through the gate structure 250’ via a multi-step etching process, including block 146 where gate dielectric layer 254 is removed (thereby exposing the underlying gate electrode layer 255), and, in ¶[0054], block 150 where the etch exposes gate spacer 234 in a lower portion of the gate cut opening 286 and the gate spacer 234 may be further removed by selective etching), the gate isolation liner partially fills the gap, and the method further comprises forming a gate isolation layer to fill a remainder of the gap (Su teaches, in ¶ [0055], at block 152, depositing a dielectric material in the gate cut opening 286 to form a gate cut feature 288. Su further teaches that when the gate cut feature 288 is multilayer, it includes a dielectric liner 288A in contact with the gate segments and a dielectric filler 288B spaced apart from the gate segments by the dielectric liner. Accordingly, the dielectric liner 288A corresponds to the claimed gate isolation liner and partially fills the gate opening/gap 286, and the dielectric filler 288B corresponds to the claimed gate isolation layer that fills the remainder of the gap 286).
Re: Claim 4, Su discloses all the limitations of claim 2 on which this claim depends.
Su does not explicitly disclose wherein the etching of the gate spacers exposes the first epitaxial source/drain, the second epitaxial source/drain, or both.
However, Su teaches, in ¶ [0054], in the gate-cut opening formation sequence, that operations at block 150 expose gate spacer 234 in a lower portion of the gate cut opening 286 and that gate spacer 234 may be further removed by selective etching. Su also teaches, in Fig. 21B and ¶ [0049], that the gate cut opening 286 extends into the source/drain regions, and further teaches, in ¶[0057], that in some embodiments, the forming of the gate cut openings 286 in the source/drain regions include extending through the dielectric layers 222 to expose a backside-facing surface of the contact feature 260. In view of Su’s teaching that (a) the gate cut opening extends into the source/drain regions, (b) the process already includes selectively removing gate spacer 234 to enlarge the lower portion of the opening, and (c) the opening may be extended to expose the source/drain contact 260 in the source/drain regions, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention as a matter of routine process tuning to continue/extend the selective removal in the source/drain-region portion of the opening such that the etch also exposes the underlying epitaxial source/drain feature 245 (i.e., the claimed wherein the etching of the gate spacers exposes the first epitaxial source/drain, the second epitaxial source/drain, or both) in order to improve clearance/isolation and to further reduce parasitic coupling, consistent with Su’s stated goal of reducing capacitance between the gate electrode and the source/drain features (Su, ¶ [0051])).
Su further teaches
wherein the gate isolation liner is formed on the first epitaxial source/drain, the second epitaxial source/drain, or both (Su teaches, in ¶ [0055], forming gate cut feature 288 by depositing dielectric material, and teaches that when multilayered, the gate cut feature includes a dielectric liner 288A (in contact with the gate segments and a dielectric filler 288B. Once the etch is performed to expose the epitaxial source/drain surface within the opening (as above), the subsequently deposited liner 288A would (as a liner deposition into the opening) to formed along the exposed surfaces within the opening, including the exposed epitaxial source/drain feature, thereby meeting the limitation that the gate isolation liner is formed on the first/second epitaxial source/drain).
Re: Claim 5, Su discloses all the limitations of claim 2 on which this claim depends.
Su further discloses,
further comprising forming a first dielectric layer before etching the gate dielectric and before etching the gate spacers, wherein the first dielectric layer includes an interlayer dielectric (ILD) layer disposed over a contact etch stop layer (CESL) (Su teaches, in ¶[0032], block 120 where a contact etch stop layer (CSEL) 243 is deposited and then an interlayer dielectric (ILD) layer 244 is deposited over the CESL 243 (i.e., a dielectric stack that corresponds to the claimed “first dielectric layer”, which includes ILD over CSEL. Su further teaches, in ¶ [0050], that later block 146 removes/etches the gate dielectric layer 254 (exposing the underlying gate electrode layer 255), and further, in ¶ [0054], operations at block 150 expose the gate spacer 234 (and the gate spacer may be further removed), demonstrating that the CESL/ILD stack (243/244) is formed before the subsequent gate dielectric etch and gate spacer etch/removal).
Re: Claim 6, Su discloses all the limitations of claim 5 on which this claim depends.
Regarding the limitation of claim 6 “wherein the etching of the gate dielectric and the etching of the gate spacers forms a gap between the sidewalls of the gate electrode and the first dielectric layer”, Su teaches, in ¶ [0032], forming the “first dielectric layer” as CESL 243 and ILD 244 over CESL 243 (block 120). Su further teaches, in ¶¶ [0049] - [0050], forming a gate cut opening 286 (explicitly described as having a “gap width t1”) and extending the opening through the gate structure. In this sequence, Su teaches removing gate dielectric 254 to expose surface of the underlying gate electrode 255 in the opening (block 146), and Su teaches, in ¶ [0054], etching that exposes gate spacer 234 and may continue such that CESL 243 and then IDL 244 are exposed in the same gate cut opening 286 (block 150). Accordingly, the gate cut opening 286 is the claimed gap between the exposed gate electrode surfaces (255) and the first dielectric layer (CESL/ILD, 243/244).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to perform the disclosed gate dielectric spacer etching so that the resulting opening 286 constitutes the claimed gap between the sidewalls of the gate electrode (255) and the first dielectric layer (CSEL/ILD, 243/244), as a matter of routine etch endpoint selection consistent with Su’s gate isolation/endcap formation process which improves isolation between gate segments (Su, ¶ [0054])).
Further regarding the limitation of claim 6 “and the gate isolation liner partially fills the gap, and the method further comprises forming a second dielectric layer to fill a remainder of the gap”, Su teaches, ¶ [0055], depositing dielectric material in the gate cut opening 286 to form a gate cut feature 288 (block 152), and teaches a multilayer embodiment including a dielectric liner 288A and a dielectric filler 288B.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use Su’s disclosed multilayer configuration such that the liner 288A (gate isolation liner) partially fills the gap/opening and the filler 288B (second dielectric layer) fills the remainder, in order to obtain a robust interface in contact with the gate segments (e.g., oxygen-free liner) while using a different bulk dielectric (e.g., lower-k filler) to reduce parasitic capacitance and improve device performance (Su, ¶ [0055]).
Re: Claim 7, Su discloses all the limitations of claim 5 on which this claim depends.
Regarding the limitation of claim 7, “further comprising etching the first dielectric layer while etching the gate spacers”, Su teaches, in ¶ [0032], the “first dielectric layer” as CESL 243 with ILD 244 over CESL 243 (block 120) and teaches, in ¶ [0029], gate spacers 234. SU further teaches, in ¶ [0054], that during formation/extension of the gate cut opening 286 (a multi-step etch sequence), operations at block 150 expose the gate spacers 234, and the etch may continue such that CESL 243 is exposed, and in another embodiment may continue such that ILD 244 is exposed, i.e., the opening-formation etch reaches the CESL/ILD stack.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to etch the first dielectric layer (CESL 243 and/or ILD 244) during (i.e., while) etching the gate spacers 234 in the gate cut-opening formation flow as a routine process-integration choice, because the same opening-formation etch is already being advanced through adjacent dielectric films in that region, and combining/overlapping etch steps reduces process steps and enables achieving the desired opening depth/profile with predictable results.
Re: Claim 8, Su discloses all the limitations of claim 7 on which this claim depends.
Regarding the limitation of claim 8, wherein the etching of the gate spacers and etching of the first dielectric layer exposes the first epitaxial source/drain, the second epitaxial source/drain, or both, Su teaches, in ¶ [0054], that during formation/extension of the gate cut opening 286, operations at block 150 expose gate spacer 234, and in alternative embodiments the etch continues such that CESL 243 is exposed, and in yet another embodiment such that ILD 244 is exposed in the gate cut opening 286. Su further teaches, in ¶ [0057], the forming of the gate cut openings 286 in the source/drain regions include extending through the dielectric layers 222 to expose a backside-facing surface of the contact feature 260. Accordingly, the gate cut feature 288 extends through to reach the contact feature 260. In some alternative embodiments, the dielectric layers 222 in the source/drain regions have been removed entirely (see FIGS. 25B-3 and 25B-4), such as at the processing stage associated with FIG. 10. Accordingly, the gate cut feature 288 similarly extend to reach a back-facing surface of the contact feature 260 (FIG. 25B-3) or further extend into the contact feature 260.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to tune/extend the disclosed etching of gate spacers 234 and the first dielectric layer (CESL/ILD 243/244) in the source/drain region portion of the gate cut opening so that the etch also exposes a surface of the epitaxial source/drain features 245 when needed, to further improve isolation and reduce parasitic coupling consistent with Su’s stated goal of improving gate isolation and reducing capacitance (including between the gate electrode and the source/drain features).
wherein the gate isolation liner is formed on the first epitaxial source/drain, the second epitaxial source/drain, or both (Su teaches, in ¶ [0055], depositing dielectric in the opening to form gate cut feature 288, including a multilayer embodiment with dielectric liner 288A and dielectric filler 288B. Once the epitaxial source/drain surface is exposed in the opening (as above), it would have been an obvious and predictable result of the conformal liner deposition that the liner 288A is formed on the exposed surfaces within the opening, including the exposed epitaxial source/drain surfaces).
Re: Claim 9, Su discloses all the limitations of claim 1 on which this claim depends.
Regarding the limitation of claim 9, wherein the etching the gate dielectric reduces a width of the gate electrode, Su teaches, in ¶ [0050], that in block 146 the gate dielectric layer 254 is removed, thereby exposing surfaces of the underlying gate electrode layer 255 in the gate cut opening 286. Su further teaches, in ¶ [0051], that in block 148 the gate electrode layer 255 may be recessed, including being laterally recessed such that gate cut opening 286 is widened and the endcap distance is reduced. (A lateral recess of the gate electrode necessarily corresponds to a reduction in gate electrode width at the recessed region.
Although Su teaches the lateral recess of gate electrode 255 as a later step (block 148), it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to integrate/overlap that lateral recess with the gate dielectric removal step (block 146) i.e., perform the gate dielectric etch/over-etch with conditions that also laterally recess the exposed portion of gate electrode 155 - because Su teaches that reducing endcap distance reduces capacitance (including between the gate electrode and the source/drain features) and improves device performance, and combining adjacent etch operations is a routine process-integration choice to reduce steps while achieving the same opening geometry and capacitance benefit.
Re: Independent Claim 10, Su discloses a method comprising:
forming a channel layer over a substrate (Su teaches, in Fig. 2 and ¶ [0021], channel layer 208 on substrate base 202);
forming a gate structure over the channel layer by:
forming gate spacers (Su teaches, in Figs. 7-8 and ¶ [0029], forming gate spacers 234 around the dummy gate stack 230 (in block 114)).
Regarding the limitation of claim 10, forming a gate dielectric layer over the channel layer, wherein the gate dielectric layer is disposed along sidewalls of gate spacers, Su teaches, in ¶ [0033], forming gate trenches between adjacent gate spacers 234 (block 122); then (¶ [0037]) forming gate dielectric layer 254 on and surrounding the channel layer 208 (including interface layer 254A and high k-254B. Although Su doesn’t explicitly state that 254 is “disposed along sidewalls” of spacers 234, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form the gate dielectric 254 conformally along the spacer-bounded trench sidewalls (i.e., along the spacer sidewalls) as a routine integration choice to ensure continuous dielectric isolation and proper gate stack formation in the spacer-defined gate trench); and
forming a gate electrode layer over the gate dielectric layer (Su teaches, in Fig. 17 and ¶ [0038], forming gate electrode layer 255 on and surrounding gate dielectric layer 254); recessing the gate dielectric layer to expose sidewalls of the gate electrode layer (Su teaches, in Figs. 22A-22B, ¶ [0050], gate dielectric layer 254 is removed, thereby exposing the surface of underlying gate electrode layer 255 in the gate cut opening region); and forming a lining layer to cover the exposed sidewalls of the gate electrode layer (Su teaches, in ¶ [0055], gate cut features 288 may be multilayered and include a dielectric line 288A in contact with the gate segment, i.e., lining/covering the exposed gate electrode surfaces in the opening).
Re: Claim 13, Su discloses all the limitations of claim 10 on which this claim depends.
Su further teaches
further comprising: forming a source/drain feature adjacent to the channel layer (Su, in Figs. 9-10 and ¶¶ [0030] – [0031], forms source/drain features 245 in source/drain trenches 236 adjacent the channel region (channel layer 208));
forming a contact etch stop layer over the source/drain feature (Su, in Fig. 11 and ¶ [0032], deposits a contact etch stop layer (CESL) 243 that is conformally deposited over the workpiece, including on surfaces of the source/drain features 245);
forming an interlayer dielectric layer over the contact etch stop layer (Su, in Fig. 11 and ¶ [0032], then blanket deposits ILD layer 244 over CESL 243); and
In regards to the limitation of claim 13, “recessing the interlayer dielectric layer and the contact etch stop layer while recessing the gate dielectric layer”, Su further teaches, in ¶ [0050], that during formation/extension of the gate cut opening 286 (a multi-step etching operation), the process includes removing gate dielectric 254 to expose the underlying gate electrode 255 (block 146), and operations that may continue such that CESL 243 is exposed and then teaches, in ¶ [0054], ILD 244 is exposed in the gate cut opening (block 150). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to recess ILD 244 and CESL 243 during (i.e., while) the gate dielectric 254 is recessed in the gate-cut-opening formation sequence, because Su already teaches etching these adjacent dielectric films in the same localized opening region to shape/expand the opening, and integrating/overlapping such recess operations to achieve the desired opening depth/profile and clearance with predictable results is a routine process-integration choice.
Re: Claim 14, Su discloses all the limitations of claim 10 on which this claim depends.
Su does not explicitly state that
further comprising laterally recessing the gate electrode layer while recessing the gate dielectric layer.
However, Su teaches, in ¶ [0067], recessing the exposed portion of the gate dielectric layer thereby exposing a portion of the gate electrode layer. Su also teaches, in ¶ [0067], laterally recessing the gate electrode layer to expand and extend the gate cut opening. Although Su describes these as separate operations (recess gate dielectric to expose gate electrode, then laterally recess gate electrode), it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to laterally recess the gate electrode layer while recessing the gate dielectric layer, because once dielectric recess exposes the gate electrode, overlapping/combining etch sequence (or extending the same recess step with conditions that also etch the exposed gate electrode) is a routine process-integration choice to achieve the same widened opening/reduced endcap distance that Su already identifies as beneficial for reduced capacitance while reducing discrete processing steps (Su, ¶ [0051]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Su (CN 114678328 A) in view of Chuang (US 20100065915 A1).
Re: Claim 11, Su discloses all the limitations of claim 10 on which this claim depends.
Su further teaches,
further comprising: forming a filling layer over the lining layer, wherein a composition of the filling layer is different than a composition of the lining layer (Su teaches, ¶ [0055], depositing into the gate cut opening 286 to form gate cut feature 288, and teaches that feature 288 may be multilayer, including a dielectric liner 288A and a dielectric filler 288B over the liner, where the liner and filler may be different material (e.g., liner oxygen-free and filler oxygen-containing; and/or different dielectric constants)).
Regarding performing a planarization process on the filling layer and lining layer, wherein the planarization process exposes the gate electrode layer, Su teaches, in ¶ [0055], performing a planarization (CMP) on deposited dielectric of gate cut feature 288 to remove excess dielectric.
Although Su describes CMP exposing backside dielectric layer 270 / isolation feature 204 / liner 284, Su does not expressly state that this planarization exposes the gate electrode layer.
However, Chuang teaches, in ¶ [0038], that after forming dielectric layers, a CMP overpolish may be performed to expose dummy gate structure (i.e., exposing a gate electrode by planarization endpoint selection. Because the dummy gate structure includes the dummy gate electrode, Chuang is explicitly teaching that a planarization process (CMP+ over-polish) can be end-pointed to expose a gate electrode (the dummy gate electrode) as part of a standard process flow.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, when implementing Su’s liner/filler dielectric stack (288A/288B) and CMP step, to choose the CMP endpoint/stop so that the planarization exposes the gate electrode layer (as claim 11 requires), because Chuang teaches that CMP /over-polish is routinely used in gate processing to expose a gate electrode surface (at least the dummy electrode) for subsequent processing; and selecting a CMP endpoint to expose a desired underlying conductive layer is a routine and predictable integration choice.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Su (CN 114678328 A) in view of Lu (US 20170117380 A1).
Re: Claim 12, Su discloses all the limitations of claim 10 on which this claim depends.
Su is silent regarding
further comprising recessing the gate spacers while recessing the gate dielectric layer, wherein after the recessing of the gate spacers and the recessing of the gate dielectric layer, a top surface of the gate dielectric layer is lower than top surfaces of the gate spacers.
However, Lu teaches further comprising recessing the gate spacers while recessing the gate dielectric layer (Lu teaches, in Figs. 1-2 and ¶ [0076], co-removal/co-recess of spacer and gate stack materials in the same operation , i.e, portions of the gate electrode 212 and the dielectric layer 214 of the gate structure 310 may be removed with the low-k dielectric gate spacers 120), wherein after the recessing of the gate spacers and the recessing of the gate dielectric layer, a top surface of the gate dielectric layer is lower than top surfaces of the gate spacers (Lu teaches, in Fig. 15 and ¶ [0077] , the gate electrodes and dielectric layers can be recessed more than gate spacers to create the exact height relationship: “a gate electrode 212d and dielectric layer 214d may be recessed more than the low-k dielectric gate spacer 120d so that an upper surface of the gate electrode 212d and the dielectric layer 214d is lower than an upper surface of the low-k dielectric gate spacer 120d”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement Su’s recessing gate dielectric 254 (block 146) and etch-back/recessing of gate spacers 234 using the co-recess integration taught by Lu (i.e., etch conditions/endpoint that recess spacers and gate dielectric during the same recess flow) in order to achieve the predictable and expressly taught post-recess height relationship (gate dielectric top lower than spacer tops), which improves process integration/clearance near the gate region and is a routine etch-depth/selectively control objective when shaping recessed gate topography.
Claims 21-22, 24, 26 are rejected under 35 U.S.C. 103 as being unpatentable over Hsiung (US 20220102199 A1) in view of Bohr (US 20110156107 A1).
Re: Independent Claim 21, Hsiung discloses a method comprising:
forming a gate structure that includes a gate stack and gate spacers disposed along sidewalls of the gate stack (Hsiung teaches, in Figs. 31B-32 and ¶ [0084], forming a gate structure between gate spacers and describes gate sidewall spacers 260 defining the gate region/gate trench and a replacement gate structure 320 formed between the spacers), wherein the gate stack includes a gate electrode and a gate dielectric (Hsiung teaches, in Fig. 31A and 31B and ¶ [0084], gate structure 320 includes work function metal layer 324 and fill metal layer 326 combined which is the claimed gate electrode, and gate dielectric 322) and after reducing a height of the gate dielectric and a height of the gate spacers (Hsiung teaches, in Fig. 32 and ¶ [0085], an etching back process that etches back the replacement gate structure 320 and the gate spacers 260, producing recesses over both. Because the replacement gate structure 320 includes gate dielectric 322 (Hsiung, ¶ [0084]) within the replacement gate structure, etching back the replacement gate structure reduces the height of the gate dielectric/gate stack, and etching back spacers 260 reduces the spacer height), forming a dielectric structure over the gate spacers, the gate dielectric, and the gate electrode (Hsiung teaches, in Fig. 33 and ¶ [0087], after the etching of gate dielectric and gate spacers as explained above, forming gate dielectric caps 340 (claimed dielectric structure) over gate spacers 260, gate dielectric 322 and gate electrode (324/326)), wherein the dielectric structure is disposed between the gate electrode and an interlayer dielectric layer (Hsiung teaches, in Fig. 36 and ¶ [0094], dielectric structure 340 is disposed between gate electrode 324/326 and interlayer dielectric layer 370).
Hsiung is silent regarding wherein the gate electrode wrapped by the gate dielectric.
However, Bohr teaches wherein the gate electrode wrapped by the gate dielectric (Bohr, Fig. 3A and ¶ [0029], gate electrode layer 102 is formed on the gate dielectric layer 104, i.e., gate electrode 102 is wrapped by the gate dielectric 104). Hsiung and Bohr both disclose transistor fabrication, hence analogous art. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement Hsiung’s replacement gate stack (within replacement gate structure 320 between spacers 260) using Bohr’s U-shaped gate dielectric configuration (104 wrapping the gate electrode 102) in order to provide enhanced dielectric isolation/encapsulation of the gate electrode sidewalls during gate -contact/self-aligned-contact integration (a predictable design choice to reduce gate-to-contact leakage/short risk in precisely the type of contact-formation environment addressed by Hsiung).
Re: Claim 22, Hsiung and Bohr disclose all the limitations of claim 21 on which this claim depends.
Hsiung further teaches
wherein the reducing the height of the gate dielectric and the height of the gate spacers recesses the gate dielectric and the gate spacers below a top of the interlayer dielectric layer (Hsiung teaches, in Fig. 32 and ¶¶ [0084] – [0085], performing an etch-back process that etches back the replacement gate structures 320 and the gate spacers 260, thereby forming recesses over the etched-back gate structures and the etched-back gate spacers. Because the replacement gate structures include the gate dielectric 322 and the gate spacers 260, this etch-back corresponds to reducing the height of the dielectric and the height of the gate spacers. Hsiung further teaches, in Fig. 36, that after the above etch-back/recessing, a dielectric stack including a metal CESL 360 is deposited and then another ILD layer 370 is deposited over the metal CESL 360 and the recessed gate dielectric layer 322 and the gate spacers 260 are below top of the interlayer dielectric layer 370).
Re: Claim 24, Hsiung and Bohr disclose all the limitations of claim 21 on which this claim depends.
Hsiung further teaches
wherein the reducing the height of the gate dielectric and the height of the gate spacers (Hsiung teaches, in ¶ [0085], performing an etch-back process that etches back the replacement gate structures 320 (including gate dielectric 322) and the gate spacers 260, resulting in recessed over the etched-back gate structures 320 and etched-back gate spacers 260).
Bohr teaches reduces a width of the gate electrode (Bohr teaches, in ¶ [0041], that when gate structures are recessed (height-reduced), the recess etch may also remove gate-electrode material such that the metal gate electrode 102 is recessed within the spacers 108, thereby reducing the thickness of the metal gate electrode 102, and Bohr explains, in ¶ [0057], it is important that no portion of the metal gate electrode 102 remains above the top of the spacers 108 after the recessing (because remaining portions atop the spacers can cause contact-to-gate-shorts). Accordingly, removing the portions of the gate electrode that extend onto/above the spacer region necessarily reduces the lateral width of the gate electrode at the top/recessed region).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement Hsiung’s etch-back (height reduction) of the replacement gate structures 320 (including gate electrode metals 324/326) and gate spacers 260 using Bohr’s taught recess integration (recessing the gate electrode within the spacers such that gate-electrode material atop/over the spacer region is removed), in order to avoid gate-to-contact shorts (Bohr, ¶ [005]).
Re: Claim 26, Hsiung and Bohr disclose all the limitations of claim 21 on which this claim depends.
Hsiung further teaches,
further comprising, after forming the dielectric structure, removing a portion of the interlayer dielectric layer when forming a source/drain contact (Hsiung teaches, in Figs. 33-34 and ¶¶ [0087] -[0088], gate dielectric caps 340 formed over gate metal caps 330 and gate spacers 260, and thereafter forming source/drain contracts 350. Hsiung further teaches, in ¶ [0088], that formation of the source/drain contact 350 includes performing one or more etching processes to form contact openings extending through the ILD layer 310 to expose the source/drain epitaxial structures 280, followed by metal fill and CMP. Accordingly, Hsiung teaches that after forming the dielectric structure, a portion of the ILD layer (e.g., ILD 310 is removed by etching when forming the source/drain contacts 350, thereby meeting the additional limitation of claim 26).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Hsiung (US 20220102199 A1) in view of Bohr (US 20110156107 A1) further in view of Liu (US 20150263132 A1).
Re: Claim 23, Hsiung and Bohr disclose all the limitations of claim 21 on which this claim depends.
Both Hsiung and Bohr are silent regarding,
wherein the reducing the height of the gate dielectric and the height of the gate spacers reduces a thickness of the interlayer dielectric layer.
However, Liu teaches wherein the reducing the height of the gate dielectric and the height of the gate spacers reduces a thickness of the interlayer dielectric layer (Liu teaches ILD thickness is determined by recess depth, i.e., Liu teaches, in ¶ [0062], that the thickness of ILD layer is determined by the extent to which an underlying conductive feature is recessed, stating that the “the thickness 238 of ILD layer 223 is generally determined by the extent to which metal 227 is recessed by etching 183”. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Hsiung’s recessing/height reduction of the gate region (replacement gate structures 320, including the gate dielectric, and spacers 260) and subsequent ILD formation (ILD 370), to implement the ILD formation such that the ILD thickness is reduced in response to (i.e., as a consequence of) the recess depth/height reduction, consistent with the teaching of Liu that ILD thickness is determined by the extend of recessing of underlying features, in order to provide a desirable amount of insulation (Liu, ¶ [0062]).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Hsiung (US 20220102199 A1) in view of Bohr (US 20110156107 A1) further in view of Hung (US 8962490 B1).
Re: Claim 25, Hsiung and Bohr disclose all the limitations of claim 21 on which this claim depends.
Both Hsiung and Bohr are silent regarding,
wherein the forming the dielectric structure over the gate spacers, the gate dielectric, and the gate electrode includes: depositing a first dielectric layer; depositing a second dielectric layer; and removing the first dielectric layer and the second dielectric layer from over a top of the gate electrode and a top of the interlayer dielectric layer.
However, Hung teaches the specific dielectric-structure formation sequence of claim 25: wherein the forming the dielectric structure over the gate spacers, the gate dielectric, and the gate electrode includes: depositing a first dielectric layer; depositing a second dielectric layer; and removing the first dielectric layer and the second dielectric layer from over a top of the gate electrode and a top of the interlayer dielectric layer (Hung teaches, in Figs. 1-2, Column 4 and lines 6-12, also lines 49-55, providing a substrate having an interlayer dielectric (ILD) layer 118, with at least one metal gate 124 (claimed gate electrode), dielectric layer 122 (claimed gate dielectric) and gate spacer 108 formed in the ILD, forming a first dielectric layer 130 on the ILD layer 118 and the metal gates 120, forming a second dielectric layer 138 on the first dielectric layer (e.g., TEOS layer). Hung further teaches, in Fig. 2 and column 4 lines 55-67 to column 5 lines 1-20, removing (via etching) the second dielectric layer 138 and the first dielectric layer 130from above (over) the metal gates 120 (gate electrodes) and from above regions of the ILD (since the first dielectric layer is formed on the ILD layer), e. g., Hung teaches an etch that “partially removes the TEOS layer 138 above the metal gates 120 “and “partially removes” the underlying first dielectric components (e.g., NDC 128/cap oxide 126) above the metal gates.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement Hsiung’s dielectric-structure formation over the recessed gate region using Hung’s taught two dielectric deposition + removal (etch-back/etch-open) scheme in order to achieve a well-controlled multilayer dielectric structure above/around metal gates with predictable processing benefits (e.g., improved etch selectivity/clean removal of dielectric stack portions above the gate electrode for subsequent integration steps), as evidenced by Hung explicit focus on processing dielectric layers above metal gates in an ILD environment (explained in Hung’s column 5, lines 34-50).
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
Ouyang (US 20200335346 A1) and Wallace (US 20220190128 A1) disclose integrated circuit structure with gate spacers and plurality of conductive trench contact structures.
Conclusion
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/BIPANA ADHIKARI DAWADI/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898