DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 8-9, 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Torii (US Publication No. 2013/0134548) in view of Liu et al (US Publication No. 2014/0203446).
Regarding claim 1, Torri discloses a method, comprising: forming a first opening Fig 6A, CGa/CGb in a semiconductor substrate Fig 6A, 1, in a plan view the first opening having a ring shape Fig 6B, CGa/CGb; forming a dielectric guard ring in the first opening Fig 7 and Fig 8A, 62a/62b ¶0069-0072; forming an active device Fig 8A, 21 along a first surface of the semiconductor substrate Fig 8A, 1; forming first metallization layers over the active device Fig 8A; forming a second opening Fig 8A, THa/THb through the semiconductor substrate Fig 8A, 1, the second opening adjacent to the ring shape of the dielectric guard ring Fig 8A; forming a conductive through via in the second opening ¶0074; and forming second metallization layers over the first metallization layers Fig 9A-15A. Torii discloses all the limitations but silent on the arrangement of the guard ring. Whereas Liu discloses wherein the dielectric guard ring is level with a major surface of the semiconductor substrate, and wherein the dielectric guard ring extends less than an entirety of a thickness of the semiconductor substrate Fig 3A-3B. Torii and Liu are analogous art because they are directed to semiconductor devices having guard ring structure and one of ordinary skill in the art would have had a reasonable expectation of success to modify Torii because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the guard ring of Torri and incorporate the teachings of Liu since such a modification would have involved a mere change in the size/shape of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1995). A change in shape is generally recognized as being within the level of ordinary skill in the art. In reDailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 2, Torri discloses wherein the first opening is formed through the first surface of the semiconductor substrate Fig 6A and 6B.
Regarding claim 3, Torri discloses wherein the second opening is formed through the first surface of the semiconductor substrate Fig 6A and 6B.
Regarding claim 4, Torri discloses wherein the first opening is formed through a second surface of the semiconductor substrate, and wherein the second surface is opposite of the first surface Fig 6A and 6B.
Regarding claim 5, Torri discloses wherein the second opening is formed through the second surface of the semiconductor substrate, and wherein the second opening exposes the second metallization layers Fig 6A and 6B.
Regarding claim 8, Torri discloses wherein the semiconductor substrate comprises a keep out zone based on the through via, and wherein an entirety of the dielectric guard ring is located within the keep out zone Fig 8A-15A.
Regarding claim 9, Torri discloses a semiconductor device, comprising: an active device Fig 8A, 21 along a first surface of a semiconductor substrate Fig 8A, 1; first metallization layers over and electrically connected to the active device Fig 8A-8B, the first metallization layers comprising conductive features embedded in first dielectric layers Fig 8A-8B; a through via Fig 8A, THa/THb extending through the semiconductor substrate Fig 8A, 1; second metallization layers over and electrically connected to the first metallization layers and the through via Fig 8A-8B; and a dielectric guard ring Fig 8A, 62a/62b embedded in the semiconductor substrate Fig 8A, 1, in a plan view the dielectric guard ring encircling the through via Fig 8A-8B. Torii discloses all the limitations but silent on the arrangement of the guard ring. Whereas Liu discloses wherein the dielectric guard ring is level with a major surface of the semiconductor substrate, and wherein the dielectric guard ring extends less than an entirety of a thickness of the semiconductor substrate Fig 3A-3B. Torii and Liu are analogous art because they are directed to semiconductor devices having guard ring structure and one of ordinary skill in the art would have had a reasonable expectation of success to modify Torii because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the guard ring of Torri and incorporate the teachings of Liu since such a modification would have involved a mere change in the size/shape of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1995). A change in shape is generally recognized as being within the level of ordinary skill in the art. In reDailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 11, Torri discloses wherein a width of the through via at the first surface is less than a width of the through via at a second surface of the semiconductor substrate Fig 9A-9B.
Regarding claim 12, Torri discloses wherein in the plan view the dielectric guard ring has a polygonal shape Fig 8A-8B.
Regarding claim 13, Torri discloses wherein in the plan view the dielectric guard ring has a circular shape Fig 8A-8B.
Regarding claim 14, Torri discloses an additional dielectric guard ring, wherein in the plan view the additional dielectric guard ring encircles the dielectric guard ring Fig 10A-10B.
Claims 6-7, 10 are rejected under 35 U.S.C. 103 as being unpatentable over Torii (US Publication No. 2013/0134548) in view of Torii (US Publication No. 2013/0134548) in view of Liu et al (US Publication No. 2014/0203446) and in further view of Ding et al (US Publication No. 2020/0006199).
Regarding claim 6, Torii discloses all the limitations but silent on the height of the guard ring. Whereas Ding discloses wherein after forming the second metallization layers Fig 4, a first height of the guard ring Fig 4, 310 within the semiconductor substrate is less than a second height of the through via Fig 4, 200 within the semiconductor substrate. Torii and Ding are analogous art because they are directed to semiconductor devices having buffer structure/guard rings and one of ordinary skill in the art would have had a reasonable expectation of success to modify Torii because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the guard ring of Torri and incorporate the teachings of Ding since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1995).
Regarding claim 7, Ding in view of Torri discloses wherein the first height is greater than twice a first width of the dielectric guard ring Fig 4, 310, wherein the first width is measured at the first surface of the semiconductor substrate Fig 4, wherein the second height is greater than twice a second width of the through via Fig 4, and wherein the second width is measured at the first surface of the semiconductor substrate Fig 4.
Regarding claim 10, Ding discloses wherein a width of the through via at the first surface is greater than a width of the through via at a second surface of the semiconductor substrate Fig 4.
Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Torii (US Publication No. 2013/0134548) in view of Kobayashi et al (US Publication No. 2012/0315738).
Regarding claim 15, Torri discloses a semiconductor device, comprising: an active device Fig 8A, 21 along a front side surface of a semiconductor substrate, the semiconductor substrate having a thickness between the front side surface and a back side surface Fig 8A; a through via embedded in the semiconductor substrate, the through via Fig 8A, THa/THb having a first width at the front side surface, the through via having a first height within the semiconductor substrate, the through via having a first decreasing width gradient in a first direction between the front side surface and the ack side surface Fig 8A; a dielectric guard ring Fig 8A, 62a/62b embedded in the semiconductor substrate and encircling the through via Fig 8A-8B, the dielectric guard ring having a second width at a location most proximal or at the front side surface Fig 8A-8B, the dielectric guard ring having a second height Fig 8A-8B; and a metallization layer over the semiconductor substrate Fig 8A-8B, the metallization layer being electrically connected to the active device and the through via Fig 8A-8B. Torri discloses all the limitations but silent on the arrangement of the guard ring relative to the TSV. Whereas Kobayashi discloses the dielectric guard ring having a second decreasing width gradient in a second direction between the front side surface and the back side surface, the second direction being reverse of the first direction Fig 17A-17D, 18A. Torii and Kobayashi are analogous art because they are directed to semiconductor devices having guard ring structure and one of ordinary skill in the art would have had a reasonable expectation of success to modify Torii because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the guard ring of Torri and incorporate the teachings of Kobayashi since such a modification would have involved a mere change in the size/shape of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1995). A change in shape is generally recognized as being within the level of ordinary skill in the art. In reDailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claims 16-18, Torri and Kobayashi discloses all the limitations but silent on the height of the TSV relative to the guard ring. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the height of the via or the guard ring, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ (CCPA 1980).
Regarding claims 19-20, Torri and Kobayashi discloses all the limitations but silent on the ratio. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the ratio, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955).
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTINE A ENAD whose telephone number is (571)270-7891. The examiner can normally be reached Monday-Friday, 7:30 am -4:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571 272 1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811
Prosecution Insights