DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-18 in the reply filed on 4/13/2026 is acknowledged.
Currently claims 1-18 and newly added claims 21-22 are pending. Claims 19-20 are canceled.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18, 21 & 22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With regards to claim 1, the claim recites “a method for reducing a depth loading of dielectric structures on a substrate , comprising : receiving a substrate.. The use of the receiving “a substrate” creates ambiguity as to whether a second substrate is being introduced into the method. To further prosecution the examiner is interpreting that there is only one substrate being introduced. Appropriate correction is required.
With regards to claim 4, the limitation of wherein the depth loading is ± 60
nanometers is unclear and ambiguous. The claim fails to define a
reference point or baseline for the depth loading. Appropriate correction is required.
With regards to claim 13, the claim recites “a method for reducing a depth loading of dielectric structures on a substrate , comprising : receiving a substrate.. The use of the receiving “a substrate” creates ambiguity as to whether a second substrate is being introduced into the method. To further prosecution the examiner is interpreting that there is only one substrate being introduced. Appropriate correction is required.
With regards to claim 16, the limitation of wherein the depth loading is ± 60
nanometers is unclear and ambiguous. The claim fails to define a
reference point or baseline for the depth loading. Appropriate correction is required.
With regards to claim 21, the claim recites “a method for reducing a depth loading of dielectric structures on a substrate , comprising : receiving a substrate.. The use of the receiving “a substrate” creates ambiguity as to whether a second substrate is being introduced into the method. To further prosecution the examiner is interpreting that there is only one substrate being introduced. Appropriate correction is required.
With regards to claim 22, the limitation of wherein the depth loading is ± 60
nanometers is unclear and ambiguous. The claim fails to define a
reference point or baseline for the depth loading. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 13, 16, 21 & 22 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lin (US pub no. 2025/0142951 A1).
Regarding claim 13, Lin et al discloses A method for reducing a depth loading of dielectric structures(20/366/368) on a substrate(310)[0072][0066], comprising:
receiving a substrate (310)comprising a plurality of long dummy gate regions(328)
extending in a lateral direction, each dummy gate region(328) having a first dielectric spacer (330)and a second dielectric spacer(330) extending in the lateral direction and directly contacting opposite sides of the dummy gate region(328)[0072][0066];
a first continuous etch stop layer (342)extending in the lateral direction and directly contacting a side of the first dielectric spacer(330) opposite that of the dummy gate region(328)[0075]; and a second continuous etch stop layer(342) extending in the lateral direction and directly contacting a side of the second dielectric spacer(330)
opposite that of the dummy gate region(328)[0075]; forming a hard mask layer (348)over the substrate that exerts a tensile force[0076]; patterning the hard mask layer(348) to define a set of isolated long trenches (356)and a set of dense short trenches(358) over the plurality of long dummy gate regions(328)[0078-0079];
etching through the hard mask layer(348) to form the set of isolated long
trenches(368)[ 0082][0085][0087-0088]; etching through the hard mask layer(348) to form the set of dense short trenches(366)[0082][0085][0087-0088], wherein a plurality of short trenches(358) is formed from a long dummy gate region(328), with a wall of dummy gate material separating adjacent short trenches(358)[0071][0078]; and filling each trench with at least one dielectric material to form a set of isolated long dielectric structures(366) and a set of dense short dielectric structures(368) on the substrate(310) [0088].
Regarding claim 16, Lin et al discloses wherein the depth loading is ±60 nanometers[0081].
Regarding claim 21,Lin et al discloses a method for reducing a depth loading of dielectric structures(20/366/368) on a substrate(310)[0072][0066], comprising: receiving a substrate(310) comprising a plurality of long dummy gate regions (328)extending in a lateral direction, each dummy gate region(328) having a first dielectric spacer (330)and a second dielectric spacer(330) extending in the lateral direction and directly contacting opposite sides of the dummy gate region(328)[0072][0066]; a first continuous etch stop layer (342)extending in the lateral direction and directly contacting a side of the first dielectric spacer (330)opposite that of the dummy gate region(328)[0075]; and a second continuous etch stop layer(342) extending in the lateral direction and directly contacting a side of the second dielectric spacer (330)opposite that of the dummy gate region(328)[0075]; forming a hard mask layer(330) over the substrate(310) that exerts a force[0076]; patterning the hard mask layer (330) to define a set of isolated long trenches (368)and a set of dense short trenches(366) over the plurality of long dummy gate regions(328)[0082][0085][0087-0088]; etching through the hard mask layer to form the set of isolated long trenches (358)and the set of dense short trenches(356)[0082][0085][0087-0088], wherein a plurality of short trenches is formed from a long dummy gate region(328) )[0082][0085][0087-0088], with a wall of dummy gate material separating adjacent short trenches(356) )[0082][0085][0087-0088]; and filling each trench with at least one dielectric material to form a set of isolated long dielectric structures(368) and a set of dense short dielectric structures (366)on the substrate)[0082][0085][0087-0088].
Regarding claim 22, Lin et al discloses wherein the depth loading is ±60 nanometers[0081].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6,8,9,11,12,14,15,17, & 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US pub no. 2025/0142951 A1).
Regarding claim 1, Lin et al discloses A method for reducing a depth loading of dielectric structures (20/366/368)on a substrate(310)[0088], comprising: receiving a substrate (310)comprising a plurality of long dummy gate regions(328) extending in a lateral direction, each dummy gate region (328)having a first dielectric spacer (330)and a second dielectric spacer (330)extending in the lateral direction and directly contacting opposite sides of the dummy gate region(328)[0072][0066]; a first continuous etch stop layer(342) extending in the lateral direction and directly contacting a side of the first dielectric spacer(328) opposite that of the dummy gate region(328) [0075]; and
a second continuous etch stop layer(328) extending in the lateral direction and directly contacting a side of the second dielectric spacer(330) opposite that of the dummy gate region(328) [0075]; forming a hard mask layer (348)over the substrate(310); patterning the hard mask layer (348)to define a set of isolated long trenches(356 ) and a set of dense short trenches(358) over the plurality of long dummy gate regions(328)[0078-0079][0034]; etching through the hard mask layer(348) to form the set of isolated long trenches[0082][0085][0087]; etching through the hard mask layer to form the set of dense short trenches[0082][0085][0087], wherein a plurality of short trenches is formed from a long dummy gate region(328), with a wall of dummy gate material separating adjacent short trenches(356)[0071][0078]; and filling each trench with at least one dielectric material to form a set of isolated long dielectric structures(366) and a set of dense short dielectric structures(368) on the substrate(310)[0088].
Lin et al fig. 7a-13b fails to teach a hard mask exerting a compressive stress.
In another embodiment (fig. 4b) Lin et al discloses ,the hard mask (46) over the substrate(12) exerts a compressive stress[0050]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Lin et al with the embodiment of fig, 4b since the hard mask shrinks the surface area of the substrate resulting in a n opening with a reduced or compressed CD.
Regarding claim 2, Lin et al discloses wherein an average critical dimension(CD) of the set of isolated long dielectric structures and an average critical dimension(CD) of the set of dense short dielectric structures[0047-0048] and further teaches that critical dimensions is dependent on passivation oriented etch processes and /or stress tuning [0048]but fails to teach is each 20 nanometers or less. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to achieve 20 nm or less through routine experimentation. W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation."In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)
Regarding claim 3, Lin et al discloses wherein an average depth of the set of isolated long dielectric structures and an average depth of the set of dense short dielectric structures[0047-0048] and further teaches that the trench depth is dependent on passivation oriented etch processes and /or stress tuning [0048]but fails to teach is each at least 180 nanometers. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to achieve each at least 180 nanometers through routine experimentation. W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation."In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)
Regarding claim 4, Lin et al discloses wherein the depth loading is ±60 nanometers[0081].
Regarding claim 5, Lin et al discloses wherein the first dielectric spacer (330)and the second dielectric spacer (330)have a Young's modulus of 75 GPa or less[0072- silicon carboxynitride-same material as disclosed in claim 6].
Regarding claim 6, Lin et al discloses wherein the first dielectric spacer (330)and the second dielectric spacer (330)are made of silicon carboxynitride[0072].
Regarding claim 8, Lin et al discloses wherein the first continuous etch stop layer (342)and the second continuous etch stop layer (342)have a Young's modulus of about 250 GPa or higher[0075 same material as disclosed in claim 9].
Regarding claim 9, Lin et al discloses , wherein the first continuous etch stop layer(342) and the second continuous etch stop layer (342)are made of silicon nitride[0075].
Regarding claim 11, Lin et al discloses wherein the dummy gate material has a Young's modulus of about 140 GPa to about 180 GPa[0071-same material as claim 12].
Regarding claim 12, Lin et al discloses wherein the dummy gate material is polysilicon[0071].
Regarding claim 14, Lin et al discloses wherein an average critical dimension(CD) of the set of isolated long dielectric structures and an average critical dimension(CD) of the set of dense short dielectric structures[0047-0048] and further teaches that critical dimensions is dependent on passivation oriented etch processes and /or stress tuning [0048]but fails to teach is each 20 nanometers or less. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to achieve 20 nm or less through routine experimentation. W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation."In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)
Regarding claim 15, Lin et al discloses wherein an average depth of the set of isolated long dielectric structures and an average depth of the set of dense short dielectric structures[0047-0048] and further teaches that the trench depth is dependent on passivation oriented etch processes and /or stress tuning [0048]but fails to teach is each at least 180 nanometers. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to achieve each at least 180 nanometers through routine experimentation. W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation."In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)
Regarding claim 17, Lin et al discloses wherein the first dielectric spacer (330)and the second dielectric spacer (330) material silicon carboxynitride [0072] but it is silent to teach of have a Young's modulus of 75 GPa or less. Since Lin et al discloses the same material as applicant’s invention the dielectric spacer properties of Young's modulus of 75 GPa or less are necessarily present. "Products of identical chemical composition can not have mutually exclusive properties." In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990).
Regarding claim 18, Lin et al discloses wherein the first continuous etch stop layer (342)and the second continuous etch stop layer (342) silicon nitride [0075] but is silent have a Young's modulus of about 250 GPa or higher. Since Lin et al discloses the same material as applicant’s invention the dielectric spacer properties of Young's modulus of about 250 GPa or higher. "Products of identical chemical composition can not have mutually exclusive properties." In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LATANYA N CRAWFORD EASON whose telephone number is (571)270-3208. The examiner can normally be reached Monday-Friday 8:30 AM-4:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LATANYA N CRAWFORD EASON/Primary Examiner, Art Unit 2813
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