Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see section titled “35 U.S.C. 112,” filed 05/06/2026, with respect to the rejection of claims 1, 4-5, 7-8, 10-16, and 18-20 under 35 U.S.C. 112 have been fully considered and are persuasive. The rejection of claims 1, 4-5, 7-8, 10-16, and 18-20 under 35 U.S.C. 112 has been withdrawn.
Applicant's arguments filed 05/06/2026 have been fully considered but they are not persuasive.
Regarding arguments that the cited prior art Hutson (US4021837A) does not teach the newly added limitation
wherein the trench and the isolation region prevent migration of one or more charge carriers between the first and second semiconductor device.
Hutson teaches in col. 5 that “[a]n important aspect of the switch shown in FIG. 1 is that the width of the grooves 20 and 24 is sufficiently wide that electrical carriers are unable to pass through the N-type layer 12 from one area to another between the grooves” and so Hutson’s isolation region does prevent carrier migration between first and second semiconductor devices.
See below for full claims mapping.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-5, 7-8, 10-16, and 18-21 are rejected under 35 U.S.C. 103 as being unpatentable over Hutson (US4021837A) in view of Galtie et al. (US20020008247A1, hereinafter Galtie).
Regarding claim 1, Hutson teaches a semiconductor device, comprising:
a first silicon layer (Fig. 4 layer 14), a second silicon layer (Fig. 4 layer 12), and a third silicon layer (Fig. 4 layer 16), the first silicon being coupled to the second silicon layer and the second silicon layer being coupled to the third silicon layer (Fig. 4 layers 12/14/16 all coupled to each other), wherein the first silicon layer is a p-type silicon layer, the second silicon layer is an n-type silicon layer, and the third silicon layer is a p-type silicon layer (Fig. 4 layer 14 is a p-type layer, layer 12 is an n-type layer, and layer 16 is a p-type layer. Examiner notes the type of doping is present on figure 4);
a trench formed in the first silicon layer and in at least a portion of the second silicon layer (Fig. 4 grooves 92/94 formed in layers 14/16 and extending into layer 12 from both directions);
an isolation region formed in at least the second silicon layer (Fig. 4 carrier lifetime degrading material 96/98 in grooves 92/94), the trench and the isolation region separate the semiconductor device into a first semiconductor device portion and a second semiconductor device portion (Hutson col. 5 teaches that “[a] groove [92/94] is formed in each of the outer layers to electrically separate each of the outer layers into two areas”), wherein the trench and the isolation region prevent migration of one or more charge carriers between the first and second semiconductor device portions (Hutson col. 5 teaches that “[a]n important aspect of the switch shown in FIG. 1 is that the width of the grooves 20 and 24 is sufficiently wide that electrical carriers are unable to pass through the N-type layer 12 from one area to another between the grooves” and so Hutson’s isolation region does prevent carrier migration between regions);
a first main terminal one and a first gate terminal coupled to a first portion of the first silicon layer (Fig. 4 electrodes 30 and 24 coupled to a portion of layer 14 to the left of groove 92);
a second main terminal one and a second gate terminal coupled to a second portion of the first silicon layer (Fig. 4 electrodes 32 and 26 coupled to a portion of layer 14 to the right of groove 92);
a main terminal two coupled to the third silicon layer (Fig. 4 electrode 38 coupled to layer 16); and
one or more silicon regions in the first silicon layer and in the third silicon layer, the one or more silicon regions are n-type silicon regions (Fig. 4 N+ type layers 16/18 in layer 14 and N+ layer 22 within layer 16).
Hutson does not appear to teach
wherein the isolation region is configured to extend from the trench to the third silicon layer
Galtie teaches
wherein the isolation region is configured to extend from the trench to the third silicon layer (Fig. 2 p-type isolating wall 13 extends from a top surface down to a bottom surface).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hutson with the teachings of Galtie because as both Hutson and Galtie teach suitable and compatible methods for forming an isolating structure in a TRIAC device, it would have been obvious to combine Hutson’s trench filled with a carrier lifetime degrading material that extends partially through the center of the device with Galtie’s p-type isolating wall that extends fully through the center of the device to achieve the predictable result of forming a p-type isolating structure that extends fully through the device in combination with a trench filled with a carrier lifetime degrading material that extends partially through the center of the device.
Regarding claim 4, the combination of Hutson and Galtie teaches the semiconductor device according to claim 1,
wherein the first and third silicon layers are P+ doped layers (Hutson fig. 4 layer 14 is a p-type layer and layer 16 is a p-type layer. While the combination of Hutson and Galtie does not explicitly disclose layers 14 and 16 being p+, as the only difference between the combination of Hutson and Galtie and the claimed invention is a relative recitation of concentration in layers 14 and 16 and nothing within the disclosure indicates that a device having the claimed dimensions would perform differently than the combination of Hutson and Galtie, such a recitation of relative dimensions is not enough to be patentably distinct, see MPEP 2144.04(IV)(A)).
Regarding claim 5, the combination of Hutson and Galtie teaches the semiconductor device according to claim 4,
wherein the second silicon layer is a N- doped layer (Hutson fig. 4 layer 12 is an n-type layer. While the combination of Hutson and Galtie does not explicitly disclose layers 12 as being n-, as the only difference between the combination of Hutson and Galtie and the claimed invention is a relative recitation of concentration in layer 12 and nothing within the disclosure indicates that a device having the claimed dimensions would perform differently than the combination of Hutson and Galtie, such a recitation of relative dimensions is not enough to be patentably distinct, see MPEP 2144.04(IV)(A)).
Regarding claim 7, the combination of Hutson and Galtie teaches the semiconductor device according to claim 1,
wherein the isolation region is a p-doped region (Galtie teaches a p-type isolating wall 13 as seen in Galtie fig. 2, see above rejection of claim 1).
Regarding claim 8, the combination of Hutson and Galtie teaches the semiconductor device according to claim 1,
wherein the trench is configured to separate the first silicon layer into the first portion of the first silicon layer and the second portion of the first silicon layer (Hutson col. 5 “[a] groove is formed in each of the outer layers to electrically separate each of the outer layers into two areas”).
Regarding claim 10, the combination of Hutson and Galtie teaches the semiconductor device according to claim 8,
wherein the first main terminal one and the first gate terminal are each coupled to at least one region in the one or more silicon regions (Hutson fig. 4 electrodes 30 coupled to N+ regions 16. While electrode 24 is not coupled to an N+ region within layer 14, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further add an N+ region below electrode 24 in order to increase contact efficiency as done for electrode 30).
Regarding claim 11, the combination of Hutson and Galtie teaches the semiconductor device according to claim 10,
wherein the second gate terminal is coupled to at least another region in the one or more silicon regions and the second main terminal one is not coupled to the one or more silicon regions (Hutson fig. 4 electrode 26 coupled to N+ region 18 and electrode 32 is not coupled to one of the N+ regions).
Regarding claim 12, the combination of Hutson and Galtie teaches the semiconductor device according to claim 11,
wherein the main terminal two is coupled to at least yet another region in the one or more silicon regions, the at least yet another region being positioned in the third silicon layer in the second semiconductor device portion (Hutson fig. 4 electrode 38 coupled to N+ layer 22), the at least yet another region being positioned in the third silicon layer in the second semiconductor device portion (Fig. 4 N+ layer is positioned within layer 16 and in the semiconductor device portion to the right of groove 92).
Regarding claim 13, the combination of Hutson and Galtie teaches the semiconductor device according to claim 8,
wherein a depth of the trench is configured to be greater than a thickness of the first silicon layer (Hutson fig. 4 groove 92 extends deeper than layer 14 into layer 12 and so it has a greater thickness than layer 14).
Regarding claim 14, the combination of Hutson and Galtie teaches the semiconductor device according to claim 8,
wherein the trench and the isolation region are configured to prevent migration of one or more charge carriers between the first and second semiconductor device portions (Hutson teaches in col. 5 that “[a]n important aspect of the switch shown in FIG. 1 is that the width of the grooves 20 and 24 is sufficiently wide that electrical carriers are unable to pass through the N-type layer 12 from one area to another between the grooves” and so Hutson’s isolation region does prevent carrier migration between first and second semiconductor devices).
Regarding claim 15, the combination of Hutson and Galtie teaches
the semiconductor device according to claim 11, wherein the first semiconductor device portion is configured to route current upon a bias of main terminal two being higher than a bias of the first main terminal one (Hutson col. 3 “[t]he device shown in FIG. 1 provides symmetrical electrical switching operation somewhat similar to that of conventional triacs upon the application of suitable bias to the three electrodes” and so the semiconductor device portion to the left of groove 92 routes current upon a biasing of electrode 38 higher than electrode 30).
Regarding claim 16, the combination of Hutson and Galtie teaches the semiconductor device according to claim 15,
wherein the second semiconductor device portion is configured to route current upon a bias of the second main terminal one being higher than a bias of the main terminal two (Hutson col. 3 “[t]he device shown in FIG. 1 provides symmetrical electrical switching operation somewhat similar to that of conventional triacs upon the application of suitable bias to the three electrodes” and so the semiconductor device portion to the right of groove 92 routes current upon a biasing of electrode 32 higher than electrode 38).
Regarding claim 18, the combination of Hutson and Galtie teaches the semiconductor device according to claim 1,
wherein the semiconductor device is a thyristor (Hutson col. 1 “[a] symmetrical switch for providing bidirectional switching is commonly termed a triac and has heretofore generally comprised five layers of alternating semiconductor types” and examiner notes TRIACs comprise a thyristor).
Regarding claim 19, the combination of Hutson and Galtie teaches the semiconductor device according to claim 18,
wherein the semiconductor device is a TRIAC semiconductor device (Hutson col. 1 “[a] symmetrical switch for providing bidirectional switching is commonly termed a triac and has heretofore generally comprised five layers of alternating semiconductor types” and so the combination of Hutson and Galtie teaches a TRIAC semiconductor device).
Regarding claim 20, Hutson teaches a semiconductor device, comprising:
a first silicon layer (Fig. 4 layer 14), a second silicon layer (Fig. 4 layer 12), and a third silicon layer (Fig. 4 layer 16), the first silicon being coupled to the second silicon layer and the second silicon layer being coupled to the third silicon layer (Fig. 4 layers 12/14/16 all coupled to each other), wherein the first silicon layer is a p-type silicon layer, the second silicon layer is an n-type silicon layer, and the third silicon layer is a p-type silicon layer (Fig. 4 layer 14 is a p-type layer, layer 12 is an n-type layer, and layer 16 is a p-type layer. Examiner notes the type of doping is present on figure 4);
a trench formed in the first silicon layer and in at least a portion of the second silicon layer (Fig. 4 grooves 92/94 formed in layers 14/16 and extending into layer 12 from both directions);
an isolation region formed in at least the second silicon layer (Fig. 4 carrier lifetime degrading material 96/98 in grooves 92/94), wherein the trench and the isolation region are configured to separate the semiconductor device into a first semiconductor device portion and a second semiconductor device portion (Hutson col. 5 “[a] groove is formed in each of the outer layers to electrically separate each of the outer layers into two areas”), wherein the trench and the isolation region prevent migration of one or more charge carriers between the first and second semiconductor device portions (Hutson col. 5 teaches that “[a]n important aspect of the switch shown in FIG. 1 is that the width of the grooves 20 and 24 is sufficiently wide that electrical carriers are unable to pass through the N-type layer 12 from one area to another between the grooves” and so Hutson’s isolation region does prevent carrier migration between regions);
a first main terminal one and a first gate terminal coupled to a first portion of the first silicon layer (Fig. 4 electrodes 30 and 24 coupled to a portion of layer 14 to the left of groove 92);
a second main terminal one and a second gate terminal coupled to a second portion of the first silicon layer (Fig. 4 electrodes 32 and 26 coupled to a portion of layer 14 to the right of groove 92);
a main terminal two coupled to the third silicon layer (Fig. 4 electrode 38 coupled to layer 16); and
one or more silicon regions in the first silicon layer and in the third silicon layer, the one or more silicon regions are n-type silicon regions (Fig. 4 N+ type layers 16/18 in layer 14 and N+ layer 22 within layer 16);
wherein the first semiconductor device portion is configured to route current upon a bias of main terminal two being higher than a bias of the first main terminal one (Hutson col. 3 “[t]he device shown in FIG. 1 provides symmetrical electrical switching operation somewhat similar to that of conventional triacs upon the application of suitable bias to the three electrodes” and so the semiconductor device portion to the left of groove 92 routes current upon a biasing of electrode 38 higher than electrode 30), and the second semiconductor device portion is configured to route current upon a bias of the second main terminal one being higher than a bias of the main terminal two (Hutson col. 3 “[t]he device shown in FIG. 1 provides symmetrical electrical switching operation somewhat similar to that of conventional triacs upon the application of suitable bias to the three electrodes” and so the semiconductor device portion to the right of groove 92 routes current upon a biasing of electrode 32 higher than electrode 38).
Hutson does not appear to teach
wherein the isolation region is configured to extend from the trench to the third silicon layer.
Galtie teaches
wherein the isolation region is configured to extend from the trench to the third silicon layer (Fig. 2 p-type isolating wall 13 extends from a top surface down to a bottom surface).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hutson with the teachings of Galtie because as both Hutson and Galtie teach suitable and compatible methods for forming an isolating structure in a TRIAC device, it would have been obvious to combine Hutson’s trench filled with a carrier lifetime degrading material that extends partially through the center of the device with Galtie’s p-type isolating wall that extends fully through the center of the device to achieve the predictable result of forming a p-type isolating structure that extends fully through the device in combination with a trench filled with a carrier lifetime degrading material that extends partially through the center of the device.
Regarding claim 21, Hutson teaches a method for manufacturing a semiconductor device, comprising:
providing a first silicon layer (Fig. 4 layer 14), a second silicon layer (Fig. 4 layer 12), and a third silicon layer (Fig. 4 layer 16), wherein the first silicon layer is a p-type silicon layer, the second silicon layer is an n-type silicon layer, and the third silicon layer is a p-type silicon layer (Fig. 4 layer 14 is a p-type layer, layer 12 is an n-type layer, and layer 16 is a p-type layer. Examiner notes the type of doping is present on figure 4);
coupling the first silicon to the second silicon layer and coupling the second silicon layer to the third silicon layer (Fig. 4 layers 12/14/16 all coupled to each other);
forming a trench in the first silicon layer and at least a portion of the second silicon layer (Fig. 4 grooves 92/94 formed in layers 14/16 and both extending into layer 12);
forming an isolation region in at least the second silicon layer (Fig. 4 carrier lifetime degrading material 96/98 in grooves 92/94), the trench and the isolation region separate the semiconductor device into a first semiconductor device portion and a second semiconductor device portion, wherein the trench and the isolation region prevent migration of one or more charge carriers between the first and second semiconductor device portions (Hutson col. 5 teaches that “[a]n important aspect of the switch shown in FIG. 1 is that the width of the grooves 20 and 24 is sufficiently wide that electrical carriers are unable to pass through the N-type layer 12 from one area to another between the grooves” and so Hutson’s isolation region does prevent carrier migration between regions);
coupling a first main terminal one and a first gate terminal to a first portion of the first silicon layer (Fig. 4 electrodes 30 and 24 coupled to a portion of layer 14 to the left of groove 92), coupling a second main terminal one and a second gate terminal to a second portion of the first silicon layer (Fig. 4 electrodes 32 and 26 coupled to a portion of layer 14 to the right of groove 92), and coupling a main terminal two to the third silicon layer (Fig. 4 electrode 38 coupled to layer 16); and
forming one or more regions in the first and second portions of the first silicon layer and the third silicon layer, the one or more silicon regions are n-type silicon regions (Fig. 4 N+ type layers 16/18 in layer 14 and N+ layer 22 within layer 16).
Hutson does not appear to teach
wherein the isolation region is configured to extend from the trench to the third silicon layer.
Galtie teaches
wherein the isolation region is configured to extend from the trench to the third silicon layer (Fig. 2 p-type isolating wall 13 extends from a top surface down to a bottom surface).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hutson with the teachings of Galtie because as both Hutson and Galtie teach suitable and compatible methods for forming an isolating structure in a TRIAC device, it would have been obvious to combine Hutson’s trench filled with a carrier lifetime degrading material that extends partially through the center of the device with Galtie’s p-type isolating wall that extends fully through the center of the device to achieve the predictable result of forming a p-type isolating structure that extends fully through the device in combination with a trench filled with a carrier lifetime degrading material that extends partially through the center of the device.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLE LEON LINDSEY whose telephone number is (571)272-4028. The examiner can normally be reached Monday - Friday, 8:00 a.m. - 5:00 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COLE LEON LINDSEY/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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