DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-6 are pending in the application.
Claims 1-6 are examined on merits herein.
Specification
The disclosure is objected to because of the following informalities:
Paragraphs 0030, 0031, 0137, 0138, and 0140 of the published application (US 2024/0105114) refer to Figs. 13 and 14 as describing “a driving range”. However, Fig. 13 is explicitly directed to a driving current of a driving transistor T1, and Fig. 14 is explicitly directed to a driving voltage of the driving transistor. Examiner suggests making the above-cited paragraphs clearer by identifying one “driving range” as “a driving current” and by identifying a second “driving range” as “a driving voltage”.
Paragraphs 0060 and 0154 of the published application contradict to each other: Paragraph 0060 teaches that transistor T4 (being an initialization voltage transistor, see 0059) is an NMOS transistor, which means that a positive voltage (VINT) applies to its drain (see at least Fig. 19 of Sze, NPL, provided with the Office Action, on voltages appropriate for NMOS and PMOS transistors). However, paragraph 0154 states that the transistor initialization voltage VINT has a negative polarity, which contradicts to a polarity of a voltage drain of the NMOS transistor taught by paragraph 0060.
Appropriate corrections are required.
Claim Objections
Claims 2- 3 are objected to because of the following informalities:
Claim 2 recites (lines 6-7): “a global gate electrode disposed on the global active pattern, and which overlaps the global channel region”. Examiner suggests changing the recitation to: “a global gate electrode disposed on the global active pattern and overlaps the global channel region”, for simplicity of the statement.
Claim 3 contains a bracket in the beginning of the claim; the bracket shall be removed.
Appropriate corrections are required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-6 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
In re Claim 1: Claim 1 recites: “a global transistor which provides a first voltage which decreases over time”. The recitation is unclear, since Claim 1 and none Claims 2 through 6, dependent on Claim 1, does not clarify what “time” Claim 1 means, and, accordingly, the recitation leads to questions: Does “time” mean a single time period of the device operation? Does “time” mean a life span of a component? These “times” differ from each other in more than thousand times.
Appropriate correction is required to clarify the claim language.
For this Office Action, based on paragraph 0003 of the published application, describing “over time” as related to a life span of a component, the cited limitation of Claim 1 was interpreted as: “a first global transistor provides a first voltage which decreases over a life of the global transistor”.
In re Claims 2 and 5: Claim 2 recites: “a global gate electrode… receives a second voltage which has a negative polarity”, and Claim 5 recites: “an initialization drain terminal which receives a transistor initialization voltage, and wherein the second voltage is the transistor initialization voltage”, where paragraphs 0059-0060 of the published application teach that the initialization transistor T4 is an NMOS, and, accordingly, its drain voltage is positive (see an attached page 195 from Sze, NPL, related to voltages applied to an NMOS transistor and a PMOS transistor). Application of a positive initialization drain voltage to a global gate electrode would contradict with the above limitation of Claim 2 (describing a negative voltage applied to the gate of the global transistor), on which Claim 5 depends.
Appropriate correction is required to clarify the claim language.
For this Office Action, the cited limitation of Claim 5 was interpreted as: “an initialization drain terminal which receives a transistor initialization voltage”.
In re Claim 3: Claim 3 recites: (The display device of claim 1, wherein the voltage supply line”. There is a lack of antecedent basis in the cited limitation due to use of article “the” with: “voltage supply line”, since Claim 1, on which Claim 3 depends, does not recite: “a voltage supply line” – Claim 2 has this recitation.
Appropriate correction is required to clarify the claim language.
For this Office Action, the cited limitation was interpreted as: “The display device of claim 2, wherein the voltage supply line”.
In re Claim 4: Claim 4 recites (lines 2-3): “a light emitting diode electrically connected to the driving transistor and which receives a low power voltage”. The recitation is not quite clear with respect to what element receives a low power voltage – a light emitting diode or the driving transistor.
Appropriate correction is required to clarify the claim language.
For this Office Action, based on the specification of the application, the cited limitation was interpreted as: “a light emitting diode electrically connected to the driving transistor and receives a low power voltage”.
In re Claims 2 and 6: Claims 2 and 6 are rejected under 35 U.S.C. 112(b) due to dependency on Claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
As far as the claims are understood, Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Yoon et al. (US 2021/0272521) in view of Priel et al. (US 2014/0002160).
In re Claim 1, Yoon teaches a display device (Title, Abstract) comprising (Figs. 6 and 9):
a substrate 110 (paragraph 0120);
a driving transistor T1 (paragraph 0120) including an active pattern 130 (paragraph 0121) disposed on the substrate 110 (as in Fig. 6) and including a channel region (paragraphs 0018, 0120, inherently disposed between source and drain regions of the active pattern 130) a gate electrode 155 (paragraph 0120) disposed on the active pattern 130 and overlapping the channel region in a plan view, and a back-gate pattern M1-1 (paragraph 0119) disposed under the active pattern 130 and overlapping the active pattern 130 in the plan view; and
a global transistor T8 (Fig. 7, paragraph 0052) which provides a first voltage to the back-gate pattern M1 (paragraph 0185).
Yoon does not teach, at least, explicitly, that the first voltage submitted to the back-gate M1 by T8 is decreases over time. However, Yoon teaches that all transistors in Fig. 9 are MOSFETs (as having a gate, a source, a drain, and a channel, paragraphs 0018, 0092).
Priel teaches (paragraph 0003) that MOSFETs are aging over time, which leads to decrease of a drain current.
Yoon and Priel teach analogous arts directed to MOSFETs, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in modifying/understanding the Yoon device in view of the Priel teaching, since they are from the same field of endeavor, and Priel refers to a commonly known phenomenon of MOSFETs.
In view of Priel, one of ordinary skill in the art before the effective date of filing the application would understand that the global transistor of Yoon is aging, which leads to decrease of its drain current, and, as a result, to a decrease of a voltage generated on a back-gate pattern of the Yoon device.
Allowable Subject Matter
Claim 2 contains allowable subject matter, and would be allowed if amended to incorporate all limitations of Claim 1, corrected to avoid grounds for rejections under 35 U.S.C. 112(b).
Reason for Indicating Allowable Subject Matter
Re Claim 2: The prior arts of record, alone or in combination, do not anticipate and do not render obvious such limitations as: “a global source region electrically connected to a voltage supply line which provides a third voltage which has a positive polarity” and “a global gate electrode… which… receives a second voltage which has a negative polarity”, in combination with other limitations of Claim 2, and in combination with all limitations of Claim 1 corrected to overcome grounds for rejection under 35 U.S.C. 112(b). Polarities cited by Claim 2 are appropriate for a P-type MOSFET, but Yoon does not teach, at least, explicitly, that this is the case. Other prior arts of record, including: Miyake (US 2021/0167096), Chen et al. (US 2018/0268,757), Chen (US 2022/0415273), Cho et al. (US 2021/0027719), Cha et al. (US 2021/0043139), Ota (JP 2009063607), Park et al. (US 2011/0273419), Seo et al. (US 2020/0402464), or Lee (US 2020/0243017) – do not cure the above deficiency.
Conclusion
Any inquiry concerning this communication should be directed to GALINA G YUSHINA whose telephone number is 571-270-7440. The Examiner can normally be reached between 8 AM - 7 PM Pacific Time (Flexible).
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/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 02/04/26