Prosecution Insights
Last updated: August 17, 2026
Application No. 18/526,872

DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

Final Rejection §103§112
Filed
Dec 01, 2023
Priority
Dec 30, 2019 — RE 10-2019-0178412 +1 more
Examiner
BELL, LAUREN R
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
2 (Final)
40%
Grant Probability
Moderate
3-4
OA Rounds
8m
Est. Remaining
72%
With Interview

Examiner Intelligence

Grants 40% of resolved cases
40%
Career Allowance Rate
154 granted / 384 resolved
-27.9% vs TC avg
Strong +31% interview lift
Without
With
+31.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
52 currently pending
Career history
453
Total Applications
across all art units

Statute-Specific Performance

§103
43.8%
+3.8% vs TC avg
§102
16.1%
-23.9% vs TC avg
§112
35.1%
-4.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 384 resolved cases

Office Action

§103 §112
DETAILED ACTION Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim(s) 1-5 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 1, the limitation “providing a substrate comprising a pixel circuit layer comprising a plurality of transistors, a first partition wall and a second partition wall on the pixel circuit layer, each of the first and second partition walls having a shape protruding in a thickness direction, and a first electrode and a second electrode respectively on the first partition wall and the second partition wall” is unclear as to which of the elements recited after “a substrate comprising a pixel circuit layer” are required to be a part of the substrate and as to which of the elements recited after “a pixel circuit layer comprising a plurality of transistors” are also required to be a part of the “pixel circuit layer.” It is further unclear as to what element is intended to comprise “a first partition wall and a second partition wall” and “a first electrode and a second electrode.” Regarding claim 5, the limitation “further comprising etching the semiconductor layer,” is unclear as to how it is related to the “etching process” recited in claim 3. Note the dependent claims necessarily inherit the indefiniteness of the claims on which they depend. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 20190244567; herein “Cho”) in view of Misaki et al. (US 20130063675; herein “Misaki”). Regarding claim 1, Cho disclosed in Figs. 6-16 and related text a method of manufacturing a display device, the method comprising: providing a substrate comprising a pixel circuit layer (e.g. PCL) comprising a plurality of transistors (Ts and Td), a first partition wall and a second partition wall (PW left and PW right) on the pixel circuit layer, each of the first and second partition walls having a shape protruding in a thickness direction, and a first electrode and a second electrode (e.g. EL1_2 and EL1_1) respectively on the first partition wall and the second partition wall; arranging a light emitting element (LD1) between the first electrode and the second electrode; forming a second contact electrode (e.g. CNE1_1) contacting the second electrode and a first end of the light emitting element; and disposing a semiconductor layer (e.g. SCL) over the first electrode (EL1_1) and the second electrode (EL1_2), and to contact a second end of the light emitting element and the second contact electrode (e.g. electrical contact to right end of LD1 through DE and CNE2). Cho does not explicitly disclose disposing the semiconductor layer to cover the first electrode the second electrode. In the same field of endeavor, Misaki teaches in Fig. 7-8 a method manufacturing a display device comprising blanket depositing a semiconductor layer to cover all of the underlying layers (see [0008] and [0110]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Cho by having blanket depositing a semiconductor layer to cover all of the underlying layers in order to employ a well-known and common patterning method of a semiconductor layer for forming a TFT using conventional photolithography, thereby providing simplified manufacture and reduced cost. The limitation “disposing the semiconductor layer to cover the first electrode and the second electrode” is therefore taught by the blanket deposition of the semiconductor layer covering all of the underlying layers, as shown by Misaki, and the semiconductor layer being over the first electrode and the second electrode, as shown by Cho. Regarding claim 2, Cho further discloses forming a first contact electrode (e.g. DE2 of Td) on the semiconductor layer. Regarding claim 3, Cho further discloses further comprising performing an etching process (e.g. etching for SE/DE of Ts, see “etching the interlayer insulating material” [0031] and Figs. 16-17) after the forming of the first contact electrode. Regarding claim 4, the combined method shows wherein the etching process comprises a dry etching process (Misaki: [0118]). Additionally, it would have been obvious to one of ordinary skill in the art to modify the method by employing dry etching for the purpose of choosing from a finite number of identified, predictable solutions (i.e. dry or wet etching), with a reasonable expectation of success (KSR International Co. v. Teleflex Inc. 82 USPQ2d 1385 (2007)). Response to Arguments Applicant's arguments filed 5/14/2026 have been fully considered but they are not persuasive. Applicant argues (page 4-5) that Cho and Misaki do not teach or suggest the claimed invention because the semiconductor layer (SCL) of Cho does not contact a second end of the light emitting element and the second contact electrode. In response, the examiner disagrees. Specifically, the Examiner notes that in accordance with MPEP 2111, USPTO personnel are to give claims their broadest reasonable interpretation in light of the supporting disclosure. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023, 1027-28 (Fed. Cir. 1997). Therefore the claim limitation “contact” has been given its broadest reasonable interpretation and does not require a direct physical contact. Accordingly, Cho teaches the limitation in that there is, e.g., electrical contact between the elements. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LAUREN R BELL/Primary Examiner, Art Unit 2896
Read full office action

Prosecution Timeline

Dec 01, 2023
Application Filed
Feb 18, 2026
Non-Final Rejection mailed — §103, §112
May 14, 2026
Response Filed
Jul 14, 2026
Final Rejection mailed — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12701831
LIGHT EMITTING DIODE PACKAGE AND LIGHT EMITTING APPARATUS COMPRISING THE SAME
5y 7m to grant Granted Aug 04, 2026
Patent 12696605
DISPLAY DEVICE AND MANUFACTURING METHOD THEREFOR
3y 6m to grant Granted Jul 28, 2026
Patent 12690222
INNER SPACER LINER FOR GATE-ALL-AROUND DEVICE
2y 7m to grant Granted Jul 21, 2026
Patent 12684905
LIGHT-EMITTING DEVICE, MANUFACTURING METHOD THEREOF AND DISPLAY APPARATUS
2y 6m to grant Granted Jul 14, 2026
Patent 12672278
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
2y 6m to grant Granted Jun 30, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
40%
Grant Probability
72%
With Interview (+31.4%)
3y 5m (~8m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 384 resolved cases by this examiner. Grant probability derived from career allowance rate.

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