Prosecution Insights
Last updated: April 19, 2026
Application No. 18/526,872

DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

Non-Final OA §103§112
Filed
Dec 01, 2023
Examiner
BELL, LAUREN R
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
1 (Non-Final)
40%
Grant Probability
At Risk
1-2
OA Rounds
3y 7m
To Grant
70%
With Interview

Examiner Intelligence

Grants only 40% of cases
40%
Career Allow Rate
148 granted / 375 resolved
-28.5% vs TC avg
Strong +31% interview lift
Without
With
+30.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
61 currently pending
Career history
436
Total Applications
across all art units

Statute-Specific Performance

§103
42.1%
+2.1% vs TC avg
§102
19.7%
-20.3% vs TC avg
§112
33.1%
-6.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 375 resolved cases

Office Action

§103 §112
DETAILED ACTION Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim(s)1-5 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 1, the claim is indefinite for the recitation of “[a] method of manufacturing a display device, the display device comprising a pixel circuit layer comprising a plurality of transistors, a first partition wall and a second partition wall on the pixel circuit layer, each of the first and second partition walls having a shape protruding in a thickness direction, and a first electrode and a second electrode respectively on the first partition wall and the second partition wall, the method comprising” because it is unclear as to what constitutes the preamble and as to if each of the elements of display device are required by the claim. Regarding claim 5, the limitation “further comprising forming a semiconductor pattern overlapping the first contact electrode by etching the semiconductor layer,” is unclear as to how it is related to the “etching process” previously recited. Note the dependent claims necessarily inherit the indefiniteness of the claims on which they depend. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 20190244567; herein “Cho”) in view of Misaki et al. (US 20130063675; herein “Misaki”). Regarding claim 1, Cho disclosed in Figs. 6-16 and related text a method of manufacturing a display device, the display device comprising a pixel circuit layer (e.g. PCL) comprising a plurality of transistors (Ts and Td), a first partition wall and a second partition wall (PW left and PW right) on the pixel circuit layer, each of the first and second partition walls having a shape protruding in a thickness direction, and a first electrode and a second electrode (e.g. EL1_2 and EL1_1) and respectively on the first partition wall and the second partition wall, the method comprising: arranging a light emitting element (LD1) between the first electrode and the second electrode; forming a second contact electrode (e.g. CNE1_1) contacting the second electrode and a first end of the light emitting element; and disposing a semiconductor layer (e.g. SCL) over the first electrode (EL1_1), the second electrode (EL1_2), and the second contact electrode (top layer of CNE1_1). Cho does not explicitly disclose disposing the semiconductor layer to cover the first electrode, the second electrode, and the second contact electrode. In the same field of endeavor, Misaki teaches in Fig. 7-8 a method manufacturing a display device comprising blanket depositing a semiconductor layer to cover all of the underlying layers (see [0008] and [0110]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Cho by having blanket depositing a semiconductor layer to cover all of the underlying layers in order to employ a well-known and common patterning method of a semiconductor layer for forming a TFT using conventional photolithography, thereby providing simplified manufacture and reduced cost. The limitation “disposing the semiconductor layer to cover the first electrode, the second electrode, and the second contact electrode” is therefore taught by the blanket deposition of the semiconductor layer covering all of the underlying layers, as shown by Misaki, and the semiconductor layer being over the first electrode, the second electrode, and the second contact electrode, as shown by Cho. Regarding claim 2, Cho further discloses forming a first contact electrode (e.g. DE2 of Td) on the semiconductor layer. Regarding claim 3, Cho further discloses further comprising performing an etching process (e.g. etching for SE/DE of Ts, see “etching the interlayer insulating material” [0031] and Figs. 16-17) after the forming of the first contact electrode. Regarding claim 4, the combined method shows wherein the etching process comprises a dry etching process (Misaki: [0118]). Additionally, it would have been obvious to one of ordinary skill in the art to modify the method by employing dry etching for the purpose of choosing from a finite number of identified, predictable solutions (i.e. dry or wet etching), with a reasonable expectation of success (KSR International Co. v. Teleflex Inc. 82 USPQ2d 1385 (2007)). Regarding claim 5, the combined method shows comprising forming a semiconductor pattern overlapping the first contact electrode by etching the semiconductor layer (Misaki: [0008] and [0111]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LAUREN R BELL/Primary Examiner, Art Unit 2896 2/12/2026
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Prosecution Timeline

Dec 01, 2023
Application Filed
Feb 12, 2026
Non-Final Rejection — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604518
SEMICONDUCTOR DEVICE
2y 5m to grant Granted Apr 14, 2026
Patent 12588472
VIA ACCURACY MEASUREMENT
2y 5m to grant Granted Mar 24, 2026
Patent 12581934
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
2y 5m to grant Granted Mar 17, 2026
Patent 12575197
PHOTONIC STRUCTURE AND METHODS OF MANUFACTURING
2y 5m to grant Granted Mar 10, 2026
Patent 12563957
DISPLAY DEVICE
2y 5m to grant Granted Feb 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
40%
Grant Probability
70%
With Interview (+30.7%)
3y 7m
Median Time to Grant
Low
PTA Risk
Based on 375 resolved cases by this examiner. Grant probability derived from career allow rate.

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