7DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 16 is objected to because of the following informalities: In claim 16, line 10, “and a second portion and is connected” should read “and a second portion connected”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Glass et al. (2022/0093790).
Re claim 1, Glass teaches a multi-gate switch field effect transistor, FET, (Fig. 3) comprising: a semiconductor structure (202); a source contact (230) on the semiconductor structure (202); a drain contact (234) on the semiconductor structure (202); a first gate (208) on the semiconductor structure (202) between the source contact (230) and the drain contact (234); a second gate (302) on the semiconductor structure (202) adjacent to the first gate (208) and between the source contact (230) and the drain contact (234); and a conducting region (250) in the semiconductor structure (202) between the first gate (208) and the second gate (302).
Re claim 7, Glass teaches the multi-gate switch FET of claim 1, wherein the conducting region (250) is positioned between a first portion (“upper portion”) of the semiconductor structure (202) and a second portion (“lower portion”) of the semiconductor structure (202).
Claim(s) 16 and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Glass et al. (2022/0093790).
Re claim 16, Glass teaches a multi-gate switch field effect transistor, FET, (Fig. 3) comprising: a semiconductor structure (202); a source contact (230) on the semiconductor structure (202); a drain contact (234) on the semiconductor structure (202); a first gate (208) on the semiconductor structure (202) between the source contact (230) and the drain contact (234); a second gate (302) on the semiconductor structure (202) adjacent to the first gate (208) and between the source contact (230) and the drain contact (234); and a first conducting region (250) in the semiconductor structure (202) comprising a first portion (Fig. 3) positioned between the first gate (208) and the second gate (302) and a second portion (Fig. 3) connected to at least one of a ground, the source contact (230), and the drain contact (234).
Re claim 25, Glass teaches the multi-gate switch FET of claim 16, wherein the first conducting region (250) is positioned between a first portion (“upper portion”) of the semiconductor structure (202) and a second portion (“lower portion”) of the semiconductor structure (202).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Glass et al. (2022/0093790) in view of Nagumo et al. (2016/0056145).
Re claim 2, Glass teaches the multi-gate switch FET of claim 1.
Glass does not explicitly teach wherein the conducting region comprises an N-plus material.
Nagumo teaches a HEMT (Fig. 1) wherein a conducting region (CH) comprises an N-plus material (“n-AlGaN”, [77]).
Therefore, it would have been obvious to one of ordinary skill in the art as of the effective filling date of the claimed invention to modify Glass as taught by Naumo since all claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to a skilled artisan at the time the invention was made. Re claim 3, Glass teaches the multi-gate switch FET of claim 1.
Glass does not explicitly teach wherein the conducting region comprises a Group III nitride doped with at least one of silicon (Si) and germanium (Ge).
Nagumo teaches a HEMT (Fig. 1) wherein a conducting region (CH) comprises a Group III nitride (“n-AlGaN”, [77]) doped with at least one of silicon (Si) (“Si”, [77]).
Therefore, it would have been obvious to one of ordinary skill in the art as of the effective filling date of the claimed invention to modify Glass as taught by Naumo since all claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to a skilled artisan at the time the invention was made.
Re claim 4, Glass teaches the multi-gate switch FET of claim 1.
Glass does not explicitly teach wherein the conducting region comprises a Group III nitride implanted with at least one of silicon (Si) and germanium (Ge).
Nagumo teaches a HEMT (Fig. 1) wherein a conducting region (CH) comprises a Group III nitride (“n-AlGaN”, [77]) implanted with at least one of silicon (Si) [82].
Therefore, it would have been obvious to one of ordinary skill in the art as of the effective filling date of the claimed invention to modify Glass as taught by Naumo since all claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to a skilled artisan at the time the invention was made. Claim(s) 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Glass et al. (2022/0093790) in view of Bisi et al. (2023/0299190).
Re claim 5, Glass teaches the multi-gate switch FET of claim 1. Glass does not explicitly teach wherein the conducting region comprises a regrowth N-plus layer of gallium nitride (GaN).
Bisi teaches a HEMT (Figs. 2 and 4D) wherein a conducting region comprises a regrowth N-plus layer of gallium nitride (GaN) [67].
Therefore, it would have been obvious to one of ordinary skill in the art as of the effective filling date of the claimed invention to modify Glass as taught by Bisi since all claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to a skilled artisan at the time the invention was made.
Re claim 6, Glass teaches the multi-gate switch FET of claim 1.
Glass does not explicitly teach wherein the conducting region comprises an N-plus material and an ohmic metal on the N-plus material.
Bisi teaches a HEMT (Figs. 2 and 4D) wherein a conducting region comprises an N-plus material and an ohmic metal on the N-plus material [67].
Therefore, it would have been obvious to one of ordinary skill in the art as of the effective filling date of the claimed invention to modify Glass as taught by Bisi since all claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to a skilled artisan at the time the invention was made. Claim(s) 15 is rejected under 35 U.S.C. 103 as being unpatentable over Glass et al. (2022/0093790) in view of the following reasons.
Re claim 15, Glass teaches the multi-gate switch FET of claim 1.
Glass does not explicitly teach wherein the conducting region has a sheet resistance in a range from about 30 ohms per square to about 200 ohms per square.
However, the following claim limitation is drawn to a method of use or a device under test “the conducting region has a sheet resistance in a range from about 30 ohms per square to about 200 ohms per square”, intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In re Casey,152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). In this case the structure is capable of performing this use.
Claim(s) 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over Glass et al. (2022/0093790) in view of Nagumo et al. (2016/0056145).
Re claim 20, Glass teaches the multi-gate switch FET of claim 16.
Glass does not explicitly teach wherein the first conducting region comprises an N-plus material.
Nagumo teaches a HEMT (Fig. 1) wherein a conducting region (CH) comprises an N-plus material (“n-AlGaN”, [77]).
Therefore, it would have been obvious to one of ordinary skill in the art as of the effective filling date of the claimed invention to modify Glass as taught by Naumo since all claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to a skilled artisan at the time the invention was made.
Re claim 21, Glass teaches the multi-gate switch FET of claim 16. Glass does not explicitly teach wherein the first conducting region comprises a Group III nitride doped with at least one of silicon (Si) and germanium (Ge).
Nagumo teaches a HEMT (Fig. 1) wherein a conducting region (CH) comprises a Group III nitride (“n-AlGaN”, [77]) doped with at least one of silicon (Si) (“Si”, [77]).
Therefore, it would have been obvious to one of ordinary skill in the art as of the effective filling date of the claimed invention to modify Glass as taught by Naumo since all claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to a skilled artisan at the time the invention was made.
Re claim 22, Glass teaches the multi-gate switch FET of claim 16. Glass does not explicitly teach wherein the first conducting region comprises a Group III nitride implanted with at least one of silicon (Si) and germanium (Ge).
Nagumo teaches a HEMT (Fig. 1) wherein a conducting region (CH) comprises a Group III nitride (“n-AlGaN”, [77]) implanted with at least one of silicon (Si) [82].
Therefore, it would have been obvious to one of ordinary skill in the art as of the effective filling date of the claimed invention to modify Glass as taught by Naumo since all claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to a skilled artisan at the time the invention was made.
Claim(s) 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Glass et al. (2022/0093790) in view of Bisi et al. (2023/0299190).
Re claim 23, Glass teaches the multi-gate switch FET of claim 16.
Glass does not explicitly teach wherein the first conducting region comprises a regrowth N-plus layer of gallium nitride (GaN).
Bisi teaches a HEMT (Figs. 2 and 4D) wherein a conducting region comprises a regrowth N-plus layer of gallium nitride (GaN) [67].
Therefore, it would have been obvious to one of ordinary skill in the art as of the effective filling date of the claimed invention to modify Glass as taught by Bisi since all claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to a skilled artisan at the time the invention was made.
Re claim 24, Glass teaches the multi-gate switch FET of claim 16. Glass does not explicitly teach wherein the first conducting region comprises an N-plus material and an ohmic metal on the N-plus material.
Bisi teaches a HEMT (Figs. 2 and 4D) wherein a conducting region comprises an N-plus material and an ohmic metal on the N-plus material [67].
Therefore, it would have been obvious to one of ordinary skill in the art as of the effective filling date of the claimed invention to modify Glass as taught by Bisi since all claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to a skilled artisan at the time the invention was made.
Claim(s) 33 is rejected under 35 U.S.C. 103 as being unpatentable over Glass et al. (2022/0093790) in view of the following reasons.
Re claim 33, Glass teaches the multi-gate switch FET of claim 16. Glass does not explicitly teach wherein the conducting region has a sheet resistance in a range from about 30 ohms per square to about 200 ohms per square.
However, the following claim limitation is drawn to a method of use or a device under test “the conducting region has a sheet resistance in a range from about 30 ohms per square to about 200 ohms per square”, intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In re Casey,152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). In this case the structure is capable of performing this use.
Allowable Subject Matter
Claims 8-14, 17-19 and 26-32 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Re claim 8, Glass teaches the multi-gate switch FET of claim 7, further comprising: a first portion (“lower portion”) of a dielectric material (260) on the semiconductor structure (202), the first portion (“lower portion”) of the dielectric material (260) having a first length (Fig. 3) that extends from a first edge of the source contact (230) to a first edge of the first gate (208), yet remains explicitly silent to a second portion of the dielectric material on the conducting region and on the first and second portions of the semiconductor substrate, the second portion of the dielectric material comprising (i) a second length that extends from a second edge of the first gate to a first edge of the conducting region, (ii) a third length that extends from the first edge of the conducting region to a second edge of the conducting region, and (iii) a fourth length that extends from the second edge of the conducting region to a second edge of the second gate; and a third portion of the dielectric material on the semiconductor substrate, the third portion of the dielectric material having a fifth length that extends from a first edge of the drain contact to a first edge of the second gate.
Claims 9-14 are objected to for at least depending from objected claim 8.
Re claim 17, Glass teaches the multi-gate switch FET of claim 16, yet remains explicitly silent to wherein the second portion of the first conducting region is connected to the ground.
Re claim 18, Glass teaches the multi-gate switch FET of claim 16, wherein the first gate (208) comprises a first gate finger (Fig. 3), the second gate (302) comprises a second gate finger (Fig. 3), yet remains explicitly silent to and the second portion of the first conducting region is positioned under at least one of the first gate finger and the second gate finger. Re claim 19, Glass teaches the multi-gate switch FET of claim 16, yet remains explicitly silent to further comprising: a third gate on the semiconductor structure adjacent to the second gate and between the source contact and the drain contact; and a second conducting region in the semiconductor structure comprising at least a third portion positioned between the second gate and the third gate. Re claim 26, Glass teaches the multi-gate switch FET of claim 25, further comprising: a first portion (“lower portion”) of a dielectric material (260) on the semiconductor structure (202), the first portion (“lower portion”) of the dielectric material (260) having a first length (Fig. 3) that extends from a first edge of the source contact (230) to a first edge of the first gate (208), yet remains explicitly silent to a second portion of the dielectric material on the conducting region and on the first and second portions of the semiconductor substrate, the second portion of the dielectric material comprising (i) a second length that extends from a second edge of the first gate to a first edge of the conducting region, (ii) a third length that extends from the first edge of the conducting region to a second edge of the conducting region, and (iii) a fourth length that extends from the second edge of the conducting region to a second edge of the second gate; and a third portion of the dielectric material on the semiconductor substrate, the third portion of the dielectric material having a fifth length that extends from a first edge of the drain contact to a first edge of the second gate.
Claims 27-32 are objected to for at least depending from objected claim 26.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM S BOWEN whose telephone number is (571)272-3984. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/ADAM S BOWEN/Examiner, Art Unit 2897
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