Prosecution Insights
Last updated: April 19, 2026
Application No. 18/527,703

FLAT SEMICONDUCTOR PACKAGE WITH COPLANAR LEADS

Non-Final OA §102§103
Filed
Dec 04, 2023
Examiner
SANDVIK, BENJAMIN P
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Panjit International Inc.
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
2y 8m
To Grant
82%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allow Rate
874 granted / 1142 resolved
+8.5% vs TC avg
Moderate +6% lift
Without
With
+6.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
25 currently pending
Career history
1167
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
60.5%
+20.5% vs TC avg
§102
25.2%
-14.8% vs TC avg
§112
6.7%
-33.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1142 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liao (U.S. Pub #2014/0299978). With respect to claim 1, Liao teaches a flat semiconductor package comprising: a die pad (Fig. 5, 30) having a top surface and a bottom surface; a die (Fig. 5, 20) attached on the top surface of the die pad; multiple leads (Figs. 5-6, 40) distributed around the die pad and electrically connected to the die, each lead having a top surface, a bottom surface, two opposite side surfaces, and an end surface; and an encapsulant layer (Fig. 5-6, 50 and Paragraph 36) covering the die pad, the die and a portion of each lead, the encapsulant layer having a top surface, a bottom surface and four side surfaces (Fig. 6, four sides of square shape); wherein all of the top surface, the bottom surface, the four side surfaces of the encapsulant layer are flat surfaces (Figs. 5-6, 50); the four side surfaces of the encapsulant layer are perpendicular to the top surface and the bottom surface of the encapsulant layer (Fig. 5-6, 50); and the multiple leads (Fig. 5-6, 40) laterally protrude from the encapsulant (Fig. 5-6, 50) layer without being bent. With respect to claim 2, Liao teaches that the encapsulant layer has a substantial flat cuboid configuration (Fig. 5-6, 50); and the bottom surfaces of the multiple leads (Fig. 5, 40), the bottom surface of the encapsulant layer and the bottom surface of the die pad (Fig. 5, 30) are coplanar. With respect to claim 3, Liao teaches that the multiple leads are electrically connected to the die through conductive wires (Fig. 5, unlabeled; Fig. 1, 5). Claims 1-3, 5-7, and 9-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al (U.S. Pub #2022/0246501). With respect to claim 1, Yu teaches a flat semiconductor package comprising: a die pad (Figs. 7-10, 210) having a top surface and a bottom surface; a die attached on the top surface of the die pad (Paragraph 155); multiple leads (Fig. 7-10, 220) distributed around the die pad and electrically connected to the die, each lead having a top surface, a bottom surface, two opposite side surfaces, and an end surface; and an encapsulant layer (Fig. 7-10, 230 and Paragraph 154) covering the die pad, the die and a portion of each lead, the encapsulant layer having a top surface, a bottom surface and four side surfaces; wherein all of the top surface, the bottom surface, the four side surfaces of the encapsulant layer are flat surfaces (Figs. 7-10, 230); the four side surfaces of the encapsulant layer are perpendicular to the top surface and the bottom surface of the encapsulant layer; and the multiple leads (Figs. 7-10, 220) laterally protrude from the encapsulant layer without being bent. With respect to claim 2, Yu teaches that the encapsulant layer has a substantial flat cuboid configuration (Figs. 7-10, 230); and the bottom surfaces of the multiple leads (Figs. 7-10, 220), the bottom surface of the encapsulant layer and the bottom surface of the die pad (Figs. 7-10, 210) are coplanar. With respect to claim 3, Yu teaches that the multiple leads are electrically connected to the die through conductive wires (Paragraph 200, “wire bonding between the semiconductor die and the protruding leads”). With respect to claim 5, Yu teaches that a tin layer (Fig. 9-10, 221 and Paragraph 158) is formed on the top surface, the bottom surface and the two opposite side surfaces of each lead; and the end surface (Figs. 9-10, 222 and Paragraph 155) of each lead is formed by cutting and not covered by the tin layer (Paragraph 156). With respect to claim 6, Yu teaches that a tin layer (Fig. 9-10, 221 and Paragraph 158) is formed on the top surface, the bottom surface and the two opposite side surfaces of each lead; and the end surface (Figs. 9-10, 222 and Paragraph 155) of each lead is formed by cutting and not covered by the tin layer (Paragraph 156). With respect to claim 7, Yu teaches that a tin layer (Fig. 9-10, 221 and Paragraph 158) is formed on the top surface, the bottom surface and the two opposite side surfaces of each lead; and the end surface (Figs. 9-10, 222 and Paragraph 155) of each lead is formed by cutting and not covered by the tin layer (Paragraph 156). With respect to claim 9, Yu teaches that the multiple leads (Figs. 7-10, 220) protrude from two opposite ones of the four side surfaces of the encapsulant layer (Figs. 7-10, 230). With respect to claim 10, Yu teaches that the multiple leads (Figs. 7-10, 220) protrude from two opposite ones of the four side surfaces of the encapsulant layer (Figs. 7-10, 230). With respect to claim 11, Yu teaches that the multiple leads (Figs. 7-10, 220) protrude from two opposite ones of the four side surfaces of the encapsulant layer (Figs. 7-10, 230). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 4, 8, 12, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Yu, in view of Tsui et al (U.S. Pub #2013/0017652). With respect to claim 4, Yu does not teach that the multiple leads are electrically connected to the die through conductive clips. Tsui teaches a flat package, wherein multiple leads (Fig. 8A, 224) are electrically connected to the die through conductive clips (Fig. 8A, 228 and 232). It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to electrically connect the die of Yu to the multiple leads through clips as taught by Tsui in order to reduce the resistance of the connection (Paragraph 104). With respect to claim 8, Yu teaches that a tin layer (Fig. 9-10, 221 and Paragraph 158) is formed on the top surface, the bottom surface and the two opposite side surfaces of each lead; and the end surface (Figs. 9-10, 222 and Paragraph 155) of each lead is formed by cutting and not covered by the tin layer (Paragraph 156). With respect to claim 12, Yu teaches that the multiple leads (Figs. 7-10, 220) protrude from two opposite ones of the four side surfaces of the encapsulant layer (Figs. 7-10, 230). With respect to claim 17, Yu does not depict the thickness of the die pad, and hence does not explicitly disclose that each of the multiple leads and the die pad have the same thickness. Tsui teaches that each of the multiple leads and the die pad have the same thickness (Fig. 8A, 224). It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to form the die pad and multiple leads of Yu to have the same thickness as taught by Tsui in order to allow the die pad to conduct heat (Paragraph 137). Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Yu, in view of Do et al (U.S. Pub #2009/0127680). With respect to claim 13, Yu does not teach a metal heat dissipation layer is formed over the top surface of the encapsulant layer. Do teaches a metal heat dissipation layer (Fig. 12, 1204) is formed over the top surface of the encapsulant layer (Fig. 12, 1202). It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide a heat dissipation layer over the top surface of the encapsulant layer of Yu as taught by Do in order to enhance thermal transfer (Paragraph 94). With respect to claim 14, Yu does not teach a metal heat dissipation layer is formed over the top surface of the encapsulant layer. Do teaches a metal heat dissipation layer (Fig. 12, 1204) is formed over the top surface of the encapsulant layer (Fig. 12, 1202). It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide a heat dissipation layer over the top surface of the encapsulant layer of Yu as taught by Do in order to enhance thermal transfer (Paragraph 94). With respect to claim 15, Yu does not teach a metal heat dissipation layer is formed over the top surface of the encapsulant layer. Do teaches a metal heat dissipation layer (Fig. 12, 1204) is formed over the top surface of the encapsulant layer (Fig. 12, 1202). It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide a heat dissipation layer over the top surface of the encapsulant layer of Yu as taught by Do in order to enhance thermal transfer (Paragraph 94). Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Yu and Tsui, in view of Do et al (U.S. Pub #2009/0127680). With respect to claim 16, Yu does not teach a metal heat dissipation layer is formed over the top surface of the encapsulant layer. Do teaches a metal heat dissipation layer (Fig. 12, 1204) is formed over the top surface of the encapsulant layer (Fig. 12, 1202). It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide a heat dissipation layer over the top surface of the encapsulant layer of Yu as taught by Do in order to enhance thermal transfer (Paragraph 94). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN P SANDVIK whose telephone number is (571)272-8446. The examiner can normally be reached M-F: 10-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BENJAMIN P SANDVIK/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Dec 04, 2023
Application Filed
Feb 07, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
82%
With Interview (+6.0%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 1142 resolved cases by this examiner. Grant probability derived from career allow rate.

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