Prosecution Insights
Last updated: August 17, 2026
Application No. 18/527,714

SEMICONDUCTOR DEVICE AND METHODS OF FABRICATION THEREOF

Non-Final OA §112
Filed
Dec 04, 2023
Priority
Aug 04, 2023 — provisional 63/530,905
Examiner
CHANG, JAY C
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
568 granted / 667 resolved
+17.2% vs TC avg
Moderate +14% lift
Without
With
+14.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
32 currently pending
Career history
702
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
42.3%
+2.3% vs TC avg
§102
27.9%
-12.1% vs TC avg
§112
27.3%
-12.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 667 resolved cases

Office Action

§112
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This action is responsive to the following communications: the Amendment filed 6/23/2026. Claims 18-37 are pending. Claims 1-17 are cancelled. Claims 21-37 are new. Claims 18, 30 and 35 are independent. Information Disclosure Statement The information disclosure statements (IDS) submitted on 12/4/2023 and 3/31/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Election/Restrictions Applicant’s election without traverse of Group II in the reply filed on 6/23/2026 is acknowledged. Claims 1-17, which have been canceled, were drawn to a nonelected Group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/23/2026. Claim Objections Claims 18 and 32 are objected to because of the following informalities: Claim 18 recites the limitation “a second fin structures” in lines 2-3 of the claim, which appears to be a grammatical/typographical error, and thus, the Examiner suggests amending the limitation to “a second fin structure”. Claim 32 recites the limitation “prior to converting the base layer into the sacrificial layer” in lines 1-2 of the claim, which the Examiner suggests amending to “prior to converting at least a portion of the base layer into the sacrificial layer”, because it appears the claimed step was previously recited using that specific language. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 18-29 and 37 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 18 recites the limitation “the exposed portion” (singular form) in line 17 of the claim, which is indefinite and unclear, because the claim previously introduces “to expose portions” (plural form) in line 16 of the claim, and thus it is unclear which specific “exposed portion” element is being referenced in the limitation “the exposed portion” in line 17 of the claim. Claim 37 recites “a sidewall of a bottommost dielectric spacer” in lines 2-3 of the claim, however “a sidewall of a bottommost dielectric spacer” element was already introduced earlier in lines 20-21 of claim 35, which claim 37 depends from, and thereby it is unclear whether the “a sidewall of a bottommost dielectric spacer” in lines 2-3 of the claim is directed to that same element and therefore should be properly amended to “the a sidewall of the bottommost dielectric spacer” or directed to an entirely different element and therefore should be amended with specific language to distinguish it from the already introduced element. Note the dependent claims 19-29 necessarily inherit the indefiniteness of the claims on which they depend. Allowable Subject Matter Claims 18-29 would be allowable if rewritten or amended to overcome the objected subject matter and/or the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action. Regarding independent claim 18, Lee et al. (US 2021/0126135 A1, hereinafter “Lee”) discloses a method for forming a semiconductor device structure, comprising: depositing a sacrificial gate structure 124 (“dummy gate structures”- ¶0024) over a portion of a first fin structure 112 (“fin structure”- ¶0016) and a second fin structures 114 (“fin structure”- ¶0016) formed from a substrate 100 (“substrate”- ¶0009), wherein each first and second fin structure 112, 114 comprises a plurality of first semiconductor layers 108 (“semiconductor layers”- ¶0011) and a plurality of second semiconductor layers 106 (“semiconductor layers”- ¶0011) alternatingly stacked (see Fig. 9A); removing portions of the first and second fin structures 1124, 114 not covered by the sacrificial gate structure 124 to form a recess R1 (“recesses”- ¶0028) on opposite sides of the sacrificial gate structure 124 (see Fig. 13B); forming a base layer 145 (“layers”- ¶0036) on a portion of a top surface of the substrate 100 exposed through the recess R1, wherein the base layer 145 comprises a first material (¶0036) (see Fig. 19B); converting the base layer 145 into a supporting layer 145’ (“oxidized layers”- ¶0040) (¶0040) (see Fig, 21B); forming a source/drain (S/D) layer 162 (“source/drain epitaxial layers”- ¶0043) on the supporting layer 145’ (see Fig. 23B) removing the plurality of second semiconductor layers 106 to expose portions of first semiconductor layers 108 of the first and second fin structures 112, 114, since 106 is removed (¶0059) (see Figs. 31B-32B); and forming a gate electrode layer 170 (“metal gate structures”- ¶0059) to surround at least the exposed portion of one of the plurality of first semiconductor layers 108 of the first and second fin structures 112, 114 (see Fig. 32B). Lee does not expressly disclose converting the base layer into a supporting layer by treating the base layer with plasma or a radical of species generated from a second material and wherein the S/D layer covers a top portion of the supporting layer so that an air gap is formed between a bottom surface of the S/D layer and the top surface of the substrate. Thus, regarding independent claim 18 (which claims 19-29 depend from), the prior art of record including Lee, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “converting the base layer into a supporting layer by treating the base layer with plasma or a radical of species generated from a second material” and “wherein the S/D layer covers a top portion of the supporting layer so that an air gap is formed between a bottom surface of the S/D layer and the top surface of the substrate”. Claims 30-31 and 33-36 are allowed. Regarding independent claim 30, Lee discloses a method for forming a semiconductor device structure, comprising: forming a plurality of fin structures 112, 114 (“fin structure”- ¶0016) from a substrate 100 (“substrate”- ¶0009), each fin structure 112, 114 comprising a plurality of first semiconductor layers 106 (“semiconductor layers”- ¶0011) and a plurality of second semiconductor layers 108 (“semiconductor layers”- ¶0011) alternatingly stacked (see Fig. 2); forming a sacrificial gate structure 124 (“dummy gate structures”- ¶0024) over a portion of the plurality of fin structures 112, 114 (see Fig. 9A); removing portions of the plurality of fin structures 112, 114 not covered by the sacrificial gate structure 124 to form a recess R1 (“recesses”- ¶0028), and forming dielectric spacers 135 (“spacer layer”- ¶0031) between adjacent first semiconductor layers (see Figs. 13B-16B); forming a base layer 145 (“layers”- ¶0036) on exposed surfaces within the recess R1 using a bottom-up growth technique, wherein the base layer 145 on a top surface of the substrate 100 has a curved top surface profile (¶0036) (see Fig. 19B); converting at least a portion of the base layer 145 into a sacrificial layer 145’ (“oxidized layers”- ¶0040) by treating the base layer 145 with a nitridation process or an oxidation process (¶0040) (see Fig. 21B); forming an epitaxial source/drain feature 162 (“source/drain epitaxial layers”- ¶0043) on a supporting layer 145’ (see Fig. 23B). Lee does not expressly disclose wherein a gap is formed between the base layer adjacent a sidewall of a bottommost dielectric spacer and the base layer on the top surface of the substrate, removing the sacrificial layer from sidewall surfaces of the sacrificial gate structure to leave a supporting layer on the top surface of the substrate and wherein an air gap is formed at the gap between a bottom surface of the epitaxial source/drain feature and the top surface of the substrate. Thus, regarding independent claim 30, the claim is allowed, because the prior art of record including Lee, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “wherein a gap is formed between the base layer adjacent a sidewall of a bottommost dielectric spacer and the base layer on the top surface of the substrate”, “removing the sacrificial layer from sidewall surfaces of the sacrificial gate structure to leave a supporting layer on the top surface of the substrate” and “wherein an air gap is formed at the gap between a bottom surface of the epitaxial source/drain feature and the top surface of the substrate”. Claims 31 and 33-34 are allowed as being dependent on allowed claim 30. Regarding independent claim 35, Lee discloses a method for forming a semiconductor device structure, comprising: providing a substrate 100 (“substrate”- ¶0009) having a first fin structure 112 (“fin structure”- ¶0016) and a second fin structure 114 (“fin structure”- ¶0016), each comprising a plurality of first semiconductor layers 108 (“semiconductor layers”- ¶0011) and a plurality of second semiconductor layers 106 (“semiconductor layers”- ¶0011) alternatingly stacked (see Fig. 2); forming a sacrificial gate structure 124 (“dummy gate structures”- ¶0024) over a portion of the first and second fin structures 112, 114 (see Fig. 9A); removing portions of the first and second fin structures 112, 114 not covered by the sacrificial gate structure 124 to form a recess R1 (“recesses”- ¶0028) on opposite sides of the sacrificial gate structure 124 (see Fig. 13B); forming a liner 140 (“liner”- ¶0034) on exposed surfaces of the first and second fin structures 112, 114 and the substrate 100 (see Fig. 17B); forming a base layer 145 (“layers”- ¶0036) on a bottom surface of the liner 140, wherein the base layer 145 on a top surface of the substrate 100 has a rounded head or curved top surface profile (see Fig. 19B); converting the base layer 145 into a supporting layer 145’ (“oxidized layers”- ¶0040), wherein the supporting layer 145’ comprises an oxide or a nitride (¶0040) (see Fig, 21B); forming an epitaxial source/drain feature 162 (“source/drain epitaxial layers”- ¶0043) on the supporting layer 145’ (see Fig. 23B); removing the plurality of second semiconductor layers 106 (¶0059) (see Figs. 31B-32B); and forming a gate electrode layer 170 (“metal gate structures”- ¶0059) to surround at least a portion of each of the plurality of first semiconductor layers 108 (see Fig. 32B). Lee does not expressly disclose removing the supporting layer from sidewall surfaces of the sacrificial gate structure and the first and second fin structures while leaving the supporting layer on the top surface of the substrate and wherein an air gap is formed between a bottom surface of the epitaxial source/drain feature, a sidewall of a bottommost dielectric spacer, a sidewall of the supporting layer, and the top surface of the substrate. Thus, regarding independent claim 35, the claim is allowed, because the prior art of record including Lee, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “removing the supporting layer from sidewall surfaces of the sacrificial gate structure and the first and second fin structures while leaving the supporting layer on the top surface of the substrate” and “wherein an air gap is formed between a bottom surface of the epitaxial source/drain feature, a sidewall of a bottommost dielectric spacer, a sidewall of the supporting layer, and the top surface of the substrate”. Claim 36 is allowed as being dependent on allowed claim 35. Claim 32 (which depends from allowed claim 30) would be allowable if rewritten or amended to overcome the objected subject matter set forth in this Office action. Claim 37 (which depends from allowed claim 35) would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Lin et al. (US 2020/0395237 A1), which discloses a method for forming a semiconductor device structure comprising forming a base layer in a recess between fin structures. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAY C CHANG/ Primary Examiner, Art Unit 2817
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Prosecution Timeline

Dec 04, 2023
Application Filed
Jul 28, 2026
Non-Final Rejection mailed — §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
99%
With Interview (+14.0%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 667 resolved cases by this examiner. Grant probability derived from career allowance rate.

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