DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of the device of claims 1-13 and 21-27 in the reply filed on 2/11/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-7, 23 and 25-26 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KIM (US 20210375722).
Regarding claim 1, KIM discloses a device, comprising:
a plurality of source/drain regions (source/drain regions 110, see fig 1-3, para 25);
a plurality of source/drain contacts (the contacts 180A on each 110, see fig 1-3, para 47) disposed over a front side of the plurality of source/drain regions (180A is above a top side of 110 on which it is directly disposed, see fig 2), respectively, wherein the plurality of the source/drain contacts are electrically coupled to the plurality of source/drain regions (180A is directly connected to 110, see fig 2); and
a plurality of conductive vias (the vias comprising 180B, 120 and 250, see fig 1-3, para 47, 33 and 35) disposed over a back side of the source/drain contacts (if fig 2 where inverted, then 255 would be above a bottom side of 110 opposite to the side where 180 is disposed, see fig 2), respectively, wherein the back side is opposite the front side, and wherein the plurality of the conductive vias are electrically coupled to the plurality of source/drain contacts (180B, 120 and 250 are electrically connected to 180A, see fig 2).
Regarding claim 2, KIM discloses the device of claim 1, further comprising an interconnect structure (the wiring structures V1 and M1 over 180A, see fig 1-3, para 49) disposed over the front side of the source/drain contacts.
Regarding claim 3, KIM discloses the device of claim 1, wherein at least one of the conductive vias extends vertically through a semiconductor material (250 extends through 101 and 102, see fig 2, para 23).
Regarding claim 4, KIM discloses the device of claim 1, wherein at least one of the conductive vias extends vertically through a shallow trench isolation (STI) structure (120 extends through 162, see fig 2, para 29).
Regarding claim 5, KIM discloses the device of claim 4, wherein the at least one of the conductive vias is a first conductive via (the left via 250 in fig 2), wherein the device further comprises a second conductive via (the right via 120 in fig 2) that is disposed over the back side of one of the source/drain regions (if the device is inverted, then 120 would be above a bottom surface of 110, see fig 2);
wherein:
the second conductive via is electrically coupled to the one of the source/drain regions (120 is at least indirectly in electrical contact with 180A, see fig 2); and
the first conductive via and the second conductive via are electrically coupled together (120 and 250 are electrically coupled, see fig 2).
Regarding claim 6, KIM discloses the device of claim 1, wherein:
a first conductive via of the conductive vias (the left via 250, see fig 2, 120 and 250, para 35) extends vertically through a semiconductor material (250 extends through 101 and 102, see fig 2, para 23) and is electrically coupled to a first source/drain contact of the source/drain contacts (the left via 250 is electrically coupled to the left 180A, see fig 2); and
a second conductive via of the conductive vias (the right via 120, see fig 2, para 33) extends vertically through a shallow trench isolation (STI) structure (120 extends through 162, see fig 2, para 30) and is electrically coupled to a second source/drain contact of the source/drain contacts (120 is at least indirectly electrically coupled to the right 180A, see fig 2, para 33).
Regarding claim 7, KIM discloses the device of claim 6, wherein the first conductive via is substantially longer than the second conductive via (the first conductive via comprising 120 and 250 must be longer than the second via comprising 120, see fig 2).
Regarding claim 23, KIM discloses a device, comprising:
a first source/drain (the source/drain region 110 under the lower-left contact 180 in fig 1, see fig 1-3, para 25 and 47), a second source/drain (the source/drain region 110 under the upper-left contact 180 in fig 1, see fig 1-3, para 25 and 47), a third source/drain (the source/drain region 110 under the upper-right contact 180 in fig 1, see fig 1-3, para 25 and 47), and a fourth source/drain (the source/drain region 110 under the lower-right contact 180 in fig 1, see fig 1-3, para 25 and 47);
a first source/drain contact disposed over a front side of the first source/drain (the contact 180 disposed over the upper surface of the lower-left 110 in fig 1, see fig 1-3, para 25 and 47);
a second source/drain contact disposed over the front side of the second source/drain and the third source/drain (the upper conductor M1 in fig 1 which will be over and in electrical contact with both upper source/drains 110 in fig 1, see fig 1-3, para 25, 27 and 49);
a third source/drain contact disposed over the front side of the fourth source/drain (the contact 180 disposed over the upper surface of the lower-right 110 in fig 1, see fig 1-3, para 25 and 47);
a first conductive via disposed over a backside of the first source/drain contact and electrically coupled to the first source/drain contact (the via comprising 120 and 250 connected to the underside of the lower-left contact 180 in fig 1, see fig 1-3, para 43, 44 and 35);
a second conductive via disposed over the back side of the second source/drain contact and electrically coupled to the second source/drain contact (the via comprising 120 connected to the underside of the upper-left contact 180 in fig 1, see fig 1-3, para 43, 44 and 35, which will be in electrical contact with M1 via 180 and V1); and
a third conductive via disposed over the back side of the third source/drain contact and electrically coupled to the third source/drain contact (the via comprising 120 and 250 connected to the underside of the lower-right contact 180 in fig 1, see fig 1-3, para 43, 44 and 35).
Regarding claim 25, KIM discloses the device of claim 23, wherein at least one of the first (the first via comprising 120 and 250 extends through STI 162 and semiconductor 102 and 103, see fig 2, para 30), second, or third conductive vias extends vertically through a semiconductor material or a shallow trench isolation (STI) structure.
Regarding claim 26, KIM discloses the device of claim 23, wherein the second conductive via is substantially shorter than the first conductive via or the third conductive via (the second via comprising only 120 is shorter than the first via comprising 120 and 250, see fig 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIM (US 20210375722) in view of CHUANG (US 20210358891).
Regarding claim 8, KIM discloses the device of claim 1.
KIM fails to explicitly disclose a device, further comprising a gate structure, wherein at least one of the conductive vias is electrically coupled to both the gate structure and one of the source/drain contacts.
CHUANG discloses a device, further comprising a gate structure (gate comprising gate electrode 102, see fig 21D, para 13), wherein at least one of the conductive vias (the conductive via 106 connected to the s/d region 92, see fig 21D, para 13 and 65) is electrically coupled to both the gate structure and one of the source/drain contacts (118 couples 102 to 106 by means of 114, see fig 21D, para 65).
KIM and CHUANG are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KIM with the via in contact with the gate of CHUANG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KIM with the via in contact with the gate of CHUANG in order to improve performance (see CHUANG para 45).
Regarding claim 27, KIM discloses the device of claim 23.
KIM fails to explicitly disclose a device, further comprising a gate structure, wherein at least one of the first, second, or third conductive vias is electrically coupled to both the gate structure and one of the first, second, or third source/drain contacts.
CHUANG discloses a device, further comprising a gate structure (gate comprising gate electrode 102, see fig 21D, para 13), wherein at least one of the first, second, or third conductive vias (the conductive via 106 connected to the s/d region 92, see fig 21D, para 13 and 65) is electrically coupled to both the gate structure and one of the first, second, or third source/drain contacts (118 couples 102 to 106 by means of 114, see fig 21D, para 65).
KIM and CHUANG are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KIM with the via in contact with the gate of CHUANG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KIM with the via in contact with the gate of CHUANG in order to improve performance (see CHUANG para 45).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIM (US 20210375722) in view of CHUANG (US 20210358891) and further in view of HARAN (US 20220415795).
Regarding claim 9, KIM and CHUANG disclose the device of claim 8.
KIM and CHUANG fail to explicitly disclose a device, wherein at least one of the conductive vias has a cross-sectional side view profile that resembles a letter "L".
HARAN discloses a device, wherein at least one of the conductive vias has a cross-sectional side view profile that resembles a letter "L" (115 has an L-shape in the cross-section in fig 1A, see para 23).
KIM, CHUANG and HARAN are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KIM and CHUANG with the L-shaped via of HARAN because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KIM and CHUANG with the L-shaped via of HARAN in order to reduce cell size and increase density (see HARAN para 24).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIM (US 20210375722) in view of HARAN (US 20220415795).
Regarding claim 9, KIM 1 discloses the device of claim 1.
KIM fails to explicitly disclose a device, wherein the device comprises a gate-all-around (GAA) transistor.
HARAN discloses a device, wherein the device comprises a gate-all-around (GAA) transistor (the device of fig 1 has nanoribbon channels 124 with wrap around gates 183, see fig 1, para 25).
KIM and HARAN are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KIM with the L-shaped via of HARAN because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KIM with the L-shaped via of HARAN in order to reduce cell size and increase density (see HARAN para 24).
Claim(s) 11-13 and 21-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over LIAO (US 20210336063) in view of WEI (US 20230067354).
Regarding claim 11, KIM discloses a device, comprising:
a semiconductor substrate (fig 22, 54, para 14);
a gate structure (fig 14 and 22, 104, para 15) located over a first side of the semiconductor substrate in a cross- sectional side view (104 is located over 54, see fig 14 and 22);
a first epi-layer (left layer 92/92P, see fig 22, para 73) and a second epi-layer (right layer 92, see fig 22, para 73) each located over the first side of the semiconductor substrate in the cross-sectional side view (92 are located over 92, see fig 14 and 22), wherein the gate structure is located between the first epi-layer and the second epi-layer in the cross-sectional side view (there is a gate 104 between the epi structures 92, see fig 14 and 22);
a first conductive contact (left contact 112A, see fig 22, para 66) and a second conductive contact (right contact 112A, see fig 22, para 66) located over the first side of the first epi-layer and the second epi-layer, respectively, wherein the first conductive contact protrudes into the first epi-layer in the cross-sectional side view (the left contact 112A is above and protrudes into the left 92, see fig 22), and wherein the second conductive contact protrudes into the second epi-layer in the cross-sectional side view (the right contact 112A is above and protrudes into the right 92, see fig 22); and
a conductive via (fig 22, 112C and 144, para 22 and 89) located over a second side of the gate structure (in fig 22, 112C extends to a higher level than the gate, see fig 22), the second side being opposite the first side, wherein a first segment of the conductive via extends vertically through the semiconductor substrate (the segment of via 112C that extends vertically between 92 and 144, see fig 22), and wherein a second segment of the conductive via extends vertically through the second epi-layer and is in direct contact with the second conductive contact (the segment of 122C extends through and vertically overlapping with 92 to be in direct contact with 112A, see fig 89).
KIM fails to explicitly disclose a device wherein a first segment of the conductive via extends vertically through the semiconductor substrate and protrudes into the gate structure.
WEI discloses a device wherein a first segment of the conductive via (fig 1, 122a and 120, para 29) extends vertically through the semiconductor substrate (122a extends through 101, see fig 1A, para 20) and protrudes into the gate structure (12- protrudes into 116a, see fig 1, para 29).
KIM and WEI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KIM with the conductive via contacting the gate of WEI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KIM with the conductive via contacting the gate of WEI in order so that the conductive material seamlessly transitions between contacting the conductive layers and the buried conductive layers to electrically tie the gate electrodes of the corresponding semiconductor devices to buried power rails (see WEI para 71).
Regarding claim 12, KIM and WEI disclose the device of claim 11.
KIM further discloses a device, wherein the gate structure is a gate structure of a gate-all-around (GAA) transistor (the channel 68 is surrounded by the gate 104, see fig 14, para 40 and 15).
Regarding claim 13, KIM and WEI disclose the device of claim 11.
KIM further discloses a device, further comprising an interconnect structure located over the first side of the gate structure, the first conductive contact, and the second conductive contact (124 and 132, see fig 22, para78-79).
Regarding claim 21, KIM and WEI disclose the device of claim 11.
KIM further discloses a device, wherein the first segment of the conductive via has a greater lateral dimension than the second segment of the conductive via in the cross-sectional side view (the segment of 112 that is vertically between 144 and 92 is wider than the section that overlaps vertically with 92, see fig 22).
Regarding claim 22, KIM and WEI disclose the device of claim 11.
KIM further discloses a device, wherein the first epi-layer and the second epi-layer have different geometric shapes in the cross-sectional side view (the left 92P and the right 92 have different shapes in fig 22).
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIM (US 20210375722) in view of LI (US 20240222229)).
Regarding claim 24, KIM discloses the device of claim 23.
KIM fails to explicitly disclose a device, further comprising an interconnect structure disposed over the front side of the first source/drain contact, the second source/drain contact, and the third source/drain contact.
LI discloses a device, further comprising an interconnect structure (the BEOL wiring layer 95 that is over 76-2F and 78, see fig 22, para 100-101) and disposed over the front side of the first source/drain contact, the second source/drain contact, and the third source/drain contact (95 is over 76-2 and 78, see fig 22).
KIM and LI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KIM with the upper interconnect structure of LI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KIM with the upper interconnect structure of LI in order to connect the different devices (see LI para 101).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811