DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3 and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LIAO (US 20210336063).
Regarding claim 1, LIAO discloses a device, comprising:
a plurality of source/drain regions (the epitaxial source/drain regions 92, see fig 22, para 15);
a plurality of source/drain contacts (the contact regions 108, see fig 22, para 64) disposed over a front side of the plurality of source/drain regions (108 are on the bottom surfaces of 92 in fig 22 and would be above 92 if fig 22 were inverted), respectively, wherein the plurality of the source/drain contacts are electrically coupled to the plurality of source/drain regions (92 and 108 are in direct contact, see fig 22); and
a plurality of conductive vias (the vias (the vias comprising 148 and the right 112A, see fig 22, para 66 and 94) disposed over a back side of the source/drain contacts (112A and 148 are disposed at least partially above a bottom side of 108 if fig 22 were inverted, see fig 22), respectively, wherein the back side is opposite the front side (the bottom side of 108 faces away from the bottom side of 92, see fig 22), and wherein the plurality of the conductive vias are electrically coupled to the plurality of source/drain contacts (112A and 148 are electrically connected to 108, see fig 22), and
wherein at least a first conductive via of the plurality of conductive vias extends vertically through, and has a greater vertical dimension than, at least one of the source/drain regions (148 extends entirely through and has a greater vertical extension than 92, see fig 22).
Regarding claim 2, LIAO discloses the device of claim 1, further comprising an interconnect structure disposed over the front side of the source/drain contacts (122 will be above 108 if fig 22 were inverted, see fig 22).
Regarding claim 3, LIAO discloses the device of claim 1, wherein at least the first conductive via extends vertically through a semiconductor material (148 extends vertically though fin 54, see fig 22).
Regarding claim 10, LIAO discloses the device of claim 1, wherein the device comprises a gate-all-around (GAA) transistor (the device can be GAAFET, see para 13).
Claim(s) 23-24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by XIE (US 20230411386).
Regarding claim 23, XIE discloses a device, comprising:
a first source/drain (the right bottom source/drain 300, see fig 48, para 115), a second source/drain (the left bottom source/drain 330, see fig 48, para 115), a third source/drain (the middle top source/drain 375, see fig 48, para 127), and a fourth source/drain (the middle bottom source/drain 330, see fig 48, para 115);
a first source/drain contact (the right source/drain contact 400, see fig 48, para 135) disposed over a front side of the first source/drain in a cross- sectional side view (400 is disposed over a top side of 330, see fig 48);
a second source/drain contact disposed over the front side of the second source/drain and the third source/drain in the cross-sectional side view (the shared source/drain contact 450 is above and connected to both the left 330 and the middle 375, see fig 48, para 138);
a third source/drain contact disposed over the front side of the fourth source/drain in the cross-sectional side view (the 400 over the middle 330, see fig 48, para 138);
a first conductive via disposed over a back side of the first source/drain contact in the cross-sectional side view and electrically coupled to the first source/drain contact (the via 417 directly on the right 400 is electrically connected to it and is over a bottom of 400, see fig 48, para 135);
a second conductive via disposed over the back side of the second source/drain contact in the cross-sectional side view and electrically coupled to the second source/drain contact (the via 417 directly on 450 is electrically connected to it and is over a bottom of 450, see fig 48, para 135); and
a third conductive via disposed over the back side of the third source/drain contact in the cross-sectional side view and electrically coupled to the third source/drain contact (the via 417 directly on the middle 400 is electrically connected to it and is over a bottom of 400, see fig 48, para 135).
Regarding claim 24, XIE discloses the device of claim 23, further comprising an interconnect structure (the interconnect structure comprising insulator 415 and the upper conductors 417, see fig 48, para 135) disposed over the front side of the first source/drain contact, the second source/drain contact, and the third source/drain contact.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 and 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over LIAO (US 20210336063).
Regarding claim 4, a first embodiment of LIAO discloses the device of claim 1.
The first embodiment of LIAO fails to explicitly disclose a device wherein at least a second conductive via of the plurality of conductive vias extends vertically through a shallow trench isolation (STI) structure.
A second embodiment of LIAO teaches a device wherein at least a second conductive via of the plurality of conductive vias extends vertically through a shallow trench isolation (STI) structure (112C, which is part of the right via 112A extends through STI layer 60, see fig 19A, para 14).
The two embodiments of LIAO are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of the first embodiment of LIAO with the via structure of the second embodiment of LIAO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of the first embodiment of LIAO with the via structure of the second embodiment of LIAO in order to increase the density of the gates and interconnects (see LIAO para 130).
Regarding claim 6, a first embodiment of LIAO discloses the device of claim 1, wherein:
the first conductive via further extends vertically through a semiconductor material and is electrically coupled to a first source/drain contact of the source/drain contacts (148 extends through fin 54 and is coupled to the left 108, see fig 22, para 14).
The first embodiment of LIAO fails to explicitly disclose a device wherein a second conductive via of the plurality of conductive vias extends vertically through a shallow trench isolation (STI) structure and is electrically coupled to a second source/drain contact of the source/drain contacts.
A second embodiment of LIAO teaches a device wherein a second conductive via of the plurality of conductive vias extends vertically through a shallow trench isolation (STI) structure (112C, which is part of the right via 112A extends through STI layer 60, see fig 19A, para 14) and is electrically coupled to a second source/drain contact of the source/drain contacts (the right via 112C is connected to the right source/drain contact 108, see fig 19A, para 64).
The two embodiments of LIAO are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of the first embodiment of LIAO with the via structure of the second embodiment of LIAO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of the first embodiment of LIAO with the via structure of the second embodiment of LIAO in order to increase the density of the gates and interconnects (see LIAO para 130).
Regarding claim 7, the embodiments of LIAO discloses the device of claim 6.
The first embodiment of LIAO further discloses to explicitly disclose a device, wherein the first conductive via is substantially longer than the second conductive via in a vertical dimension in a cross-sectional side view (148 has a longer extension in a vertical direction than the right 112A, see fig 22).
Claim(s) 5 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over LIAO (US 20210336063) in view of CHUANG (US 20210358889).
Regarding claim 5, LIAO discloses the device of claim 1, wherein
a second conductive via of the plurality of conductive vias is free of extending through any of the source/drain regions (the right via 112A does not extend through 92, see fig 22).
LIAO fails to explicitly disclose a device wherein the first conductive via and the second conductive via are electrically coupled together.
CHUANG teaches a device wherein the first conductive via and the second conductive via are electrically coupled together (two of the source/drain contact vias 112 are connected electrically by 118, see fig 30, para 94).
LIAO and CHUANG are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of LIAO with the via structure of CHUANG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of LIAO with the via structure of CHUANG in order to increase gate density (see CHUANG para 88).
Regarding claim 8, LIAO discloses the device of claim 1.
LIAO fails to explicitly disclose a device, further comprising a gate structure, wherein at least one of the conductive vias is electrically coupled to both the gate structure and one of the source/drain contacts.
CHUANG teaches a device, further comprising a gate structure (gate comprising gate electrode 102, see fig 21D, para 13), wherein at least one of the conductive vias (the conductive via 106 connected to the s/d region 92, see fig 21D, para 13 and 65) is electrically coupled to both the gate structure and one of the source/drain contacts (118 couples 102 to 106 by means of 114, see fig 21D, para 65).
LIAO and CHUANG are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of LIAO with the via structure of CHUANG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of LIAO with the via structure of CHUANG in order to increase gate density (see CHUANG para 88).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over LIAO (US 20210336063) in view of CHUANG (US 20210358889) and further in view of HARAN (US 20220415793).
Regarding claim 9, LIAO and CHUANG disclose the device of claim 8.
LIAO and CHUANG fail to explicitly disclose a device, wherein at least one of the conductive vias has a cross-sectional side view profile that resembles a letter "L".
HARAN teaches a device, wherein at least one of the conductive vias has a cross-sectional side view profile that resembles a letter "L" (115 has an L-shape in the cross-section in fig 1A, see para 23).
LIAO, CHUANG and HARAN are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of LIAO and CHUANG with the via shape of HARAN because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of LIAO and CHUANG with the via shape of HARAN in order to reduce cell size and increase density (see HARAN para 24).
Claim(s) 25-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over XIE (US 20230411386) in view of KIM (US 20210375722).
Regarding claim 25, XIE discloses the device of claim 23.
XIE fails to explicitly disclose a device, wherein at least one of the first, second, or third conductive vias extends vertically through a semiconductor material or a shallow trench isolation (STI) structure.
KIM teaches a device, wherein at least one of the first (the first via comprising 120 and 250 extends through STI 162 and semiconductor 102 and 103, see fig 2, para 30), second, or third conductive vias extends vertically through a semiconductor material or a shallow trench isolation (STI) structure.
XIE and KIM are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of XIE with the via structure of KIM because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of XIE with the via structure of KIM in order to improve the contact resistance (see KIM para 120).
Regarding claim 26, XIE discloses the device of claim 23.
XIE fails to explicitly disclose a device, wherein the second conductive via is substantially shorter than the first conductive via or the third conductive via.
KIM teaches a device, wherein the second conductive via is substantially shorter than the first conductive via or the third conductive via (the second via comprising only 120 is shorter than the first via comprising 120 and 250, see fig 3).
XIE and KIM are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of XIE with the via structure of KIM because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of XIE with the via structure of KIM in order to improve the contact resistance (see KIM para 120).
Claim(s) 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over XIE (US 20230411386) in view of CHUANG (US 20210358889).
Regarding claim 27, XIE discloses the device of claim 23.
XIE fails to explicitly disclose a device, further comprising a gate structure, wherein at least one of the first, second, or third conductive vias is electrically coupled to both the gate structure and one of the first, second, or third source/drain contacts.
CHUANG teaches a device, further comprising a gate structure (gate comprising gate electrode 102, see fig 21D, para 13), wherein at least one of the first, second, or third conductive vias (the conductive via 106 connected to the s/d region 92, see fig 21D, para 13 and 65) is electrically coupled to both the gate structure and one of the first, second, or third source/drain contacts (118 couples 102 to 106 by means of 114, see fig 21D, para 65).
XIE and CHUANG are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of XIE with the via structure of CHUANG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of XIE with the via structure of CHUANG in order to increase gate density (see CHUANG para 88).
Allowable Subject Matter
Claims 11-13 and 21-22 are allowed.
The following is an examiner’s statement of reasons for allowance: the prior art of record does not teach or suggest, singularly or in combination, at least “a semiconductor substrate; a gate structure located over a first side of the semiconductor substrate in a cross- sectional side view; a first epi-layer and a second epi-layer each located over the first side of the semiconductor substrate in the cross-sectional side view, wherein the gate structure is located between the first epi-layer and the second epi-layer in the cross-sectional side view; a first conductive contact and a second conductive contact located over the first side of the first epi-layer and the second epi-layer, respectively, wherein the first conductive contact protrudes into the first epi-layer in the cross-sectional side view, and wherein the second conductive contact protrudes into the second epi-layer in the cross-sectional side view; and a conductive via located over a second side of the gate structure, the second side being opposite the first side, wherein a first segment of the conductive via extends vertically through the semiconductor substrate and protrudes into the gate structure such that a bottom surface of the first segment of the conductive via extends to an internal portion of the gate structure, and wherein a second segment of the conductive via extends vertically through the second epi-layer and is in direct contact with the second conductive contact” as required by claim 11. This represents the main difference between the device of claim 11 and the cited prior art.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
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