DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-14 in the reply filed on 04/17/2026 is acknowledged.
Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II invention there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 4/17/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2016/0013138 to Chen et al. (hereinafter Chen).
With respect to claim 1, Chen discloses a semiconductor package (e.g., packaged semiconductor device, see the annotated Figs. 23 and 18 below) (Chen, Figs. 1, 15, 18, 23, ¶0030-¶0125), comprising:
an interconnect structure (120/120a) (Chen, Figs. 1, 15, 18, 23, ¶0039, ¶0041, ¶0076, ¶0088, ¶0106) comprising a plurality of vias (130) and a plurality of lines (128) stacked alternately and electrically connected to each other and embedded by a plurality of polymer layers (126) (Chen, Figs. 1, 15, 18, 23, ¶0041);
a plurality of first connectors (e.g., a plurality of contacts 124 between RDL 120a and the die 102) (Chen, Figs. 1, 15, 23, ¶0039, ¶0075, ¶0106, ¶0121) disposed on a first side of the interconnect structure (120/120a);
a die (102) (Chen, Figs. 1, 15, 23, ¶0039, ¶0088, ¶0106, ¶0121) bonded to the plurality of first connectors (124);
a plurality of second connectors (122) (Chen, Figs. 1, 15, 23, ¶0043-¶0044, ¶0079, ¶0092, ¶0125) disposed on a second side of the interconnect structure (120a);
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a circuit board (e.g., PCB) (Chen, Figs. 1, 15, 23, ¶0079, ¶0097, ¶0125) bonded to the plurality of second connectors (122); and
a mark structure (e.g., protection pattern 111 for aligning the package including conductive feature 112b, see the annotated Fig. 18 below) (Chen, Figs. 18, 23, ¶0099-¶0101, ¶0105-¶0115, ¶0121-¶0123) embedded in a first polymer layer (126d) (Chen, Fig. 18, ¶0106-¶0113) among the plurality of polymer layers (126a-126d) closest to the die (102) and electrically insulated from the plurality of vias (130), the plurality of lines (128) and the plurality of first connectors (124).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4, 6, 8-11, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0013138 to Chen in view of Yang et al. (US 20150362770, hereinafter Yang).
Regarding claim 2, Chen discloses the semiconductor package as claimed in claim 1. Further, Chen discloses the semiconductor package, wherein the mark structure (e.g., protection pattern 111 for aligning the package including conductive feature 112b) (Chen, Figs. 18, 23, ¶0106-¶0111, ¶0121-¶0122) is a stack of two patterns (112b/112a), but does not specifically disclose a stack of two patterns respectively formed of a reflective material and a transparent material, and orthogonal projections of the two patterns are the same.
However, Yang teaches forming alignment marks (122) (Yang, Fig. 10, ¶0053) as a stack of two patterns (122A/122B) comprising a reflective metal (e.g., copper) (122A) coated with transparent polymer (122B) or other dielectric material, wherein orthogonal projections of the two patterns(122A/122B) are the same, to minimize the reflectivity of mark to prevent the alignment marks from being visible.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Chen by forming the mark structure as a stack of two patterns as taught by Yang to have the semiconductor package, wherein a stack of two patterns respectively formed of a reflective material and a transparent material, and orthogonal projections of the two patterns are the same, in order to minimize the reflectivity of the alignment mark structure, and to prevent the alignment marks from being visible (Yang, ¶0053).
Regarding claim 3, Chen in view of Yang discloses the semiconductor package as claimed in claim 2. Further, Chen does not specifically disclose that the two patterns are a metal pattern and a polymer pattern, and the metal pattern is closer to the die than the polymer pattern.
However, Chen discloses that the metal pattern (112b) (Chen, Figs. 18, 23, ¶0106, ¶0121-¶0122) of the mark structure (e.g., 112b/112a) is closer to the die (e.g., closer to the molding material 116 surrounding the die 102 as in Figs. 18 and 23) than the polymer pattern (126c). Further, Yang teaches forming alignment marks (122) (Yang, Fig. 10, ¶0051, ¶0053) including a metal pattern (122A) and a polymer pattern (122B), and the metal pattern (122A) is closer to the structure (104) including integrated circuit.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Chen/Yang by forming the mark structure as a stack of two patterns as taught by Yang to have the semiconductor package, wherein the two patterns are a metal pattern and a polymer pattern, and the metal pattern is closer to the die than the polymer pattern, in order to minimize the reflectivity of the alignment mark structure, and to prevent the alignment marks from being visible (Yang, ¶0053).
Regarding claim 4, Chen in view of Yang discloses the semiconductor package as claimed in claim 3. Further, Chen discloses the semiconductor package, wherein a surface of the metal pattern (112b) (Chen, Figs. 18, 23, ¶0106, ¶0122) facing the die (e.g., facing the molding material 116 surrounding the die 102 as in Figs. 18 and 23) is leveled with a surface of the first polymer layer (126d) facing the die (102).
Regarding claim 6, Chen discloses the semiconductor package as claimed in claim 1. Further, Chen does not specifically disclose that the first polymer layer comprises a plurality of island-shaped patterns and a plurality of frame-shaped patterns in a chip region of the semiconductor package, and the plurality of island-shaped patterns are respectively surrounded by the plurality of frame-shaped patterns.
However, Yang teaches forming alignment marks (120 and 122) (Yang, Figs. 9-10, ¶0051-¶0053) as a stack of two patterns (e.g., 122A/122B) comprising a reflective metal (e.g., copper) (122A) coated with transparent polymer (122B) or other dielectric material, wherein the mark pattern (122) has a ring shape and surrounds the mask pattern (120) having island shape, to improve the alignment between the structures, and to minimize the reflectivity of mark to prevent the alignment marks from being visible.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Chen by forming the mark structure as a stack of two patterns and having the island shape and the ring shape as taught by Yang to have the semiconductor package, wherein the first polymer layer comprises a plurality of island-shaped patterns and a plurality of frame-shaped patterns in a chip region of the semiconductor package, and the plurality of island-shaped patterns are respectively surrounded by the plurality of frame-shaped patterns, in order to minimize the reflectivity of the alignment mark structure, to improve the alignment between the structures, and to prevent the alignment marks from being visible (Yang, ¶0051-¶0053).
With respect to claim 8, Chen discloses a semiconductor package (e.g., packaged semiconductor device, see the annotated Figs. 23 and 18 above) (Chen, Figs. 1, 15, 18, 23, ¶0030-¶0125), comprising:
an interconnect structure (120/120a) (Chen, Figs. 1, 15, 18, 23, ¶0039, ¶0041, ¶0076, ¶0088, ¶0106) comprising a plurality of vias (130) and a plurality of lines (128) stacked alternately and electrically connected to each other and embedded by a plurality of polymer layers (126) (Chen, Figs. 1, 15, 18, 23, ¶0041);
a plurality of first connectors (e.g., a plurality of contacts 124 between RDL 120a and the die 102) (Chen, Figs. 1, 15, 23, ¶0039, ¶0075, ¶0106, ¶0121) disposed on a first side of the interconnect structure (120/120a);
a die (102) (Chen, Figs. 1, 15, 23, ¶0039, ¶0088, ¶0106, ¶0121) bonded to the plurality of first connectors (124);
a plurality of second connectors (122) (Chen, Figs. 1, 15, 23, ¶0043-¶0044, ¶0079, ¶0092, ¶0125) disposed on a second side of the interconnect structure (120a);
a circuit board (e.g., PCB) (Chen, Figs. 1, 15, 23, ¶0079, ¶0097, ¶0125) bonded to the plurality of second connectors (122); and
a mark structure (e.g., protection pattern 111 for aligning the package including conductive feature 112b) (Chen, Figs. 18, 23, ¶0099-¶0101, ¶0105-¶0115, ¶0121-¶0123) embedded in a first polymer layer (126d) (Chen, Fig. 18, ¶0106-¶0113) among the plurality of polymer layers (126a-126d) closest to the die (102).
Further, Chen does not specifically disclose that the mark structure comprises a polymer pattern having a thickness smaller than a thickness of the first polymer layer.
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However, Yang teaches forming alignment marks (120 and 122, see the annotated Fig. 10 below) (Yang, Figs. 9-10, ¶0051-¶0053) as a stack of two patterns (e.g., 122A/122B) comprising a reflective metal (e.g., copper) (122A) coated with transparent polymer (122B) or other dielectric material, wherein the mark pattern (122) has a ring shape and surrounds the mask pattern (120), to minimize the reflectivity of mark, and to prevent the alignment marks from being visible.
Thus, a person of ordinary skill in the art would recognize that the mark structure of Chen embedded into the first polymer layer and comprising metal pattern covered with the polymer pattern as taught by Yang would have the polymer pattern having a thickness smaller than a thickness of the polymer layer.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Chen by forming the mark structure as a stack of two patterns as taught by Yang, wherein the mark structure including polymer pattern is embedded into the first polymer layer closest to the die of Chen to have the semiconductor package, wherein the mark structure comprises a polymer pattern having a thickness smaller than a thickness of the first polymer layer, in order to minimize the reflectivity of the alignment mark structure, and to prevent the alignment marks from being visible (Yang, ¶0053).
Regarding claim 9, Chen in view of Yang discloses the semiconductor package as claimed in claim 8. Further, Chen discloses the semiconductor package, wherein the mark structure (e.g., protection pattern 111 for aligning the package including conductive feature 112b) (Chen, Figs. 18, 23, ¶0106-¶0111, ¶0121-¶0122) further comprises a metal pattern (112b), but does not specifically disclose that orthogonal projections of the metal pattern and the polymer pattern are the same.
However, Yang teaches forming alignment marks (122) (Yang, Fig. 10, ¶0053) as a stack of two patterns (122A/122B) comprising a reflective metal (e.g., copper) (122A) coated with transparent polymer (122B) or other dielectric material, wherein orthogonal projections of the two patterns(122A/122B) are the same, to minimize the reflectivity of mark to prevent the alignment marks from being visible.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Chen/Yang by forming the mark structure as a stack of two patterns as taught by Yang to have the semiconductor package, wherein orthogonal projections of the metal pattern and the polymer pattern are the same, in order to minimize the reflectivity of the alignment mark structure, and to prevent the alignment marks from being visible (Yang, ¶0053).
Regarding claim 10, Chen in view of Yang discloses the semiconductor package as claimed in claim 9. Further, Chen discloses the semiconductor package, wherein a surface of the metal pattern (112b) (Chen, Figs. 18, 23, ¶0106, ¶0122) facing the die (e.g., facing the molding material 116 surrounding the die 102 as in Figs. 18 and 23) is leveled with a surface of the first polymer layer (126d) facing the die (102).
Regarding claim 11, Chen in view of Yang discloses the semiconductor package as claimed in claim 8. Further, Chen does not specifically disclose that the first polymer layer comprises a plurality of island-shaped patterns and a plurality of frame-shaped patterns in a chip region of the semiconductor package, and the plurality of island-shaped patterns are respectively surrounded by the plurality of frame-shaped patterns.
However, Yang teaches forming alignment marks (120 and 122) (Yang, Figs. 9-10, ¶0051-¶0053) as a stack of two patterns (e.g., 122A/122B) comprising a reflective metal (e.g., copper) (122A) coated with transparent polymer (122B) or other dielectric material, wherein the mark pattern (122) has a ring shape and surrounds the mask pattern (120) having island shape, to improve the alignment between the structures, and to minimize the reflectivity of mark to prevent the alignment marks from being visible.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Chen/Yang by forming the mark structure as a stack of two patterns and having the island shape and the ring shape as taught by Yang to have the semiconductor package, wherein the first polymer layer comprises a plurality of island-shaped patterns and a plurality of frame-shaped patterns in a chip region of the semiconductor package, and the plurality of island-shaped patterns are respectively surrounded by the plurality of frame-shaped patterns, in order to minimize the reflectivity of the alignment mark structure, to improve the alignment between the structures, and to prevent the alignment marks from being visible (Yang, ¶0051-¶0053).
Regarding claim 13, Chen in view of Yang discloses the semiconductor package as claimed in claim 8. Further, Chen discloses the semiconductor package, wherein the semiconductor package has a chip region (e.g., circuit mounting region 104) (Chen, Fig. 23, ¶0124) and a periphery region (e.g., perimeter 110) surrounding the chip region (104), and the mark structure (111) is located in the periphery region.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0013138 to Chen in view of Yang (US 20150362770) and Ohkawa et al. (US 2011/0042785, hereinafter Ohkawa).
Regarding claim 5, Chen discloses the semiconductor package as claimed in claim 1. Further, Chen does not specifically disclose that the mark structure comprises a polymer pattern, a surface of the polymer pattern facing the die is indented from a surface of the first polymer layer facing the die, and a surface of the polymer pattern facing away from the die is indented from a surface of the first polymer layer facing away from the die.
However, Yang teaches forming alignment marks (120 and 122) (Yang, Figs. 9-10, ¶0051-¶0053) as a stack of two patterns (e.g., 122A/122B) comprising a reflective metal (e.g., copper) (122A) coated with transparent polymer (122B) or other dielectric material, wherein the mark pattern (122) has a ring shape and surrounds the mask pattern (120), to minimize the reflectivity of mark, and to prevent the alignment marks from being visible.
Further, Ohkawa teaches the alignment mark pattern (18e) (Ohkawa, Figs. 2B, 3, ¶0002, ¶0006, ¶0015-¶0016, ¶0031, ¶0061-¶0071, ¶0079) in the interconnect layer structure (12/34) and the alignment mark structure including dielectric pattern (24d) (Ohkawa, Figs. 2B, 3, ¶0061-¶0071) surrounding the mark pattern (18e), wherein the dielectric pattern (24d) is formed in the step (19) of the first inter-layer (12) of the interconnect structure (12/34) such that a surface of the dielectric pattern (24d) facing the semiconductor devices of the substrate (10) is indented from a surface of the first inter-layer (12) facing the semiconductor devices of the substrate (10), and a surface of the dielectric pattern (24d) facing away from the semiconductor devices of the substrate (10) is indented from a surface of the first inter-layer (12) facing away from the semiconductor devices of the substrate (10), to provide multilayer interconnect structure having reduced resistance and to incorporate devices into the multilayer interconnect structure without impairing the reliability (Ohkawa, ¶0002, ¶0006, ¶0015-¶0016, ¶0031, ¶0061-¶0071, ¶0079).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Chen by forming the mark structure as a stack of two patterns including a polymer pattern as taught by Yang, wherein the alignment mark pattern is formed in the step of the first interlayer dielectric layer and including dielectric pattern surrounding the alignment mark pattern as taught by Ohkawa to have the semiconductor package, wherein the mark structure comprises a polymer pattern, a surface of the polymer pattern facing the die is indented from a surface of the first polymer layer facing the die, and a surface of the polymer pattern facing away from the die is indented from a surface of the first polymer layer facing away from the die, in order to minimize the reflectivity of the alignment mark structure, and to prevent the alignment marks from being visible; and to provide multilayer interconnect structure having reduced resistance and to incorporate devices into the multilayer interconnect structure without impairing the reliability (Yang, ¶0051-¶0053; Ohkawa, ¶0002, ¶0006, ¶0015-¶0016, ¶0031, ¶0061-¶0071, ¶0079).
Claims 7 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0013138 to Chen in view of Yang (US 20150362770) as applied to claim 6 (claim 11), and further in view of Ohkawa (US 2011/0042785).
Regarding claim 7, Chen in view of Yang discloses the semiconductor package as claimed in claim 6. Further, Chen does not specifically disclose that a thickness of the frame-shaped patterns is larger than a thickness of the island-shaped patterns, and a thickness of the mark structure is smaller than the thickness of the island-shaped patterns.
However, Ohkawa teaches the alignment mark pattern (18e) (Ohkawa, Figs. 2B, 3, ¶0002, ¶0006, ¶0015-¶0016, ¶0031, ¶0061-¶0071, ¶0079) in the interconnect layer structure (12/34), and the alignment mark structure including dielectric pattern (24d) (Ohkawa, Figs. 2B, 3, ¶0061-¶0071) surrounding the mark pattern (18e), wherein the dielectric pattern (24d) is formed in the step (19) of the first inter-layer (12) of the interconnect structure (12/34) such that a thickness of the dielectric pattern (24d) in the step (19) surrounding the mark pattern (18e) is larger than a thickness of the dielectric pattern (24d) above the mark pattern (18e), to provide multilayer interconnect structure having reduced resistance and to incorporate devices into the multilayer interconnect structure without impairing the reliability (Ohkawa, ¶0002, ¶0006, ¶0015-¶0016, ¶0031, ¶0061-¶0071, ¶0079).
Further, Yang teaches forming the ring-shape alignment mark (122) (Yang, Figs. 9-10, ¶0051-¶0053) to have a transparent polymer pattern (122B) or other dielectric material pattern having high index of refraction to reflect large amount of light form the upper surface of the ring-shape alignment mark (122), to reduce visibility of the mark structure.
Thus, Yang recognizes that a specific material of the ring-shape alignment mark pattern surrounding the mark structure impacts visibility of the mark structure. Thus, a specific material of the ring-shape alignment mark is a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, a specific material of the ring-shape alignment mark pattern as Yang has identified a specific material of the ring-shape alignment mark pattern as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at a specific material and a thickness of the ring-shape alignment mark pattern such that a thickness of the mark structure is smaller than the thickness of the island-shaped patterns, in order to reduce visibility of the mark structure as taught by Yang (¶0053) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Chen/Yang by optimizing material and thickness of the ring-shape alignment mark pattern as taught by Yang, wherein the alignment mark pattern is formed in the step of the first interlayer dielectric layer and including dielectric pattern surrounding the alignment mark structure as taught by Ohkawa to have the semiconductor package, wherein a thickness of the mark structure is smaller than the thickness of the island-shaped patterns., in order to reduce visibility of the mark structure and to provide multilayer interconnect structure having reduced resistance and to incorporate devices into the multilayer interconnect structure without impairing the reliability (Yang, ¶0051-¶0053; Ohkawa, ¶0002, ¶0006, ¶0015-¶0016, ¶0031, ¶0061-¶0071, ¶0079).
Regarding claim 12, Chen in view of Yang discloses the semiconductor package as claimed in claim 11. Further, Chen does not specifically disclose that a thickness of the frame-shaped patterns is larger than a thickness of the island-shaped patterns, and a thickness of the polymer pattern is smaller than the thickness of the island-shaped patterns.
However, Ohkawa teaches the alignment mark pattern (18e) (Ohkawa, Figs. 2B, 3, ¶0002, ¶0006, ¶0015-¶0016, ¶0031, ¶0061-¶0071, ¶0079) in the interconnect layer structure (12/34), and the alignment mark structure including dielectric pattern (24d) (Ohkawa, Figs. 2B, 3, ¶0061-¶0071) surrounding the mark pattern (18e), wherein the dielectric pattern (24d) is formed in the step (19) of the first inter-layer (12) of the interconnect structure (12/34) such that a thickness of the dielectric pattern (24d) in the step (19) surrounding the mark pattern (18e) is larger than a thickness of the dielectric pattern (24d) above the mark pattern (18e), to provide multilayer interconnect structure having reduced resistance and to incorporate devices into the multilayer interconnect structure without impairing the reliability (Ohkawa, ¶0002, ¶0006, ¶0015-¶0016, ¶0031, ¶0061-¶0071, ¶0079).
Further, Yang teaches forming the ring-shape alignment mark (122) (Yang, Figs. 9-10, ¶0051-¶0053) to have a transparent polymer pattern (122B) or other dielectric material pattern having high index of refraction to reflect large amount of light form the upper surface of the ring-shape alignment mark (122), to reduce visibility of the mark structure.
Thus, Yang recognizes that a specific material of the ring-shape alignment mark pattern surrounding the mark structure impacts visibility of the mark structure. Thus, a specific material of the ring-shape alignment mark is a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, a specific material of the ring-shape alignment mark pattern as Yang has identified a specific material of the ring-shape alignment mark pattern as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at a specific material and a thickness of the ring-shape alignment mark pattern such that a thickness of the polymer pattern is smaller than the thickness of the island-shaped patterns, in order to reduce visibility of the mark structure as taught by Yang (¶0053) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Chen/Yang by optimizing material and thickness of the ring-shape alignment mark pattern as taught by Yang, wherein the alignment mark pattern is formed in the step of the first interlayer dielectric layer and including dielectric pattern surrounding the alignment mark structure as taught by Ohkawa to have the semiconductor package, wherein a thickness of the polymer pattern is smaller than the thickness of the island-shaped patterns., in order to reduce visibility of the mark structure and to provide multilayer interconnect structure having reduced resistance and to incorporate devices into the multilayer interconnect structure without impairing the reliability (Yang, ¶0051-¶0053; Ohkawa, ¶0002, ¶0006, ¶0015-¶0016, ¶0031, ¶0061-¶0071, ¶0079).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0013138 to Chen in view of Yang (US 20150362770) as applied to claim 8, and further in view of Yu et al. (US 2021/0020574).
Regarding claim 14, Chen in view of Yang discloses the semiconductor package as claimed in claim 8. Further, Chen discloses the semiconductor package, wherein the interconnect structure (120) (Chen, Figs. 1, 23, ¶0039, ¶0041, ¶0076, ¶0088, ¶0106) comprises a first redistribution layer structure (120a), a plurality of conductive vias (106) (Chen, Fig. 23, ¶0121-¶0125), and a second redistribution layer structure (120b), and wherein: the plurality of conductive vias (106) are located between the first redistribution layer structure (120a) and the second redistribution layer structure (120b), the plurality of first connectors (124) are located between the first redistribution layer structure (120a) and the die (102), but does not specifically disclose a plurality of bridge dies, the plurality of bridge dies are located between the first redistribution layer structure and the second redistribution layer structure, and the plurality of second connectors are located between the second redistribution layer structure and the circuit board.
However, Yu teaches forming a package (Yu, Fig. 6, ¶0002, ¶0014, ¶0016-¶0040, ¶0058-¶0059) including a bridge die for interconnection to improve integration of package components and to obtain an integrated circuit package with increased functionality, wherein the plurality of bridge dies (26/32) (Yu, Fig. 6, ¶0018-¶0030) are located between the first redistribution layer structure (e.g., RDL 42) (Yu, Fig. 6, ¶0031) and the second redistribution layer structure (e.g., RDL 62) (Yu, Fig. 6, ¶0038), and the plurality of second connectors (64) (Yu, Fig. 6, ¶0038-¶0040) are located between the second redistribution layer structure (RDL 62) and the circuit board (68).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Chen/Yang by forming an integrated circuit package including a bridge die for interconnection as taught by Yu to have the semiconductor package, comprising: plurality of bridge dies, the plurality of bridge dies are located between the first redistribution layer structure and the second redistribution layer structure, and the plurality of second connectors are located between the second redistribution layer structure and the circuit board, in order to improve integration of package components and to obtain an integrated circuit package with increased functionality (Yu, ¶0002, ¶0014, ¶0018-¶0021, ¶0058-¶0059).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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