DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Foreign Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file, as electronically retrieved 02/02/2024.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/05/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Claims 12-19 and 22-24 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04/23/2026.
Applicant’s election without traverse of Invention I (clams 1-11 and 20-21) in the reply filed on 04/23/2026 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-8 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Lim (PG Pub 2021/0202541) and Kim et al. (PG Pub 2021/0335926; hereinafter Kim), Kim (PG Pub 2017/0329189; hereinafter Kim-2) and Kwon et al. (PG Pub 2015/0243722; hereinafter Kwon).
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Regarding claim 1, refer to the Examiner’s mark-up of Fig. 3a provided above, Lim teaches a display device comprising:
a substrate 110;
a first semiconductor layer 310 disposed on the substrate, the first oxide semiconductor layer comprising a channel region (center portion of 310), a source region (portion of 310 below 320), and a drain region (portion of 310 below 330), the source region and the drain region being spaced apart from each other with the channel region therebetween (see Fig. 3);
a first gate insulating layer 112 continuously disposed on the substrate and covering an upper surface of the first oxide semiconductor layer (see Fig. 3);
a second semiconductor layer 410 disposed on the first gate insulating layer, the second oxide semiconductor layer comprising a channel region (center portion of 410), a source region (portion of 410 below 420), and a drain region (portion of 410 below 430), the source region and the drain region being spaced apart from each other with the channel region therebetween (see Fig. 3); and
a second gate insulating layer 115 disposed to cover an upper surface of the second oxide semiconductor layer,
wherein the first gate insulating layer has a first thickness (a distance from a bottom surface of 112 to a top surface of 112) in a direction perpendicular to the substrate, the second gate insulating layer has a second thickness (a distance from a bottom surface of 115 to a top surface of 115) in a direction perpendicular to the substrate, and a difference between the first thickness and the second thickness is 500 Å or less.
Although, Lim teaches the first thickness of the first gate insulating layer and the second thickness of the second gate insulating layer (and their respective locations), he does not explicitly teach “a difference between the first thickness and the second thickness is 500 Å or less.”
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In the same field of endeavor, refer to the Examiner’s mark-up of Fig. 8 provided above, Kim teaches a display device comprising: a first gate insulating layer 113a; and a second gate insulating layer 113b; wherein the first gate insulating layer has a first thickness (a distance from a bottom surface of 113a to a top surface of 113a) in a direction perpendicular to the substrate (see Fig. 8), the second gate insulating layer has a second thickness (a distance from a bottom surface of 113b to a top surface of 113b) in a direction perpendicular to the substrate, and a difference between the first thickness and the second thickness is 500 Å or less (113a and 113b are substantially the same thickness. Therefore, the difference between the first thickness and the second thickness is 500 Å or less) (see Fig. 8).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first and second thickness’ be 500 Å or less (i.e. equal to one another), as taught by Kim, to simplify the manufacturing process.
Furthermore, one of ordinary skill in the art would have found it obvious to alter the first thickness to be less than, equal to, or greater than the second thickness since the court has held changes in size are considered routine expedients are discussed below (MPEP § 2144). According to MPEP § 2144.05(IV)(A) “[W]here the facts in a prior legal decision are sufficiently similar to those in an application under examination, the examiner may use the rationale used by the court. Examples directed to various common practices which the court has held normally require only ordinary skill in the art and hence are considered routine expedients are discussed below.” See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation), see Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree “will not sustain a patent”); and see In re Williams, 36 F.2d 436, 438 (CCPA 1929) (“It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions.”).
Although, Lim teaches the first and second active layer comprise a poly-silicon, he does not explicitly teach their material composition as comprising a metal oxide.
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In the same field of endeavor, refer to Fig. 6-provided above, Kim-2 teaches a Thin Film Transistor (TFT); wherein TFTs can be categorized into amorphous silicon (a-Si) TFTs using amorphous silicon (a-Si) as an active layer, polycrystalline silicon (poly-Si) TFTs using polycrystalline silicon (poly-Si) as an active layer, and oxide semiconductor TFTs using an oxide semiconductor as an active layer, based on a material of each active layer.
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have first semiconductor layer and the second oxide semiconductor layer comprise choose a polycrystalline silicon (poly-Si) or an oxide semiconductor material, for the active layer, as taught by Kim-2, for the purpose of choosing a suitable and well recognized active layer material composition.
Although, the combined invention teaches the active layers can comprise an oxide material composition they do not explicitly teach the material being a metal oxide.
In the same field of endeavor, Kwon teaches a transistor 1500 comprising: an active layer 1122; wherein the active layer comprises a metal oxide (para [0097]).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first oxide semiconductor layer (aka first active layer comprising ITGZO) and the second oxide semiconductor layer (aka second active layer comprising IGZO) comprise a metal oxide, as taught by Kwon, for the purpose of choosing a suitable and well know active layer material composition.
Regarding claim 2, refer to the figures cited above, in the combination of Lim, Kim, Kim-2 and Kwon teach the first gate insulating layer 112 is disposed to completely cover the upper surface of the first oxide semiconductor layer 310, and the second gate insulating layer 115 is disposed to completely cover the upper surface of the second oxide semiconductor layer 410 (see Fig. 3a).
Regarding claim 3, refer to the figures cited above, in the combination of Lim, Kim, Kim-2 and Kwon teach the first gate insulating layer 112 and the second gate insulating layer 115 include a same material as each other (para [0112] and [0092] respectively).
Regarding claim 4, refer to the figures cited above, in the combination of Lim, Kim, Kim-2 and Kwon teach the first oxide semiconductor layer 310-Lim and the second oxide semiconductor layer 410-Lim include different materials from each other (see Kwon-para [0097]).
Regarding claim 5, refer to the figures cited above, in the combination of Lim, Kim, Kim-2 and Kwon teach the first oxide semiconductor layer 310 and the second oxide semiconductor layer 410 comprise a poly-silicon (Poly-Si) material (para [0073]-Lim).
Regarding claim 6, refer to the figures cited above, in the combination of Lim, Kim, Kim-2 and Kwon teach the first oxide semiconductor layer 310 includes ITGZO (para [0097]-Kwon), and the second oxide semiconductor layer 410 includes IGZO (para [0097]-Kwon).
Regarding claim 7, refer to the figures cited above, in the combination of Lim, Kim, Kim-2 and Kwon teach a third oxide semiconductor layer 111 (para [0070]) disposed on the substrate 110 (see Fig. 3a).
Regarding claim 8, refer to the figures cited above, in the combination of Lim, Kim, Kim-2 and Kwon teach the third oxide semiconductor layer 111 includes an oxide material composition.
In the same field of endeavor, Kwon teaches an oxide material composition can comprise IGZO and/or ITGZO (para [0097]-Kwon).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the third oxide semiconductor layer comprise IGZO or ITGZO, as taught by Kwon, for the purpose of choosing a suitable and well-known oxide material composition.
Regarding claim 11, refer to the figures cited above, in the combination of Lim, Kim, Kim-2 and Kwon teach a first gate electrode 340 disposed on the first gate insulating layer 113 and overlapping the channel region (center of 310) of the first oxide semiconductor layer 310; and a second gate electrode 440 disposed on the second gate insulating layer 115 and overlapping the channel region of the second oxide semiconductor layer (center of 410).
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lim, Kim, Kim-2 and Kwon, as applied to claim 1 above, and further in view of Liu et al. (PG Pub 2019/0386083; hereinafter Liu).
Regarding claim 9, refer to the figures cited above, in the combination of Lim, Kim, Kim-2 and Kwon, Lim teaches the first oxide semiconductor layer 310 and the second oxide semiconductor layer 410; and Kwon teaches the material composition of the first oxide semiconductor layer 310 and the second oxide semiconductor layer comprise IGZO and a layer including ITGZO.
Lim does not teach that the first oxide semiconductor layer or the second oxide semiconductor layer has a structure in which a layer including IGZO and a layer including ITGZO are stacked.
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In the same field of endeavor, refer to Fig. 12-provided above, Liu teaches a transistor structure comprising: an oxide semiconductor layer 4 has a structure in which the oxide semiconductor layer stacked 41,42,42 (see Fig.12).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first or second oxide semiconductor layers comprise stacked layers of metal oxides selected form the list provide by Kwon (see para [0097]), as taught by Liu, for the purpose of choosing a suitable and well recognized oxide material composition.
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lim, Kim, Kim-2 and Kwon, as applied to claim 1 above, and further in view of Zhang et al. (PG Pub 2019/0109238; hereinafter Zhang.
Regarding claim 10, refer to the figures cited above, in the combination of Lim, Kim, Kim-2 and Kwon, Lim teaches the first oxide semiconductor layer and the second oxide semiconductor layer (see claim 1).
However, the combined invention does not teach the source region and the drain region of the first oxide semiconductor layer and the source region and the drain region of the second oxide semiconductor layer include doped ions.
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In the same field of endeavor, refer to Fig. 17 provided above, Zhang teaches a CMOS transistor 100 comprising: a first oxide semiconductor layer 30 disposed on a substrate 10, the first oxide semiconductor layer comprising a channel region (center), a source region 31, and a drain region 32, the source region and the drain region being spaced apart from each other with the channel region therebetween (see Fig. 17); wherein the source region and the drain region of the first oxide semiconductor layer and the source region and the drain region of the second oxide semiconductor layer include doped ions (see claim 11; “active layer is: depositing a metal oxide semiconductor thin film on the second gate insulating layer, etching the metal oxide semiconductor thin film to obtain the second active layer; wherein in the step S2, a P-type heavy doping is performed on the two ends of the first active layer by an ion implantation; and a P-type ions used by the P-type heavy doping is Boron ion.”)
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to adopt the method of forming the first oxide semiconductor layer of Lim, as taught by Zhang, for the purpose of utilizing a well-known method.
Claim(s) 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Lim (PG Pub 2021/0202541) and Kim (PG Pub 2017/0329189; hereinafter Kim-2) and Zhang et al. (PG Pub 2019/0109238; hereinafter Zhang.
Regarding claim 20, refer to the Examiner’s mark-up of Fig. 3a provided above, Lim teaches a display device comprising:
a substrate 110;
a first semiconductor layer 310 disposed on the substrate, the first oxide semiconductor layer comprising a channel region (center portion of 310), a source region (portion of 310 below 320), and a drain region (portion of 310 below 330), the source region and the drain region being spaced apart from each other with the channel region therebetween (see Fig. 3);
a first gate insulating layer 112 continuously disposed on the substrate and completely covering an upper surface of the first oxide semiconductor layer (see Fig. 3);
a second semiconductor layer 410 disposed on the first gate insulating layer, the second oxide semiconductor layer comprising a channel region (center portion of 410), a source region (portion of 410 below 420), and a drain region (portion of 410 below 430), the source region and the drain region being spaced apart from each other with the channel region therebetween (see Fig. 3); and
a second gate insulating layer 115 disposed to cover an upper surface of the second oxide semiconductor layer,
Although, Lim teaches the first and second active layer comprise a poly-silicon, he does not explicitly teach their material composition as comprising an oxide.
In the same field of endeavor, refer to Fig. 6-provided above, Kim-2 teaches a Thin Film Transistor (TFT); wherein TFTs can be categorized into amorphous silicon (a-Si) TFTs using amorphous silicon (a-Si) as an active layer, polycrystalline silicon (poly-Si) TFTs using polycrystalline silicon (poly-Si) as an active layer, and oxide semiconductor TFTs using an oxide semiconductor as an active layer, based on a material of each active layer.
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have first semiconductor layer and the second oxide semiconductor layer comprise choose a polycrystalline silicon (poly-Si) or an oxide semiconductor material, for the active layer, as taught by Kim-2, for the purpose of choosing a suitable and well recognized active layer material composition.
Although, the combined invention teaches an oxide base first and second semiconductor layer, they do not teach the source region and the drain region of the first oxide semiconductor layer and the source region and the drain region of the second oxide semiconductor layer include doped ions.
In the same field of endeavor, refer to Fig. 17 provided above, Zhang teaches a CMOS transistor 100 comprising: a first oxide semiconductor layer 30 disposed on a substrate 10, the first oxide semiconductor layer comprising a channel region (center), a source region 31, and a drain region 32, the source region and the drain region being spaced apart from each other with the channel region therebetween (see Fig. 17); wherein the source region and the drain region of the first oxide semiconductor layer and the source region and the drain region of the second oxide semiconductor layer include doped ions (see claim 11; “active layer is: depositing a metal oxide semiconductor thin film on the second gate insulating layer, etching the metal oxide semiconductor thin film to obtain the second active layer; wherein in the step S2, a P-type heavy doping is performed on the two ends of the first active layer by an ion implantation; and a P-type ions used by the P-type heavy doping is Boron ion.”)
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to adopt the method of forming the first oxide semiconductor layer of Lim, as taught by Zhang, for the purpose of utilizing a well-known method.
Regarding claim 21, refer to the figures cited above, in the combination of Lim, Kim-2 and Zhang Lim teaches a third oxide semiconductor layer 111 (para [0070]) disposed on the substrate 110 (see Fig. 3a).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christina A Sylvia whose telephone number is (571)272-7474. The examiner can normally be reached on 8am-4pm (M-F).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTINA A SYLVIA/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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