DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 7-11, and 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention and species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 3/10/26.
Response to Arguments
Applicant’s arguments, see Remarks, filed 7/13/26, with respect to the rejection(s) of claim(s) 1-6, 12-16 under 35 USC § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Hsieh and Arthur.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 12, 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2010/0075503 (Bencher) in view of U.S. Patent No. 5,202,272 (Hsieh) and WO Publication No. 2014/092936 (Arthur).
Bencher discloses
1. (Original) A method of manufacturing a semiconductor device, comprising:
providing a body 300 of semiconductor material ([0026]) comprising:
a top side;
a bottom side opposite to the top side; and
a first conductivity type ([0029]);
providing a mask 314B over the top side, the mask 314B comprising a side wall;
providing a conformal layer 320 over the top side and the mask 314B;
removing a portion of the conformal layer 320 to provide a first spacer 321 adjoining the side wall of the mask 314B ([0027]);
removing the mask 314B ([0028]);
removing the first spacer 321.
Bencher fails to disclose
providing a first feature as a first part of the body of semiconductor material self-aligned to a first side of the first spacer;
providing a second feature as a second part of the body of semiconductor material self-aligned to a second side of the first spacer, wherein a portion of the body of semiconductor material is laterally interposed between the first feature and the second feature; and
wherein:
the portion of the body of semiconductor material laterally interposed between the first feature and the second feature comprises a channel region of a JFET semiconductor device or a JFET region of an insulated gate field effect transistor device.
Hsieh teaches
A method comprising:
providing a first feature 44 as a first part of the body of semiconductor material 20 self-aligned to a first side of the first spacer 42;
providing a second feature 46 as a second part of the body of semiconductor material 20 self-aligned to a second side of the first spacer 20, wherein a portion of the body of semiconductor material 20 is laterally interposed between the first feature 44 and the second feature 46; and
wherein:
the portion of the body of semiconductor material 20 laterally interposed between the first feature 44 and the second feature 46 comprises a channel region of a FET semiconductor device or a FET region of an insulated gate field effect transistor device (Abstract).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide features self-aligned to a spacer in Bencher. The motivation would be to provide a symmetric free-standing spacer as a self-alignment mask for forming semiconductor regions to avoid a separate alignment step as taught by Hsieh (column 4, line 54 to column 6, line 2).
Arthur teaches
A method comprising:
wherein:
the portion of the body of semiconductor material 200 laterally interposed between the first feature 216 and the second feature 216 comprises a channel region 218 of a JFET semiconductor device or a JFET region of an insulated gate field effect transistor device ([0043]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide the portion of semiconductor material laterally interposed as a channel region of a JFET in Bencher. The motivation would be they are well-known in the semiconductor art as taught by Arthur ([0048], [0052]). See MPEP 2144.03.
Arthur teaches
12. (Original) The method of claim 1, wherein:
providing the body of semiconductor material 200 comprises providing a IV-IV semiconductor material ([0040]).
Bencher discloses
13. (Previously Presented) A method of manufacturing a semiconductor device, comprising:
providing a body 300 of semiconductor material ([0026]) comprising:
a top side;
a bottom side opposite to the top side; and
a first conductivity type ([0029]);
providing a mask 314B over the top side, the mask 314B comprising a side wall;
providing a conformal layer 320 over the top side and the mask 314B;
removing a portion of the conformal layer 320 to provide a first spacer 321 adjoining the side wall of the mask 314B ([0027]);
removing the mask 314B ([0028]);
removing the first spacer 321.
Bencher fails to disclose
providing a first doped region and a second doped region both comprising a second conductivity type opposite the first conductivity type self-aligned to the first spacer, wherein the first doped region and the second doped region are laterally spaced apart to define a channel region between the first doped region and the second doped region.
Hseih teaches
A method comprising:
providing a first doped region 44 and a second doped region 46 self-aligned to the first spacer 42, wherein the first doped region 44 and the second doped region 46 are laterally spaced apart to define a channel region between the first doped region 44 and the second doped region 46.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide doped regions self-aligned to a spacer in Bencher. The motivation would be to provide a symmetric free-standing spacer as a self-alignment mask for forming semiconductor regions to avoid a separate alignment step as taught by Hsieh (column 4, line 54 to column 6, line 2).
Arthur teaches
A method comprising:
providing a first doped region 216 and a second doped region 216 both comprising a second conductivity type N or P ([0040]) opposite the first conductivity type P or N ([0042]), wherein the first doped region 216 and the second doped region 216 are laterally spaced apart to define a channel region 218 between the first doped region 216 and the second doped region 216.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide second conductivity doped regions laterally spaced apart as a channel region of a JFET in Bencher. The motivation would be they are well-known in the semiconductor art as taught by Arthur ([0048], [0052]). See MPEP 2144.03.
Claim(s) 2, 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bencher in view of Hsieh and Arthur as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2011/0198612 (Malhan).
The combination of references fails to teach
2. (Original) The method of claim 1, wherein:
providing the first feature comprises providing a first doped region comprising a second conductivity type opposite to the first conductivity type;
providing the second feature comprises a providing a second doped region comprising the second conductivity type;
the portion of the body of semiconductor material laterally interposed between the first doped region and the second doped region comprises the channel region of the JFET semiconductor device; and
the first doped region and the second doped region provide a gate region for the JFET semiconductor device.
Malhan teaches
A method comprising:
providing the first feature 8a comprises providing a first doped region comprising a second conductivity type P opposite to the first conductivity type N;
providing the second feature 8a (divided into two parts, [0089]) comprises a providing a second doped region comprising the second conductivity type P;
the portion of the body of semiconductor material 1 / 2 laterally interposed between the first doped region 8a and the second doped region 8a comprises the channel region 5a of the JFET semiconductor device ([0090]); and
the first doped region 8a and the second doped region 8a provide a gate region for the JFET semiconductor device ([0089]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide features that include doped regions that are a gate region in the modified method of Bencher. The motivation would be to control the channel as taught by Malhan ([0002]-[0005]).
Malhan teaches
3. (Original) The method of claim 2, further comprising:
providing a third doped region 6a comprising the first conductivity type N coupled to the channel region 5a ([0089]).
Claim(s) 4, 5 is/are rejected under 35 U.S.C. 103 as being obvious over Bencher in view of Hseih, Arthur and Malhan as applied to claim 3 above, and further in view of U.S. Patent Application Publication No. 2007/0281408 (Howard).
The combination of references fails to teach
4. (Original) The method of claim 3, wherein:
the channel region comprises a first elongate stripe;
the third doped region comprises a second elongate stripe; and
the second elongate stripe is generally orthogonal to the first elongate stripe in a top view.
Howard teaches
A method comprising:
the channel region 124 comprises a first elongate stripe;
the third doped region 120 comprises a second elongate stripe; and
the second elongate stripe is generally orthogonal to the first elongate stripe in a top view ([0058]). Also, region 116 and region 118 extend along opposite sides of channel 124 orthogonal to region 124.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide first and second elongate stripes in the modified method of Bencher. The motivation would be to provide a well-defined gate modulation region and improved channel control as taught by Howard ([0025]).
Howard teaches
5. (Original) The method of claim 4, wherein:
the gate region 116 / 118 comprises third elongate stripes generally parallel to the first elongate stripe 124.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being obvious over Bencher in view of Hseih, Arthur, Malhan and Howard as applied to claim 4 above, and further in view of U.S. Patent Application Publication No. 2013/0248944 (Morizuka).
The combination of references fails to teach
6. (Original) The method of claim 4, further comprising:
providing a fourth doped region comprising the second conductivity type coupled to the gate region;
wherein:
the fourth doped region comprises a fourth elongate stripe generally parallel to the second elongate stripe.
Morizuka teaches
A method comprising:
providing a fourth doped region 16 comprising the second conductivity type P coupled to the gate region 4;
wherein:
the fourth doped region 16 comprises a fourth elongate stripe generally parallel to the second elongate stripe ([0030], extend in the same direction).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a fourth doped region (an elongate stripe) coupled to the gate region modified method of Bencher. The motivation would be to reduce gate resistance and control threshold voltage as taught by Morizuka ([0003], [0032], [0049]-[0056], [0112]).
Claim(s) 14, 15 is/are rejected under 35 U.S.C. 103 as being obvious over Bencher in view of Hseih and Arthur as applied to claim 13 above, and further in view of Morizuka.
The combination of references fails to teach
14. (Previously presented) The method of claim 13, further comprising:
providing a third doped region of the first conductivity type coupled to the channel region; and
providing a fourth doped region of the second conductivity type coupled to the first doped region and the second doped region, wherein:
providing the body of semiconductor material comprises providing the body of semiconductor material comprising SiC.
Morizuka teaches
A method comprising:
providing a third doped region 7 of the first conductivity type N coupled to the channel region 5; and
providing a fourth doped region 16 of the second conductivity type P coupled to the first doped region 4 and the second doped region 4, wherein:
providing the body of semiconductor material 2 comprises providing the body of semiconductor material comprising SiC ([0028]-[0036]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a third doped region and a fourth doped region in the modified method of Bencher. The motivation would be to reduce gate resistance and control threshold voltage as taught by Morizuka ([0003], [0032], [0049]-[0056], [0112]).
Morizuka teaches
15. (Original) The method of claim 14, further comprising:
providing a first conductor 15 coupled to the third doped region 7;
providing a second conductor 6 coupled to the fourth doped region 16; and
providing a third conductor 14 coupled to the bottom side of the body of semiconductor material 2.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide three conductors in the modified method of Bencher. The motivation would be they are well-known in the semiconductor art as taught by Morizuka. See MPEP 2144.03.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being obvious over Bencher in view of Hseih, Arthur, Morizuka as applied to claim 14 above, and further in view of Howard.
The combination of references fails to teach
16. (Original) The method of claim 14, wherein:
providing the first doped region and the second doped region comprises providing a gate structure;
the channel region comprises a first elongate stripe;
the third doped region comprises a second elongate stripe generally perpendicular to the first elongate stripe;
the gate structure comprises third elongate stripes generally parallel to the first elongate stripe; and
the fourth doped region comprises a fourth elongate stripe generally parallel to the second elongate stripe.
Howard teaches
A method comprising:
providing the first doped region 116 and the second doped region 118 comprises providing a gate structure;
the channel region 124 comprises a first elongate stripe;
the third doped region 120 comprises a second elongate stripe generally perpendicular to the first elongate stripe;
the gate structure comprises third elongate stripes generally parallel to the first elongate stripe; and
Morizuka teaches
the fourth doped region 16 comprises a fourth elongate stripe generally parallel to the second elongate stripe.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to arrange the gate, channel and doped regions according to a cross-lateral JFET geometry in the modified method of Bencher. The motivation would be to provide a well-defined gate modulation region and improved channel control as taught by Howard ([0025]) while maintain a stripe layout as taught by Morizuka.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Application Publication Nos. 2002/0042196 (Lee), 2007/0161205 (Lin), 2009/0166722 (Hebert) teach a method of forming a semiconductor device having features self-aligned to opposing sides of a spacer structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
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/TERESA M. ARROYO/Primary Examiner, Art Unit 2893
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