DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I (claims 1-12) in the reply filed on 3/10/2026 is acknowledged. The traversal is on the ground(s) that Applicant has amended claim 13 to overcome the restriction. This is found persuasive and the restriction between Groups I and II is withdrawn. However, the restriction between Groups I / II (claims 1-12 and 13-16) and Group III (claims 17-20) has not been overcome. Accordingly, claims 17-20 are withdrawn.
Applicant also elected Species A. (Figs. 9-14B / claims 1-6, 12-16) without traverse. These claims are examined below. Accordingly, claims 7-11 are withdrawn.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2010/0075503 (Bencher) in view of U.S. Patent Application Publication No. 2009/0294873 (Zhu).
Bencher discloses
1. (Original) A method of manufacturing a semiconductor device, comprising:
providing a body 300 of semiconductor material comprising:
a top side;
a bottom side opposite to the top side; and
a first conductivity type ([0029]);
providing a mask 314B over the top side, the mask comprising a side wall;
providing a conformal layer 320 over the top side and the mask;
removing a portion of the conformal layer 320 to provide a first spacer 321 adjoining the side wall of the mask ([0027]);
removing the mask 314B ([0028]).
Bencher fails to disclose
providing a first feature as a first part of the body of semiconductor material self-aligned to a first side of the first spacer;
providing a second feature as a second part of the body of semiconductor material self-aligned to a second side of the first spacer, wherein a portion of the body of semiconductor material is laterally interposed between the first feature and the second feature; and
removing the first spacer;
wherein:
the portion of the body of semiconductor material laterally interposed between the first feature and the second feature comprises a channel region of a JFET semiconductor device or a JFET region of an insulated gate field effect transistor device.
Zhu teaches
A method comprising:
providing a first feature 20 as a first part of the body of semiconductor material 10 self-aligned to a first side of the first spacer 23’;
providing a second feature 20 as a second part of the body of semiconductor material 10 self-aligned to a second side of the first spacer 23’, wherein a portion of the body of semiconductor material 10 is laterally interposed between the first feature 20 and the second feature 20; and
removing the first spacer 23’;
wherein:
the portion of the body of semiconductor material 10 laterally interposed between the first feature 20 and the second feature 20 comprises a channel region of a JFET semiconductor device or a JFET region of an insulated gate field effect transistor device ([0034]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide features self-aligned to a spacer and removing the spacer in Bencher. The motivation would be to provide a FET device with enhanced performance as taught by Zhu ([0001]-[0017]).
Bencher discloses
13. (Currently amended) A method of manufacturing a semiconductor device, comprising:
providing a body 300 of semiconductor material comprising:
a top side;
a bottom side opposite to the top side; and
a first conductivity type ([0029]);
providing a mask 314B over the top side, the mask comprising a side wall;
providing a conformal layer 320 over the top side and the mask;
removing a portion of the conformal layer 320 to provide a first spacer 321 adjoining the side wall of the mask ([0027]);
removing the mask 314B ([0028]).
Bencher fails to disclose
providing a first doped region and a second doped region both comprising a second conductivity type opposite the first conductivity type self-aligned to the first spacer, wherein the first doped region and the second doped region are laterally spaced apart to define a channel region between the first doped region and the second doped region; and
removing the first spacer.
Zhu teaches
A method comprising:
providing a first doped region 20 and a second doped region 20 both comprising a second conductivity type opposite the first conductivity type ([0031]-[0034]) self-aligned to the first spacer 23’, wherein the first doped region 20 and the second doped region 20 are laterally spaced apart to define a channel region between the first doped region 20 and the second doped region 20 ([0034]); and
removing the first spacer 23’.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide features self-aligned to a spacer and removing the spacer in Bencher. The motivation would be to provide a FET device with enhanced performance as taught by Zhu ([0001]-[0017]).
Claim(s) 2, 3, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bencher in view of Zhu as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2017/0170298 (Balakrishna).
The combination of references fails to teach
2. (Original) The method of claim 1, wherein:
providing the first feature comprises providing a first doped region comprising a second conductivity type opposite to the first conductivity type;
providing the second feature comprises a providing a second doped region comprising the second conductivity type;
the portion of the body of semiconductor material laterally interposed between the first doped region and the second doped region comprises the channel region of the JFET semiconductor device; and
the first doped region and the second doped region provide a gate region for the JFET semiconductor device.
Balakrishna teaches
A method comprising:
providing the first feature 110 comprises providing a first doped region comprising a second conductivity type opposite to the first conductivity type;
providing the second feature 110 comprises a providing a second doped region comprising the second conductivity type;
the portion of the body of semiconductor material 502 / 710 laterally interposed between the first doped region 110 and the second doped region 110 comprises the channel region of the JFET semiconductor device ([0036]); and
the first doped region 110 and the second doped region 110 provide a gate region for the JFET semiconductor device ([0039]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide features that include doped regions that are a gate region in the modified method of Bencher. The motivation would be to provide multiple threshold voltage devices for a vertical field-effect-transistor so power/performance tradeoff can be tuned in circuit design as taught by Balakrishna ([0002]-[0005]).
Balakrishna teaches
3. (Original) The method of claim 2, further comprising:
providing a third doped region comprising the first conductivity type coupled to the channel region ([0038]).
Balakrishna teaches
12. (Original) The method of claim 1, wherein:
providing the body of semiconductor material 502 / 710 comprises providing a IV-IV semiconductor material ([0039], [0040]).
Claim(s) 4-6, 14-16 is/are rejected under 35 U.S.C. 103 as being obvious over Bencher in view of Zhu and Balakrishna as applied to claims 3 / 13 above, and further in view of U.S. Patent Application Publication No. 2024/0178269 (Franchi).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
The combination of references fails to teach
4. (Original) The method of claim 3, wherein:
the channel region comprises a first elongate stripe;
the third doped region comprises a second elongate stripe; and
the second elongate stripe is generally orthogonal to the first elongate stripe in a top view.
Franchi teaches (Fig. 6)
A method comprising:
the channel region 141A comprises a first elongate stripe;
the third doped region 37 comprises a second elongate stripe; and
the second elongate stripe is generally orthogonal to the first elongate stripe in a top view ([0058]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide first and second elongate stripe in the modified method of Bencher. The motivation would be based on its suitability for an intended purpose as taught by Franchi ([0003]-[0006]). See MPEP 2144.07.
Franchi teaches
5. (Original) The method of claim 4, wherein:
the gate region 31 comprises third elongate stripes generally parallel to the first elongate stripe.
Franchi teaches
6. (Original) The method of claim 4, further comprising:
providing a fourth doped region 34 comprising the second conductivity type coupled to the gate region 31;
wherein:
the fourth doped region 34 comprises a fourth elongate stripe generally parallel to the second elongate stripe ([0058]).
Franchi teaches (Fig. 6)
14. (Currently amended) The method of claim 13, further comprising:
providing a third doped region 37 of the first conductivity type coupled to the channel region 141A; and
providing a fourth doped region 34 of the second conductivity type coupled to the first doped region 141 and the second doped region 31, wherein:
providing the body of semiconductor material 12 comprises providing the body of semiconductor material comprising SiC ([0037]).
Franchi teaches (Fig. 6)
15. (Original) The method of claim 14, further comprising:
providing a first conductor 44A coupled to the third doped region 37;
providing a second conductor 44B coupled to the fourth doped region 34; and
providing a third conductor 46 coupled to the bottom side of the body of semiconductor material 12.
Franchi teaches (Fig. 6)
16. (Original) The method of claim 14, wherein:
providing the first doped region 141 and the second doped region 31 comprises providing a gate structure ([0042]);
the channel region 141A comprises a first elongate stripe;
the third doped region 37 comprises a second elongate stripe generally perpendicular to the first elongate stripe ([0058]);
the gate structure comprises third elongate stripes generally parallel to the first elongate stripe ([0058]); and
the fourth doped region 34 comprises a fourth elongate stripe generally parallel to the second elongate stripe.
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
JP Publication No. H0730110 (Nobuyoshi), U.S. Patent Application Publication No. 2021/0082767 (Kim), U.S. Patent Nos. 5,998,261 (Hofmann), 8,409,956 (Kang), 9,343,309 (Bangar) teach a method of forming a semiconductor device having features self-aligned to opposing sides of a spacer structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
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/TERESA M. ARROYO/Primary Examiner, Art Unit 2893
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