Prosecution Insights
Last updated: July 17, 2026
Application No. 18/529,948

CONDUCTIVE FEATURES OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME

Non-Final OA §102§103
Filed
Dec 05, 2023
Priority
Aug 14, 2023 — provisional 63/519,371
Examiner
VU, HUNG K
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
877 granted / 1001 resolved
+19.6% vs TC avg
Moderate +9% lift
Without
With
+9.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
34 currently pending
Career history
1034
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
72.0%
+32.0% vs TC avg
§102
18.1%
-21.9% vs TC avg
§112
3.6%
-36.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1001 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election with traverse of Invention of Group II, Embodiment 1 of Figures 12-14, Claims 1-15 and 21-25 in the reply filed on 04/20/2026 is acknowledged. The traversal is on the ground(s) that the Examiner fails to show a serious search burden. This is not found persuasive because the fields of search for device and method claims are not coextensive and the determinations of patentability of method and device claims are different, that is device limitations and method limitations are given weight differently in determining the patentability of the claimed inventions. Also, the strategies for doing text searching of the device claims and method claims are different. Thus, separate searches are required The requirement is still deemed proper and is therefore made FINAL. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. (US 2018/0315764). Yang et al. discloses, as shown in Figures, a method comprising: depositing a first dielectric material (20) over a substrate (10) [0031]; depositing a first barrier layer (35) over the first dielectric material; depositing a conductive material (40, polysilicon) over the first barrier layer; etching a plurality of recesses extending through the conductive material and the first barrier layer ([0038], Figure 2); selectively depositing a protective material (45) on exposed surfaces of the conductive material and the first barrier layer, wherein the first dielectric material is free of the protective material (Figure 3); and depositing a liner layer (48 or 50) on the protective material and the first dielectric material (Figures 4-7). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-15 and 21-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2022/0319990) in view of Yang et al. (US 2018/0315764). Regarding claim 1, Huang et al. discloses, as shown in Figures 1E-2M, a method comprising: forming a conductive layer (112) over a first dielectric layer (104) [Figure 1E]; etching a recess (116) in the conductive layer, wherein the recess exposes a top surface of the first dielectric layer [Figure 1F]; depositing a liner (118) in the recess [Figure 1G]; forming a sacrificial material (120) in the recess [Figure 1H]; and forming a second dielectric layer (122) on the sacrificial material and on sidewalls of the recess [1J]; and after forming the second dielectric layer, performing a thermal process to remove the sacrificial material [0033], [1H]. Huang et al. does not disclose selectively depositing a capping layer on exposed sidewalls of the conductive layer within the recess. However, Yang et al. discloses a method of selectively depositing a capping layer (45) on exposed sidewalls of the conductive layer (40) within the recess. Note Figures 3-4 of Yang et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form a conductive layer of Huang et al. having a capping layer on exposed sidewalls of the conductive layer, such as taught by Yang et al. in order to protect the conductive layer from contamination. Regarding claim 2, Huang et al. and Yang et al. disclose the method further comprising forming a first barrier layer (110) between the conductive layer and the first dielectric layer. Regarding claim 3, Huang et al. and Yang et al. disclose the method further comprising forming a second barrier layer (114) on a top surface of the conductive layer [Figure 1E]. Regarding claim 4, Huang et al. and Yang et al. disclose forming the sacrificial material (120) comprises: filling the recess with the sacrificial material; and performing an etch-back process to remove upper portions of the sacrificial material [Figure 1I]. Regarding claim 5, Huang et al. and Yang et al. disclose the liner (118) physically contacts a top surface of first dielectric layer (104) [Figure 1G]. Regarding claim 6, Huang et al. and Yang et al. disclose performing the thermal process to remove the sacrificial material forms an air gap (124) underneath the second dielectric layer [0033] [Figure 1K]. Regarding claim 7, Huang et al. and Yang et al. disclose the method further comprising forming a third dielectric layer (126) on the second dielectric layer after performing the thermal process, wherein the regions underneath the second dielectric layer remain free of the third dielectric layer [Figure 1L]. Regarding claim 8, Huang et al. and Yang et al. disclose further comprising performing a planarization process to remove upper portions of the second dielectric layer, the capping layer, and the liner [Figure 1M]. Regarding claim 9, Huang et al. discloses, as shown in Figures 1E-2M, a method comprising: depositing a first dielectric material (104) over a substrate (502) [0012] [Figures 1D]; depositing a first barrier layer (110) over the first dielectric material [Figure 1E]; depositing a conductive material (112) over the first barrier layer [Figure 1E]; etching a plurality of recesses (116) extending through the conductive material and the first barrier layer [Figure 1F]; and depositing a liner layer (118) on the protective material and the first dielectric material [Figure 1G]. Huang et al. does not disclose selectively depositing a protective material on exposed surfaces of the conductive material and the first barrier layer, wherein the first dielectric material is free of the protective material. However, Yang et al. disclose a method of selectively depositing a protective material (45) on exposed surfaces of the conductive material (40) and the first barrier layer (35), wherein the first dielectric material (20) is free of the protective material. Note Figures 3-4 of Yang et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the conductive material and the first barrier layer of Huang et al. having a protective material on exposed surfaces, such as taught by Yang et al. in order to protect the conductive material and the first barrier layer from contamination. Regarding claim 10, Huang et al. and Yang et al. disclose further comprising: filling the plurality of recesses with a sacrificial material (120) [Figure 1H]; removing upper portions of the sacrificial material to expose the liner layer within the plurality of recesses [Figure 1I]; depositing a second dielectric material (122) on the sacrificial material [Figure 1J]; and removing the remaining portions of the sacrificial material to form a plurality of air gaps (124) in the plurality of recesses [Figure 1K]. Regarding claim 11, Huang et al. and Yang et al. disclose a top surface of the conductive material is higher than the plurality of air gaps [Figure 1K]. Regarding claim 12, Huang et al. and Yang et al. disclose at least one recess of the plurality of recesses exposes a conductive feature (106/108) underlying the first dielectric material [Figure 1F]. Regarding claim 13, Huang et al. and Yang et al. disclose the plurality of recesses extend lower than a top surface of the first dielectric material [Figure 1F]. Regarding claim 14, Huang et al. and Yang et al. disclose the conductive material is ruthenium (112 and 106 are the same material [0024], [0025]). Regarding claim 15, Huang et al. and Yang et al. disclose the protective material is deposited to a thickness of 20 nm [0040]. Huang et al. and Yang et al. do not disclose the protective material having the thickness as claimed. However, the selection of these parameters such as energy, concentration, temperature, time, speed, molar fraction, depth, thickness, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, etc., or in combination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Alter 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934). Regarding claim 21, Huang et al. discloses, as shown in Figures 1E-2M, a method comprising: forming a first conductive feature (112) and a second conductive feature (112) on a top surface of a first dielectric layer (104); forming an air gap (124) between the first conductive feature and the second conductive feature comprising: depositing a sacrificial layer (120) on the top surface of the first dielectric layer between the first conductive feature and the second conductive feature; depositing a sustain layer (118) on the sacrificial layer between the first conductive feature and the second conductive feature; and removing the sustain layer [Figure 1M]; and depositing a second dielectric layer (126) on the sustain layer between the first conductive feature and the second conductive feature. Huang et al. does not disclose depositing a capping layer on facing sidewalls of the first conductive feature and the second conductive feature, wherein the capping layer is vertically separated from the top surface of the first dielectric layer. However, Yang et al. disclose a method of selectively depositing a capping layer (45) on facing sidewalls of the first conductive feature and the second conductive feature, wherein the capping layer is vertically separated from the top surface of the first dielectric layer (20). Note Figures 3-4 of Yang et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the first and second conductive features of Huang et al. having a capping layer on facing sidewalls, such as taught by Yang et al. in order to protect the first and second conductive features from contamination. Regarding claim 22, Huang et al. and Yang et al. do not disclose the material of the capping layer. However, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form the capping layer of Huang et al. and Yang et al. having the materials as that claimed by Applicant, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Regarding claim 23, Huang et al. and Yang et al. disclose the method further comprising depositing a liner layer (118) on the capping layer and on the top surface of the first dielectric layer. Regarding claim 24, Huang et al. and Yang et al. disclose the first conductive feature and the second conductive feature comprise a barrier layer on the top surface of the first dielectric layer (110). Regarding claim 25, Huang et al. and Yang et al. disclose the air gap extends underneath the capping layer. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNG K VU whose telephone number is (571)272-1666. The examiner can normally be reached Monday - Friday: 7am - 5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JACOB CHOI can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HUNG K VU/ Primary Examiner, Art Unit 2897
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Prosecution Timeline

Dec 05, 2023
Application Filed
Jul 01, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
97%
With Interview (+9.3%)
2y 6m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1001 resolved cases by this examiner. Grant probability derived from career allowance rate.

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