DETAILED ACTION
This Office action responds to the application filed on 12/05/2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 & 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 20200006324) in view of Kim (US 20240136273) and further in view of Chang (US 20220149020).
Regarding Claim 1, Chen (see, e.g., fig. 1) shows a method comprising:
forming a dummy component 300 (dummy die, see, e.g., para.0045), comprising:
forming a plurality of through-substrate vias (TSVs) TSVb (see, e.g., para.0030) in a substrate S3 (see, e.g., para.0029);
forming a structure 304 (see, e.g., para.0031-0033) over the plurality of TSVs,
wherein the structure 304 comprises a plurality of metal lines (metal lines of 308, see, e.g., para.0031) in a plurality of dielectric layers 306 & 309 (see, e.g., para.0031-0032);
forming a bonding layer BDL3 (see, e.g., para.0033) over the structure 304;
and forming a plurality of bond pads BP3 (see, e.g., para.0033) within the bonding layer;
bonding the dummy component 300 to a package component 100;
and bonding a semiconductor die 200 (see, e.g., para.0036) to the package component.
Chen, however, fails to explicitly state the structure 304 is a thermal structure.
Although Chen does not explicitly state structure 304 is a thermal structure, Kim (see, e.g., para.0135) states dummy dies can be used as heat dissipation passages for package components. Furthermore, Chang (see, e.g., fig. 1, para.0028, para.0053) states RDL structures, similar to structure 304 of Sun, can improve heat dissipation.
Therefore it would have been obvious at the time of filing the invention to one of ordinary skill in the art to interpret the structure 304 of Chen as a thermal structure, in view of Kim and further in view of Chang.
Regarding Claim 2, Chen (see, e.g., para.0038), in view of Kim and further in view of Chang, shows the method of claim 1,
wherein bonding the dummy component to the package component comprises
bonding the bonding layer to the package component using dielectric-to-dielectric bonding (BL3 to BDL1, see, e.g., para.0038)
and bonding the plurality of bond pads to the package component using metal-to-metal bonding (BP3 to BPb, see, e.g., para.0038).
Regarding Claim 3, Chen (see, e.g., para.0031, para.0033), in view of Kim and further in view of Chang, shows the method of claim 1,
wherein forming the dummy component further comprises
forming a plurality of metal vias (metal plugs of 308 & BV3, see, e.g., para.0031, para.0033) in the plurality of dielectric layers 306 & 309,
wherein metal vias of the plurality of metal vias physically contact
metal lines of the plurality of metal lines
and TSVs of the plurality of TSVs.
Regarding Claim 4, Chen (see, e.g., fig. 1), in view of Kim and further in view of Chang, shows the method of claim 3,
wherein metal vias (metal plugs of 308 & BV3) of the plurality of metal vias physically contact
metal lines of the plurality of metal lines
and bond pads of the plurality of bond pads.
Regarding Claim 6, Chen (see, e.g., fig. 1, annotated figure 1), in view of Kim and further in view of Chang, shows the method of claim 1,
wherein the plurality of TSVs comprise
a third set of TSVs having a first pitch (labeled P1, see, e.g., annotated figure 1)
and a fourth set of TSVs having a second pitch (labeled P2, see, e.g., annotated figure 1) that is different from the first pitch.
Since Claim 6 does not depend on Claim 5, the limitations “third & fourth set” do not establish the presence of first and second sets. Claim 6 can be rejected with only two sets of TSVs.
Regarding Claim 7, Chen (see, e.g., fig. 1, annotated figure 1), in view of Kim and further in view of Chang, shows the method of claim 1,
wherein the plurality of TSVs comprise
a fifth set of TSVs having a first width (labeled W1, see, e.g., annotated figure 1)
and a sixth set of TSVs having a second width (labeled W2, see, e.g., annotated figure 1) that is different from the first width.
Since Claim 7 does not depend on Claims 5 or 6, the limitations “fifth & sixth set” do not establish the presence of first, second, third, and fourth sets. Claim 7 can be rejected with only two sets of TSVs. Thus, the fourth and third sets of TSVs of Claim 6 (see, e.g., annotated figure 1) are used to render the limitations of Claim 7 obvious.
Regarding Claim 8, Chen, in view of Kim and further in view of Chang, shows the method of claim 1,
wherein the dummy component 300 is electrically connected to the semiconductor die 200 by dummy routing within the package component (connection 108).
Semiconductor die 200 and dummy component 300 are both connected to and by bonding structure BS1 and interconnection structure 108. Since 108 facilitates the connection of the dummy component, Examiner interprets interconnection structure 108 as dummy routing.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 20200006324) in view of Kim (US 20240136273) & Chang (US 20220149020) and further in view of Chen (US 20200118975) hereinafter referred to as “Chiou”.
Regarding Claim 5, Chen, in view of Kim and further in view of Chang, shows the method of claim 1
Chen, in view of Kim and further in view of Chang, however, fails to show
wherein the plurality of TSVs comprise
a first set of TSVs having a first height H1
and a second set of TSVs having a second height H2 that is different from the first height.
Chiou (see, e.g., fig. 1, para.0034, para.0043-0044, para.0048), in a similar method to Chen, in view of Kim & Chang, teaches a configuration wherein that first and second sets of TSVs 103h with corresponding different heights would improve connection capabilities of dummy component 103 by allowing for multiple forms of connection.
For instance, the left set of TSVs 103h is used for facilitating a connection through dummy component 103 between top interconnection structure 105 and bottom interconnection structure 101c. The right set of TSVs 103h, with a different height, facilitates connection to the dummy component 103 by a deeper embedded conductive member 103g.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Chiou in the method of Chen, in view of Kim & Chang, to improve connection capabilities of the dummy component.
Claims 9 & 10 are rejected under 35 U.S.C. 103 as being unpatentable over Sun (US 20230420330), in view of Tsai (US 20230154913).
Regarding Claim 9, Sun (see, e.g., figs. 2-3) shows a method comprising:
forming a first bonding layer 112 (see, e.g., para.0031) on a first package component 100 (see, e.g., para.0024);
forming a plurality of first bond pads 115 (see, e.g., para.0031) in the first bonding layer;
forming a plurality of second bond pads 114 (see, e.g., para.0031) in the first bonding layer;
bonding a thermal component 160 (see, e.g., para.0031) to the first bonding layer and to the plurality of first bond pads,
wherein the thermal component comprises:
through-substrate vias (TSVs) (metal vias not shown, see, e.g., para.0045) extending into a substrate 160 (see, e.g., para.0036);
a second bonding layer 162 (see, e.g., para.0044) over the substrate and the TSVs;
and a plurality of third bond pads 164 (see, e.g., para.0044) in the second bonding layer;
and bonding an active package component 150 (see, e.g., para.0031) to the first bonding layer and to the plurality of second bond pads,
wherein the active package component comprises:
active devices (see, e.g., para.0038);
a third bonding layer 152 (see, e.g., para.0039) over the active devices;
and a plurality of fourth bond pads 154 (see, e.g., para.0039) in the third bonding layer.
Sun (see, e.g., para.0045) states the thermal component comprises metal vias as first metal features within its substrate.
The drawings of Sun, however, fail to explicitly show a configuration for the first metal features.
Although Sun does not explicitly show a configuration for the first metal features, Tsai (see, e.g., fig. 25, fig. 26a, para.0058), shows a configuration for first metal features (metal vias) 55v of a thermal component 55 extending into the substrate 55s.
Therefore it would have been obvious at the time of filing the invention to one of ordinary skill in the art to interpret the first metal features of Sun as shown in the configuration of Tsai.
Regarding Claim 10, Sun (see, e.g., fig. 3), in view of Tsai, shows the method of claim 9,
wherein the first bond pads of the plurality of first bond pads 115 are electrically isolated (see, e.g., para.0031).
Claims 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Sun (US 20230420330), in view of Tsai (US 20230154913, and further in view of Sun (US 20240021488) hereinafter referred to as “Liang”.
Regarding Claim 11, Sun, in view of Tsai, show the method of claim 9 further comprising
Sun, in view of Tsai, however, fails to show
forming a plurality of thermal routing within the first bonding layer,
wherein at least one third bond pad is bonded to one thermal routing.
Liang (see, e.g., figs. 5-6, para.0042, para.0052), in a similar method to Sun, shows a plurality of thermal routing 113a-c & 111 bonded to third bond pads of a thermal component and fourth bond pads of an active package component would improve heat dissipation between devices.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the plurality of thermal routing of Liang, in the method of Sun, in view of Tsai, to improve heat dissipation between devices.
Regarding Claim 12, Sun, in view of Tsai and further in view of Liang, show the method of claim 11,
wherein at least one fourth bond pad is bonded to one thermal routing (see paragraph above).
Regarding Claim 13, Sun, in view of Tsai and further in view of Liang (see, e.g., fig. 11, para.0051) shows the method of claim 11,
wherein the second bonding layer 162 is thinner than the third bonding layer 152.
Sun, in view of Tsai and further in view of Liang (see, e.g., fig. 11, para.0051), shows a configuration wherein the second bonding layer 162 of a dummy die 160 is thinner than the unthinned third bonding layer 152 of an active package component 150.
Regarding Claim 14, Sun, in view of Tsai and further in view of Liang (see, e.g., fig. 11, para.0051), shows the method of claim 11,
wherein a thickness of a layer of a first dielectric material within the second bonding layer 162 is different from a thickness of a layer of the first dielectric material within the third bonding layer 152.
Regarding Claim 15, Sun, in view of Tsai and further in view of Liang (see, e.g., fig. 11), shows the method of claim 14,
wherein the first dielectric material is silicon oxide (see, e.g., para.0041, para.0044).
Sun (see, e.g., para.0041, para.0044), in view of Tsai and further in view of Liang (see, e.g., fig. 11), states that second and third bonding layers 162 & 152 are both made of first dielectric material silicon oxide.
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sun (US 20230420330), in view of Tsai (US 20230154913).
Regarding Claim 16, Sun (see, e.g., fig. 3, fig. 13) shows a package comprising:
a dummy die 160 (see, e.g., para.0043) bonded to a package component 100,
wherein the dummy die comprises:
a substrate (silicon, silicon oxide, silicon carbine etc. see, e.g., para.0043);
first metal features (metal vias not shown, see, e.g., para.0045) extending into the substrate;
second metal features 143 (see, e.g., para.0068) over the first metal features and separated from the first metal features by a first dielectric layer 132 (see, e.g., para.0061);
a second dielectric layer 162 (same dielectric materials as 152, see, e.g., para.0041, para.0044) over the second metal features;
and bond pads 164 (see, e.g., para.0044) within the second dielectric layer;
and a semiconductor die 150 (see, e.g., para.0035) bonded to the package component adjacent the dummy die.
Sun (see, e.g., para.0045) states the dummy die comprises metal vias as first metal features within its substrate.
The drawings of Sun, however, fail to explicitly show a configuration for the first metal features.
Although Sun does not explicitly show a configuration for the first metal features, Tsai (see, e.g., fig. 25, fig. 26a, para.0058), shows a configuration for first metal features (metal vias) 55v of a dummy die 55 extending into the substrate 55s.
Therefore it would have been obvious at the time of filing the invention to one of ordinary skill in the art to interpret the first metal features of Sun as shown in the configuration of Tsai.
Regarding Claim 17, Sun (see, e.g., para.0045), in view of Tsai, shows the package of claim 16,
wherein the dummy die 160 is electrically isolated from the semiconductor die 150.
Sun (see, e.g., para.0045) states dummy die 160 is isolated from vias 110 of the interconnect structure 104. Thus, the dummy die has no connection with and is isolated from the semiconductor die 150.
Regarding Claim 18, Sun (see, e.g., para.0068), in view of Tsai, shows the package of claim 16,
wherein the dummy die comprises at least two layers of second metal features.
Sun (see, e.g., para.0068) states the second metal features 143 comprise multiple layers such as a barrier layer, a seed layer, and a fill metal layer. Thus, there are at least two layers of second metal features.
Regarding Claim 19, Sun (see, e.g., fig. 3), in view of Tsai, shows the package of claim 16,
wherein the package component comprises bond pads 115 (see, e.g., para.0031),
wherein the bond pads of the dummy die 162 are directly bonded to the bond pads of the package component (see, e.g., para.0044).
Regarding Claim 20, Sun, in view of Tsai, shows the package of claim 16,
wherein at least one first metal feature (metal via) is electrically connected to at least one metal pad 115 of the package component (see, e.g., annotated figure 2).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/F.R.D./ Examiner, Art Unit 2814
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814