Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendments/Arguments
Applicant's arguments to claim 1, pages 3-4 of the remarks, with respect to 35 U.S.C. 102(a)(1) rejection of claim 1 as unpatentable over US5306668A; Byungseong et al.; (hereinafter “Byungseong”) have been fully considered and are persuasive. Hence, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made under 35 U.S.C. 102(a)(1) as being unpatentable over JPH0836194A; Kiyobumi Kitawada; (hereinafter “Kitawada”). (See 35 U.S.C. 102(a)(1) rejection of claim 1 below).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 9, 11, 14, 16, 19, 21 and 23-24 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over Kitawada; see attached patent machine translation.
Regarding Claim 1, Kitawada teaches a method of forming an electrode with multi-dielectric layers ([0008]), comprising:
forming a metal pattern (#702-703, Figure 7 of Kitawada annotated) on a substrate (#701), wherein the metal pattern comprises a first metal film (#703) on the substrate and a second metal film (#702) on a top surface of the first metal film (#703), and a metal composition of the first metal film and a metal composition of the second metal film are different (#702 and #703 comprise such as aluminum and tantalum respectively); and
anodizing the metal pattern in a liquid electrolyte ([0023]) to form a covering anodized portion (#705-707) which covers an unanodized portion (#UA), wherein the covering anodized portion comprises a sidewall oxide dielectric structure (#705-706) and a top oxide dielectric structure (#707), the sidewall oxide dielectric structure (#705-706) is in contact with a side surface of the unanodized portion (side surface of #UA), the top oxide dielectric structure (#707) is in contact with a top surface of the unanodized portion (top surface of #UA) and a top surface of the sidewall oxide dielectric structure (top surface of #705), and the sidewall oxide dielectric structure and the top oxide dielectric structure have different effective permittivities (anodization of metal layers #703 and #702 of different metal compositions results in anodic oxide films #706 and #705 which inherently have different effective permittivities).
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Regarding Claim 2, Kitawada teaches the method as described in claim 1, wherein Kitawada further teaches the forming the metal pattern comprises:
depositing the first metal film (#703, Figure 7 of Kitawada annotated) on the substrate (#701);
depositing the second metal film (#702) on the first metal film (#703); and
performing an etching process to the first metal film and the second metal film to form the metal pattern, wherein the etching process is a photo engraving process ([0023], metal films #702-703 are patterned to form tapered conductive structure using conventional photolithography techniques).
Regarding Claim 9, Kitawada teaches the method as described in claim 1, wherein Kitawada further teaches a material of the second metal film comprises at least one of hafnium, tantalum, zirconium, titanium, and tungsten ([0023], metal film #703 comprises such as tantalum).
Regarding Claim 11, Kitawada teaches the method as described in claim 1, wherein Kitawada further teaches the anodizing is performed to reach a termination voltage under 500 Volt ([0023], the anodic oxidation process is performed at voltage of 40-100V or lower).
Regarding Claim 14, Kitawada teaches the method as described in claim 1, wherein Kitawada further teaches the metal pattern further comprises at least one additional metal film on a top surface of the second metal film (Figure 7 of Kitawada annotated, conductive layer #708 disposes on top of metal film #702).
Regarding Claim 16, Kitawada teaches the method for manufacturing a semiconductor device as described in claim 14, wherein Kitawada further teaches the at least one additional metal film contains at least one of hafnium, tantalum, zirconium, titanium, and tungsten ([0023], conductive layer #708 comprises such as tantalum).
Regarding Claim 19, Kitawada teaches the method as described in claim 1, wherein Kitawada further teaches forming a conductive pattern (#708, Figure 7 of Kitawada annotated) across the unanodized portion (#UA) through the top oxide dielectric structure (#707).
Regarding Claim 21, Kitawada teaches the method as described in claim 1, Kitawada further teaches a thickness of the metal pattern is less than 10 μm before the anodizing ([0023], a total thickness of metal films #702-703 is between 1000-6000 Å or 0.1-0.6 µm).
Regarding Claim 23, Kitawada teaches the method for manufacturing a semiconductor device as described in claim 1, wherein Kitawada further teaches the second metal film is partially anodized after the anodizing (Figures 7 of Kitawada annotated, metal film #702 is partially anodized).
Regarding Claim 24, Kitawada teaches the method for manufacturing a semiconductor device as described in claim 1, wherein Kitawada further teaches the unanodized portion has an atomic ratio of aluminum greater than 50% (Figure 7 of Kitawada annotated, [0023], unanodized portion/metal film #UA/#703 comprises entirely of aluminum).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3-4, 13, 20 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Kitawada in view of WO2014102881A1; Tadahiro Ohmi; (hereinafter “Ohmi”); see attached machine patent translation.
Regarding Claim 3, Kitawada teaches the method as described in claim 1.
Kitawada does not explicitly teach the first metal film is a multilayer structure.
However, Ohmi teaches a method for forming insulating films by anodic oxidation in semiconductor device (par. 1, pg. 4), wherein a first metal film is a multilayer structure (pg. 20-21, gate electrode can comprise a composite structure such as sequentially stack metal/Al (Zr) alloy).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Kitawada with the teaching of Ohmi, as it would be a simple substitution of one known element (gate electrode structure of Kitawada) for another (gate electrode structure of Ohmi) in comparable structures to obtain predictable results. See MPEP 2143(I)(B).
Regarding Claim 4, Kitawada in view of Ohmi teaches the method as described in claim 3, wherein Kitawada further teaches the first metal film contains molybdenum or titanium ([0002]).
Kitawada does not explicitly teach a bottommost layer of the first metal film contains molybdenum or titanium and rest of the first metal film has an atomic ratio of aluminum greater than 50%.
However, Ohmi teaches a bottommost layer of the first metal film contains molybdenum or titanium (pg. 20-21, gate electrode can comprise a composite structure such as sequentially stack metal/Al (Zr) alloy, wherein the metal can comprise Ti or Mo, see pg. 19) and rest of the first metal film has an atomic ratio of aluminum greater than 50% (pg. 12, Al (Zr) alloy of the gate electrode contains mostly Al since the added amount of Zr is only 0.01-0.15%).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Kitawada with the teaching of Ohmi for reason set forth in rejection of claim 3.
Regarding Claim 13, Kitawada teaches the method as described in claim 1.
Kitawada does not explicitly teach the liquid electrolyte containing a content of water less than 20 wt %.
However, Ohmi teaches the liquid electrolyte containing a content of water less than 20 wt % (pg. 15, the electrolyte for anodization contains about 20% of water).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to have selected the ranges disclosed by Ohmi in order to provide electrolytic solution with desirable characteristic for the anodization process. See MPEP § 2144.05.I.
Regarding Claim 20, Kitawada teaches the method as described in claim 19, wherein Kitawada further teaches the conductive pattern (#708-709, Figure 7 of Kitawada annotated) comprises a bottom layer (#708) and a top layer (#709), and the top layer is a metal layer (#709 is a pixel electrode).
Kitawada does not explicitly teach the bottom layer is an oxide semiconductor layer.
However, Ohmi teaches the bottom layer is an oxide semiconductor layer (Figure 1, pg. 22-23, oxide semiconductor layer #104).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Kitawada with the teaching of Ohmi as it would be a simple substitution of one known element (conductive pattern of Kitawada) for another (conductive structure of Ohmi) in comparable structures to obtain predictable results. See MPEP 2143(I)(B).
Regarding Claim 25, Kitawada teaches the method as described in claim 1.
Kitawada does not explicitly teach the effective permittivity of the top oxide dielectric structure is smaller than the effective permittivity of the sidewall oxide dielectric structure.
However, Ohmi teaches the effective permittivity of the top oxide dielectric structure is smaller than the effective permittivity of the sidewall oxide dielectric structure (material of gate electrode #102 can comprise composite structure such as a sequentially stack Ti/Al (Zr) alloy, see rejection of claim 4, which is similar to the material of the metal pattern of the instant application. Hence, anodization of the metal layers would inherently result in the top metal oxide of gate insulating layer #103 having smaller effective permittivity than that of the sidewall metal oxide of layer #103).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Kitawada with the teaching of Ohmi, as it would be a simple substitution of one known element (gate electrode material of Kitawada) for another (gate electrode material of Ohmi) in comparable structures to obtain predictable results. See MPEP 2143(I)(B).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kitawada in view of US20100025676A1; Yamazaki et al.; (hereinafter “Yamazaki”).
Regarding Claim 10, Kitawada teaches the method as described in claim 1, wherein Kitawada further teaches:
forming a mask pattern (#13, Figure 2B) on a portion of a top surface of the metal pattern (#12) before the anodizing; and
removing the mask pattern after the anodizing (Figures 2C-D), such that the top surface of the unanodized portion has a covered section covered by the top oxide dielectric structure (Figure 2D or Figure 3B of Kitawada annotated) OR at least one uncovered section exposed by the top oxide dielectric structure (Figures 2C-C’).
Kitawada does not explicitly teach the top surface of the unanodized portion has at least one uncovered section exposed by the top oxide dielectric structure.
However, Yamazaki teaches a semiconductor device with a thin film transistor TFT ([0010]), wherein the top surface of the unanodized portion has at least one uncovered section exposed by the top oxide dielectric structure (Figures 1A-B, insulating film #102 exposes at least a portion of the top surface of electrode #101).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Kitawada with the teaching of Yamazaki, as it would be a simple substitution of one known element (covered gate electrode of Kitawada) for another (covered gate electrode of Yamazaki) in comparable structures to obtain predictable results. See MPEP 2143(I)(B).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kitawada in view of US20050142705A1; Konuma et al.; (hereinafter “Konuma”).
Regarding Claim 12, Kitawada teaches the method as described in claim 1.
Kitawada does not explicitly teach the anodizing is performed at a temperature under 15° C.
However, Konuma teaches a method of forming a semiconductor device ([0001]), wherein the anodizing is performed at a temperature under 15° C ([0056], the anodic oxidation is performed in electrolyte at 10° C or lower).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to have selected the ranges disclosed by Konuma in order to improve quality of the oxide film according to Konuma, [0056]. See MPEP § 2144.05.I.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Kitawada in view of Ohmi, and further in view of Yamazaki.
Regarding Claim 26, Kitawada in view of Ohmi teaches the method as described in claim 25.
Kitawada in view of Ohmi does not explicitly teach the top oxide dielectric structure contains silicon oxide.
However, Yamazaki teaches the top oxide dielectric structure contains silicon oxide ([0096], gate insulating layer comprise silicon oxide).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Kitawada in view of Ohmi with the teaching of Yamazaki, as it would be a simple substitution of one known element (gate insulating material of Kitawada) for another (gate insulating material of Yamazaki) in comparable structures to obtain predictable results. See MPEP 2143(I)(B). Additionally, Ohmi also teaches Al alloy film containing unavoidable impurity such as silicon (pg. 13 of machine patent translation), which can result in silicon oxide after anodization.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
EP0768722A1 – Figures 1a-e
KR20200072177A – Figures 4a-e
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/TIEN TRAN/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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