Prosecution Insights
Prosecution Insights
Technology area: Semiconductors, Circuits & Optics
5 pending office actions • 4 art units • 5 examiners • 0 of 5 (0%) have an AI response strategy ready • 8 patents granted in the last 365 days
Mikro Mesa Technology Co., Ltd. is managing 5 pending office actions in the Semiconductors, Circuits & Optics technology area. These cases are assigned to 5 distinct examiners, indicating that each active matter is being reviewed by a different individual. This distribution requires the company to manage five separate examiner relationships simultaneously. These actions are further spread across 4 distinct art units, suggesting that the company's technology touches upon several different specialized subgroups within the semiconductor field.
LOHAKARE, PRATIKSHA JAYANT is identified as the busiest examiner for the company, though this individual is only responsible for 1 pending office action. This parity among the examiners means that no single person holds a majority of the active workload. For the practitioner, this diversity of examiners across 4 distinct art units requires a highly adaptable prosecution strategy. The company must address the specific technical requirements of multiple art units while also navigating the individual preferences of five different examiners. The 5 pending office actions represent a broad and varied engagement with the USPTO in the Semiconductors, Circuits & Optics sector.
Based on the USPTO statutory response window for each pending office action. 2 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §103 only | 3 (60%) |
| Multi-statute (no §101) | 2 (40%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| LOHAKARE, PRATIKSHA JAYANT | 1 | 82.3% | +15.3% |
| LASASSO, VICTOR JOSEPH | 1 | 87.0% | +0.8% |
| AUTORE JR, MARIO ANDRES | 1 | 57.8% | +31.8% |
| WHALEN, DANIEL B | 1 | 80.2% | +15.9% |
| TRAN, TIEN | 1 | 92.3% | +10.5% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 2 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18679463 | METHOD OF MANUFACTURING ISOLATION STRUCTURE | LOHAKARE, PRATIKSHA JAYANT | — |
| 18530238 | STRUCTURE HAVING MULTI-DIELECTRIC LAYERS | LASASSO, VICTOR JOSEPH | — |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 2 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18530211 | STRUCTURE HAVING MULTI-DIELECTRIC LAYERS | WHALEN, DANIEL B | 60d |
| 18530212 | METHOD OF FORMING ELECTRODE WITH MULTI-DIELECTRIC LAYERS | TRAN, TIEN | 83d |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 4 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18530211 | STRUCTURE HAVING MULTI-DIELECTRIC LAYERS | WHALEN, DANIEL B | 60d |
| 18530212 | METHOD OF FORMING ELECTRODE WITH MULTI-DIELECTRIC LAYERS | TRAN, TIEN | 83d |
| 18679463 | METHOD OF MANUFACTURING ISOLATION STRUCTURE | LOHAKARE, PRATIKSHA JAYANT | — |
| 18530237 | METHOD OF MANUFACTURING STRUCTURE HAVING ELECTRODE AND ANODIZED PART | AUTORE JR, MARIO ANDRES | — |
| Art Unit | Apps |
|---|---|
| 2898 | 1 |
| 2897 | 1 |
| 2893 | 1 |
| 2812 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 18679463 | METHOD OF MANUFACTURING ISOLATION STRUCTURE | LOHAKARE, PRATIKSHA JAYANT | — | §103 | Non-Final OA | — | Pending | May 31, 2024 |
| 18530238 | STRUCTURE HAVING MULTI-DIELECTRIC LAYERS | LASASSO, VICTOR JOSEPH | 2898 | §103 | Non-Final OA | — | Pending | Dec 06, 2023 |
| 18530237 | METHOD OF MANUFACTURING STRUCTURE HAVING ELECTRODE AND ANODIZED PART | AUTORE JR, MARIO ANDRES | 2897 | §103 | Non-Final OA | — | Pending | Dec 06, 2023 |
| 18530211 | STRUCTURE HAVING MULTI-DIELECTRIC LAYERS | WHALEN, DANIEL B | 2893 | §102§103 | Final Rejection | 60d | Pending | Dec 06, 2023 |
| 18530212 | METHOD OF FORMING ELECTRODE WITH MULTI-DIELECTRIC LAYERS | TRAN, TIEN | 2812 | §102§103 | Non-Final OA | 83d | Pending | Dec 06, 2023 |
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