DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks, filed on 05 July 2026, with respect to claims 18-20 have been fully considered and are persuasive. The 35 USC § 112 rejection of claims 18-20 has been withdrawn.
Applicant’s arguments, see Remarks, filed on 05 July 2026, with respect to the rejections of claims 1 and 11 under 35 USC § 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejection is made in view of another embodiment of Lu. Please see 35 USC § 103 rejections of claims 1 and 11 below.
Applicant’s arguments, see Remarks, filed on 05 July 2026, with respect to claim 16 have been fully considered and are persuasive. The 35 USC § 102 rejection of claim 16 has been withdrawn.
In summary, this application is not placed in a condition for an allowance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 7-11 are rejected under 35 U.S.C. 103 as being unpatentable over Lu (US 2019/0088777 A1).
Regarding claim 1, Lu teaches a laterally-diffused metal-oxide semiconductor (LDMOS) device (¶ [0018], see Figs. 20-24) comprising:
a gate structure (116) disposed over a substrate (102) and between a source region (104) and a drain region (106);
a multi-layered dielectric structure (2002 & 2004) disposed over the gate structure, wherein the multi-layered dielectric structure comprises:
a first dielectric layer (2002; ¶ [0104]: 2002 made of silicon dioxide or silicon nitride) in contact with the gate structure; and
a second dielectric layer (2004; ¶ [0106]: 2004 made of different dielectric materials 2006-2008 stacked over 2002) over the first dielectric layer, wherein a thickness (th3+th4 ; ¶ [0124]: the third thickness, th3, has thickness of 200-600 Angstroms; alternatively, see ¶ [0127] where th3 is 200-600 Angstroms thick and the fourth thickness, th4, is 50-200 Angstroms thick) of the second dielectric layer is equal to or greater than a thickness (¶ [0024], ¶ [0127]: the second thickness, th2, has thickness of 50-200 Angstroms) of the first dielectric layer; and
at least a conductive field plate (122 or alternatively, 408) over the multi-layered dielectric structure.
However, Lu Figs. 20-24 do not teach the device further comprising of an isolation disposed over a substrate, wherein the gate structure is disposed over a first portion of the isolation and wherein the first dielectric layer is in contact with a second portion of the isolation.
Lu, through another embodiment (Fig. 3), teaches an LDMOS device (300) comprising of an isolation (302) disposed over a substrate (102), wherein the gate structure (210) is disposed over a first portion (portion of 302 in direct contact with gate spacer 212, with the gate spacer being part of the gate structure 210; ¶ [0032]) of the isolation and wherein the first dielectric layer (124) is in contact with a second portion (portion of 302 in direct contact with 124) of the isolation.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of another embodiment of Lu into the device of Lu to add an isolation over a substrate wherein a portion of the isolation is under the gate and another portion of the isolation is under the first dielectric layer. The ordinary artisan would have been motivated to modify Lu in the manner set forth above for at least the purpose of improving the performance of the device at large operating voltages (¶ [0038] ).
Regarding claim 7, the LDMOS device of Claim 1, wherein the first dielectric layer has a top surface (top horizontal surface of 2002; see Figs. 20-21 and 23-24) and a sidewall (middle vertical surface of 2002), and the second dielectric layer covers the top surface and the sidewall of the first dielectric layer (Figs. 20-21 and 23-24 show 2004 covering the top horizontal surface and the vertical surface of 2002).
Regarding claim 8, the LDMOS device of Claim 1, wherein the second dielectric layer covers a first top surface (A, see Examiner Fig. 1) of the first dielectric layer, and exposes (due to 408) a second top surface (B) of the first dielectric layer.
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Examiner Fig. 1. Taken from Lu Fig. 22.
Regarding claim 9, the LDMOS device of Claim 8, wherein the first top surface and the second top surface of the first dielectric layer form a step height (Examiner Fig. 1 in claim 8 rejection shows the first top surface, A, is located at a height higher than the height of second top surface, B, with the heights of A and B measured from the top surface of substrate 102; hence A and B together form a step height).
Regarding claim 10, the LDMOS device of Claim 1, wherein a sidewall (S, see Examiner Fig. 2) of the second dielectric layer and a sidewall (sidewall of 122 directly contacting S) of the conductive field plate are aligned (since both sidewalls are directly contacting, then both above-mentioned elements are aligned to each other).
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Examiner Fig. 2. Taken from Lu Fig. 20.
Regarding claim 11, Lu teaches a method (1100, Figs. 11-19) for forming an LDMOS device (¶ [0018], see Fig. 21A), comprising: receiving a substrate (102), wherein a gate structure (116; labelled as 210 in Fig. 13) is formed over the substrate;
forming a patterned (Fig. 14 and ¶ [0086]: dielectric layers 124 are etched according to a photoresist mask) first dielectric layer (2002, with 2002 being the same dielectric layer 124 in the method figures) over the substrate and a portion (108 & 110) of the gate structure;
forming at least a silicide structure (2118, see Fig. 21A and ¶ [0116] ) over the substrate;
forming a second dielectric layer (2004) over the patterned first dielectric layer; and
forming at least a conductive field plate (112; see also Figs. 17-18 and ¶ [0092]-[0097]) over the second dielectric layer.
However, Lu does not teach the method to comprise of: forming an isolation over the substrate, wherein the gate structure covers a first portion of the isolation and wherein the first dielectric covers a second portion of the isolation.
Lu, in another embodiment (Fig. 3), teaches a method of forming an LDMOS device (300) comprising of forming an isolation (302) over the substrate (102), wherein the gate structure (210) covers a first portion (portion of 302 in direct contact with gate spacer 212; with the gate spacer being part of the gate structure 210; ¶ [0032]) of the isolation and wherein the first dielectric (124) covers a second portion (portion of 302 in direct contact with 124) of the isolation.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of another embodiment of Lu into the method of Lu to form an isolation over the substrate such that a first portion of the isolation is under the gate and a second portion of the isolation is under the first dielectric. The ordinary artisan would have been motivated to modify Lu in the manner set forth above for at least the purpose of improving the performance of the device at large operating voltages (¶ [0038] ).
Claims 1-4, 7, 10-13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kuo (US 2017/0352731 A1) in view of Lu (US 2019/0088777 A1).
Regarding claim 1, Kuo teaches a laterally-diffused metal-oxide semiconductor (LDMOS) device (Fig. 2) comprising:
a gate structure (116) disposed over a substrate (102, see also Fig. 4) and between a source region (104) and a drain region (106);
a multi-layered dielectric structure (124, see ¶ [0020]) disposed over the gate structure, wherein the multi-layered dielectric structure comprises:
a first dielectric layer (124a) in contact with the gate structure; and
a second dielectric layer (124b & 124c) over the first dielectric layer, wherein a thickness (vertical thickness of 124b & 124c) of the second dielectric layer is equal to or greater than a thickness (vertical thickness of 124a) of the first dielectric layer (Fig. 2 shows the vertical thickness of 124b & 124c is greater than that of 124a); and
at least a conductive field plate (131) over the multi-layered dielectric structure (see ¶ [0014]).
Furthermore, the difference between the thickness of the second dielectric layer and the thickness of the first dielectric layer constitutes a relative dimension. In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
However, Kuo does not teach the device further comprising of an isolation disposed over a substrate, wherein the gate structure is disposed over a first portion of the isolation and wherein the first dielectric layer is in contact with a second portion of the isolation.
Lu, in the same field of invention, teaches an LDMOS device (300; Fig. 3) comprising of an isolation (302) disposed over a substrate (102), wherein the gate structure (210) is disposed over a first portion (portion of 302 in direct contact with gate spacer 212, with the gate spacer being part of the gate structure 210; ¶ [0032]) of the isolation and wherein the first dielectric layer (124) is in contact with a second portion (portion of 302 in direct contact with 124) of the isolation.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of another embodiment of Lu into the device of Lu to add an isolation over a substrate wherein a portion of the isolation is under the gate and another portion of the isolation is under the first dielectric layer. The ordinary artisan would have been motivated to modify Lu in the manner set forth above for at least the purpose of improving the performance of the device at large operating voltages (¶ [0038] ).
Regarding claim 2, the LDMOS device of Claim 1, further comprising:
an etch stop layer (208; Kuo Fig. 2) disposed over the conductive field plate, the multi-layered dielectric structure and the drain region (Fig. 2 shows 208 above 131, 124, and 106);
an inter-layer dielectric (ILD) layer (118) disposed over the etch stop layer; and
a connecting structure (the fourth 120 from the left) coupled to the drain region.
Regarding claim 3, the LDMOS device of Claim 2, wherein the connecting structure penetrates the etch stop layer and is in contact with the drain region (Kuo Fig. 2 shows the fourth 120 from the left penetrates 208 and directly contacts 106).
Regarding claim 4, the device of claim 3, wherein a portion (left and right vertical sidewalls of 124a that abut 208; see Kuo Fig. 2) of a top surface (vertical sidewalls of 124a can be broadly interpreted as a top surface) of the first dielectric layer is in contact with the etch stop layer (208).
Regarding claim 7, the LDMOS device of Claim 1, wherein the first dielectric layer has a top surface (T, see Examiner Fig. 4; this surface extends horizontally above 108) and a sidewall (S; this surface extends vertically along the sidewalls of 108), and the second dielectric layer covers the top surface and the sidewall of the first dielectric layer (as shown in Examiner Fig. 4, T and S is covered by 124b&124c).
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Examiner Fig. 4. Taken from Kuo Fig. 4.
Regarding claim 10, the LDMOS device of Claim 1, wherein a sidewall (A1 or A2, see Examiner Fig. 4 in claim 7 rejection above) of the second dielectric layer and a sidewall (B1 or B2) of the conductive field plate are aligned (A1 and B1 both are in the same vertical plane; alternatively, A2 & B2 are both in the same vertical plane).
Regarding claim 11, Kuo teaches a method (Figs. 4-11; ¶ [0006]) for forming an LDMOS device, comprising: receiving a substrate (102, see Fig. 4), wherein a gate structure (116) is formed over the substrate;
forming a patterned (using dry etch 702 to form 124 out of 502, see Fig. 7 and ¶ [0030]) first dielectric layer (124a; Fig. 2 and ¶ [0020]: 124 composed of 124a-124c) over the substrate and a portion (Fig. 7 shows portions of 116 covered by 124) of the gate structure;
forming at least a silicide structure (142; see Fig. 8 and ¶ [0032]; also shown as the 222 formed over source 104 and drain 106 in Figs. 2) over the substrate;
forming a second dielectric layer (124b & 124c; see Fig. 2) over the patterned first dielectric layer; and
forming at least a conductive field plate (131; see Figs. 2; ¶ [0021]: field plate 131 comprises of 130 and the 222; Figs. 6 & 8 shows how 130 and 222/142 are formed) over the second dielectric layer.
However, Kuo does not teach the method to comprise of: forming an isolation over the substrate, wherein the gate structure covers a first portion of the isolation and wherein the first dielectric covers a second portion of the isolation.
Lu, in the same field of invention, teaches a method of forming an LDMOS device (300; Fig. 3) comprising of forming an isolation (302) over the substrate (102), wherein the gate structure (210) covers a first portion (portion of 302 in direct contact with gate spacer 212, with the gate spacer being part of the gate structure 210; ¶ [0032]) of the isolation and wherein the first dielectric (124) covers a second portion (portion of 302 in direct contact with 124) of the isolation.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of another embodiment of Lu into the method of Kuo to form an isolation over the substrate such that a first portion of the isolation is under the gate and a second portion of the isolation is under the first dielectric. The ordinary artisan would have been motivated to modify Kuo in the manner set forth above for at least the purpose of improving the performance of the device at large operating voltages (Lu ¶ [0038] ).
Regarding claim 12, the method of Claim 11, further comprising forming a source region (104, see Kuo Fig. 8) and a drain region (106) after the forming of the patterned first dielectric layer (124a was patterned the previous step as shown in Fig. 7).
Regarding claim 13, the method of Claim 11, further comprising forming an etch stop layer (208, see Kuo Fig. 9) and an ILD layer (118, see Fig. 10) over the substrate after the forming of the conductive field plate (131, which is made of 130 and 222/142, was formed in the previous step shown in Figs. 6-8).
Regarding claim 15, the method of Claim 13, wherein the first dielectric layer (124a, see Kuo Fig. 2) is separated from the etch stop layer (208) by the second dielectric layer (124b&124c is in between 124a and 208 along the vertical axis).
Claims 5, 6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Kuo (US 2017/0352731 A1) in view of Lu (US 2019/0088777 A1) as applied to claim 2 above, and further in view of Yu (US 2023/0187385 A1).
Regarding claim 5, Kuo et al. teach the LDMOS device of Claim 2, wherein the connecting structure penetrates the etch stop layer (Fig. 2 shows the fourth 120 from the left penetrates 208) and is in contact with the drain region (Fig. 2 shows the fourth 120 in contact with 106).
However, Kuo et al. do not teach the LDMOS device wherein the connecting structure penetrates the second dielectric layer of the multi-layered dielectric structure.
Yu, in the same field of invention, teaches an LDMOS device (Fig. 8; ¶ [0003]) wherein the connecting structure (117; note: 117 is connected to drain 109) penetrates the second dielectric layer (114: note Yu also teaches a first dielectric layer 100&112, located below 114, and with 100 &112 disposed on portions of gate 106; see also ¶ [0070]) of the multi-layered dielectric structure (Kuo in view of Yu teaches that 114 is the second dielectric layer in Kuo’s multi-layered dielectric structure).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Yu into the device of Kuo et al. to have the connecting structure penetrate the second dielectric layer of the multi-layered dielectric structure. The ordinary artisan would have been motivated to modify Kuo et al. in the manner set forth above for at least the purpose of extending the second dielectric layer of Kuo over the drain (109) and drift region (103) in order to use the second dielectric layer (114) as part of a Faraday shielding cover that is further comprised of a first metal layer (111) and a second metal layer (113) (Yu ¶ [0071]), for the further purpose of reducing interconnection resistances of the Faraday shielding covers, reducing resistance to ground of the device, etc., which improves device performance and efficiency (¶ [0072]).
Regarding claim 6, the LDMOS device of Claim 5, wherein the first dielectric layer is separated from the etch stop layer by the second dielectric layer (Kuo Fig. 2 shows 124b&124c is in between 124a and 208 along the vertical axis).
Regarding claim 14, Kuo teaches the method of Claim 13, further comprising forming a connecting structure (120, see Fig. 11) penetrating the ILD layer (118) and the etch stop layer (208). However, Kuo does not teach: the connecting structure penetrating the second dielectric layer.
Yu, in the same field of invention, teaches a method of forming an LDMOS device (Fig. 8; ¶ [0003]) wherein the connecting structure (117) penetrates the second dielectric layer (114: note Yu also teaches a first dielectric layer 100&112, located below 114, and with 100&112 disposed on portions of gate 106; see also ¶ [0070]).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Yu into the method of Kuo to have the connecting structure penetrate the second dielectric layer. The ordinary artisan would have been motivated to modify Kuo in the manner set forth above for at least the purpose of extending the second dielectric layer of Kuo over the drain (109) and a drift region (103) in order to use the second dielectric layer (114) as part of a Faraday shielding cover is further comprised of a first metal layer (111) and a second metal layer (113) (Yu ¶ [0071]), for the further purpose of reducing interconnection resistances of the Faraday shielding covers, reducing resistance to ground of the device, etc., which improves device performance and efficiency (¶ [0072]).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Lu (US 2019/0088777 A1) as applied to claim 1 above, and further in view of Lee (US 2022/0344479 A1)
Regarding claim 21, Lu teaches the LDMOS device of claim 1, but does not teach: wherein the first dielectric layer is coupled to a sidewall of the isolation.
Lee, in the same field of invention, teaches an LDMOS device (Fig. 2) wherein the first dielectric layer (610) is coupled to a sidewall (right curved sidewall of 312a) of the isolation (312).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Lee into the device of Lu to couple the first dielectric layer to a sidewall of the isolation. The ordinary artisan would have been motivated to modify Lu in the manner set forth above for at least the purpose of tapering the sidewall of the isolation layer (Lee ¶ [0082] ) in order to extend the width of the isolation (W1, see ¶ [0081] ) over the width (W2) of the field plate (700), since the width of the field plate is increased in order to improve the performance of the device (see ¶ [0096]: electric field reduction effect; ¶ [0080]: parasitic capacitance is reduced and switching speed is increased ).
Allowable Subject Matter
Claims 16 and 18-20 are allowed.
Regarding claim 16, no prior art was found to anticipate or render obvious a method for forming an LDMOS device comprising:
forming a second dielectric layer over the patterned first dielectric layer after the formation of the silicide structure, and
forming a conductive layer over the second dielectric layer.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ye et al. “Reliability Concerns on LDMOS With Different Split-STI Layout Patterns” teaches an isolation region directly below the gate. See Fig. 1.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS YAP whose telephone number is (703)756-1946. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DOUGLAS YAP/Assistant Examiner, Art Unit 2899
/JOHN M PARKER/Primary Examiner, Art Unit 2899
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