DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 15/081129, filed on 3/25/2016.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7, 9 and 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 7, 9 and 11 each recites the limitations "a first gate electrode" and “a second gate electrode” in lines 3-4 of each respective claim. There is insufficient antecedent basis for this limitation in the claim.
Claims 7, 9 and 11 each depend on one of claims 1, 4 and 5, each of which recites first and second gate electrodes.
For the purposes of compact prosecution, the Examiner has interpreted claims 7, 9 and 11 to mean:
“…[[a]] the first gate electrode…" and “…[[a]] the second gate electrode…”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4 and 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi et al. (PG Pub. No. US 2015/0069384 A1) in view of Yamazaki et al. (PG Pub. No. US 2011/0089417 A1).
Regarding claim 1, Kobayashi teaches a semiconductor device (figs. 14A, 14C) comprising a first transistor (¶ 0184: 2200) and a second transistor (¶ 0183: 550) forming an inverter (¶ 0031),
the first transistor comprising:
a first channel formation region comprising silicon (¶¶ 0185-0186: in at least one embodiment, transistor 2200 includes a silicon channel region); and
a first gate electrode above the first channel formation region (¶¶ 0185-0186 & figs. 14A, 14C: transistor 2200 includes an unlabeled gate electrode above the first channel region), and
the second transistor comprising:
a second channel formation region comprising an oxide semiconductor (¶¶ 0153, 0185 & figs. 8, 14: transistor 550 includes an oxide semiconductor channel region); and
a second gate electrode above the second channel formation region (¶¶ 0185-0187 & figs. 14A, 14C: transistor 550 includes an unlabeled gate electrode above the second channel region),
wherein a first insulator (¶ 0189: 2201) is above the first gate electrode fig. 14C: 2201 arranged above gate electrode of 2200),
wherein a second insulator (¶ 0189: 2204) is above the second gate electrode (fig. 14C: 2204 arranged above gate electrode of 550),
wherein a first conductor (¶ 0189: 2205) and a second conductor are is above the second insulator (fig. 14C: 2205 arranged above 2204),
wherein the second channel formation region is above the first insulator (fig. 14C: channel of 550 arranged above 2201),
wherein the first gate electrode is electrically connected to the second gate electrode through the first conductor (fig. 14C: gate electrode of 2200 electrically connected to gate electrode of 550 through 2205),
wherein the first conductor comprises a region in contact with a top surface of the second insulator (fig. 14C: 2205 includes a portion contacting top surface of 2204),
wherein the first insulator comprises a region in contact with a top surface of the first gate electrode (fig. 14C: 2201 comprises a region in contact with top surface of gate electrode of 2200) and an opening through which the first gate electrode and the first conductor are electrically connected to each other (fig. 14C: 2201 includes an opening through which 2205 connects gate electrodes of 2200 and 550),
wherein the opening is provided so as not to overlap with the first channel formation region (fig. 14C: opening in 2201 does not overlap channel region of 2200).
Kobayashi further teaches an electrical connection between one of a source region and a drain region of the first transistor and one of a source region and a drain region of the second transistor (fig. 14C: unlabeled electrode connects source/drain of 2200 to a source/drain of 550).
Kobayashi fails to teach the semiconductor device further comprises a second conductor above the second insulator,
wherein the second conductor comprises a region in contact with a top surface of the second insulator, the second conductor providing the electrical connection to one of the source region and the drain region of the first transistor and one of the source region and the drain region of the second transistor.
Yamazaki teaches a semiconductor device (figs. 1A-1B) including a second conductor (¶ 0047: 154b) in contact with a top surface of a second insulator (fig. 1A: 154b in contact with top surface of insulating layer 146, similar to 2204 of Kobayashi), the second conductor providing an electrical connection to a first source/drain region (¶ 0041: 120) of a first transistor (¶ 0040: 160, similar to 2200 of Kobayashi) and a second source/drain region (¶ 0043: 142a) of a second transistor (¶ 0040 & fig. 1A: 154b provides electrical connection between 120 and 142a of 162, similar to 550 of Kobayashi).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor device of Kobayashi with the second conductor of Yamazaki, as a means to adjust the arrangement and/or positioning of the first and second transistors, improving circuit density, circuit design, and/or allowing for connection to additional circuit elements above the semiconductor device.
Regarding claim 2, Kobayashi in view of Yamazaki teaches the semiconductor device according to claim 1, comprising a second channel formation region and a second gate electrode (Kobayashi, channel region and gate electrode of second transistor 550).
Kobayashi in view of Yamazaki as applied to claim 1 above does not teach the second transistor in the embodiment of figs. 14A & 14C further comprising a third gate electrode below the second channel formation region,
wherein the third gate electrode is electrically connected to the second gate electrode.
However, Kobayashi does teach the second transistor comprises an oxide semiconductor channel region (¶ 0183 & figs. 14A, 14C: 550 configured as OS device), and further teaches oxide semiconductor transistors (¶ 0120 & figs. 3A-3C: 460) including a third gate electrode (¶ 0120: 401) below an oxide semiconductor channel formation region (¶ 0052 & figs. 3B-3C: 401 arranged below oxide semiconductor layer 404),
wherein the third gate electrode is electrically connected to a second gate electrode (¶ 0120 & fig. 3C: in at least one embodiment, 401 electrically connected to second gate electrode 410).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor device of Kobayashi in view of Yamazaki with a third gate electrode below the second channel formation region and electrically connected to the second gate electrode, as a means to increase the on-state current, improving device performance (Kobayashi, ¶ 0120).
Regarding claim 3, Kobayashi in view of Yamazaki teaches the semiconductor device according to claim 2,
wherein a bottom surface of the second gate electrode comprises a region whose bottom surface is positioned below a bottom surface of the oxide semiconductor (Kobayashi, fig. 3C: at least a portion of 410 extends through insulating film 402 and below bottom surface of 404).
Regarding claim 6, Kobayashi in view of Yamazaki teaches the semiconductor device according to claim 1, wherein the oxide semiconductor comprises In, Ga, and Zn (Kobayashi, ¶¶ 0251-0253: in at least one embodiment, oxide semiconductor layer 404 of second transistor 550 includes IGZO).
Regarding claim 7, Kobayashi in view of Yamazaki teaches the semiconductor device according to claim 1, the first conductor (Kobayashi, 2205) further comprising:
a region overlapping with a third conductor (Kobayashi, 2202) configured as a first gate electrode (Kobayashi, fig. 14C: 2205 overlaps 2202, which is connected to gate electrode of 2200, and therefore meets the broadest reasonable interpretation of “a first gate electrode”); and
a region overlapping with a fourth conductor configured as a second gate electrode (Kobayashi, fig. 14C: 2205 overlaps with gate electrode of 550).
Regarding claim 4, Kobayashi teaches a semiconductor device (figs. 14A, 14C) comprising a first transistor (¶ 0184: 2200) and a second transistor (¶ 0183: 550) forming an inverter (¶ 0031),
the first transistor comprising:
a first channel formation region comprising silicon (¶¶ 0185-0186: in at least one embodiment, 2200 includes a silicon channel region); and
a first gate electrode above the first channel formation region ¶¶ 0185-0186 & figs. 14A, 14C: transistor 2200 includes an unlabeled gate electrode above the first channel region), and
the second transistor comprising:
a second channel formation region comprising an oxide semiconductor (¶¶ 0153, 0185 & figs. 8, 14: transistor 550 includes a channel region of oxide semiconductor layer 404);
a gate insulating layer over the second channel formation region (¶ 0154 & figs. 8B-8C: gate insulating film 408 disposed over channel region of 404); and
a second gate electrode over the gate insulating layer (¶¶ 0154, 0185-0187 & figs. 8B-8C, 14A, 14C: 550 includes gate electrode 410 above 408);
wherein a first insulator (¶ 0189: 2201) is above the first gate electrode (fig. 14C: 2201 arranged above gate electrode of 2220),
wherein a second insulator (¶ 0189: 2204) is above the second gate electrode (fig. 14C: 2204 arranged above gate electrode of 550),
wherein a first conductor (¶ 0189: 2205) is above the second insulator (fig. 14C: 2205 arranged above 2204),
wherein a bottom surface of the second gate electrode comprises a region whose bottom surface is positioned below a bottom surface of the oxide semiconductor (fig. 3C: at least a portion of 410 extends through insulating film 402 and below bottom surface of 404),
wherein the second channel formation region is above the first insulator (fig. 14C: channel of 550 arranged above 2201),
wherein a thickness of the gate insulating layer in a region overlapping with the second gate electrode is larger than a thickness of the gate insulating layer in a region not overlapping with the second gate electrode (figs. 3B, 9B among others: thickness of 408 not overlapping 410 tapers to 0, such that the broadest reasonable interpretation of “a thickness of the gate insulating layer in a region overlapping with the second gate electrode is larger than a thickness of the gate insulating layer in a region not overlapping with the second gate electrode” is met),
wherein the first gate electrode is electrically connected to the second gate electrode through the first conductor (fig. 14C: gate electrode of 2200 connected to gate electrode of 550 through 2205),
wherein the first conductor comprises a region in contact with a top surface of the second insulator (fig. 14C: 2205 includes a portion contacting top surface of 2204),
wherein the first insulator comprises a region in contact with a top surface of the first gate electrode (fig. 14C: 2201 comprises a region in contact with top surface of gate electrode of 2200) and an opening through which the first gate electrode and the first conductor are electrically connected to each other (fig. 14C: 2201 includes an opening through which 2205 connects the first and second gate electrodes),
wherein the opening is provided so as not to overlap with the first channel formation region (fig. 14C: opening in 2201 does not overlap channel region of 2200).
Kobayashi further teaches an electrical connection between one of a source region and a drain region of the first transistor and one of a source region and a drain region of the second transistor (fig. 14C: unlabeled electrode connects source/drain of 2200 to a source/drain of 550).
Kobayashi fails to teach the second transistor in the embodiment of figs. 14A, 14C further comprising a third gate electrode below the second channel formation region, wherein the third gate electrode is electrically connected to the second gate electrode, and
the semiconductor device further comprises a second conductor above the second insulator,
wherein the second conductor comprises a region in contact with a top surface of the second insulator, the second conductor providing the electrical connection to one of a source region and a drain region of the first transistor and one of a source region and a drain region of the second transistor.
However, Kobayashi does teach the second transistor comprises an oxide semiconductor channel region (¶ 0183 & figs. 14A, 14C: 550 configured as OS device), and further teaches oxide semiconductor transistors (¶ 0120 & figs. 3A-3C, 9A-9C: 460) including a third gate electrode (¶ 0120: 401) below an oxide semiconductor channel formation region (¶ 0052 & figs. 3B-3C: 401 arranged below oxide semiconductor layer 404),
wherein the third gate electrode is electrically connected to a second gate electrode (¶ 0120 & fig. 3C: in at least one embodiment, 401 electrically connected to second gate electrode 410).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor device of Kobayashi in view of Yamazaki with a third gate electrode below the second channel formation region and electrically connected to the second gate electrode, as a means to increase the on-state current, improving device performance (¶ 0120).
Kobayashi as modified above fails to teach the semiconductor device further comprises a second conductor above the second insulator,
wherein the second conductor comprises a region in contact with a top surface of the second insulator, the second conductor providing the electrical connection to one of a source region and a drain region of the first transistor and one of a source region and a drain region of the second transistor.
Yamazaki teaches a semiconductor device (figs. 1A-1B) including a second conductor (¶ 0047: 154b) in contact with a top surface of a second insulator (fig. 1A: 154b in contact with top surface of insulating layer 146, similar to 2204 of Kobayashi), the second conductor providing an electrical connection to a first source/drain region (¶ 0041: 120) of a first transistor (¶ 0040: 160, similar to 2200 of Kobayashi) and a second source/drain region (¶ 0043: 142a) of a second transistor (¶ 0040 & fig. 1A: 154b provides electrical connection between 120 and 142a of 162, similar to 550 of Kobayashi).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor device of Kobayashi with the second conductor of Yamazaki, as a means to adjust the arrangement and/or positioning of the first and second transistors, improving circuit density, circuit design, and/or allowing for connection to additional circuit elements arranged above the semiconductor device.
Regarding claim 8, Kobayashi in view of Yamazaki teaches the semiconductor device according to claim 4, wherein the oxide semiconductor comprises In, Ga, and Zn (Kobayashi, ¶¶ 0251-0253: in at least one embodiment, oxide semiconductor layer 404 includes IGZO).
Regarding claim 9, Kobayashi in view of Yamazaki teaches the semiconductor device according to claim 4, the first conductor (Kobayashi, 2205) further comprising:
a region overlapping with a third conductor (Kobayashi, 2202) configured as a first gate electrode (Kobayashi, fig. 14C: 2205 overlaps 2202, which is connected to gate electrode of 2200, and therefore meets the broadest reasonable interpretation of “a first gate electrode”); and
a region overlapping with a fourth conductor configured as a second gate electrode (Kobayashi, fig. 14C: 2205 overlaps with gate electrode of 550).
Claims 5 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi in view of Yamazaki and Akimoto et al. (PG Pub. No. US 2010/0136743 A1).
Regarding claim 5, Kobayashi teaches a semiconductor device (figs. 14A, 14C) comprising a first transistor (¶ 0184: 2200) and a second transistor (¶ 0183: 550) forming an inverter (¶ 0031),
the first transistor comprising:
a first channel formation region comprising silicon (¶¶ 0185-0186: in at least one embodiment, 2200 includes a silicon channel region); and
a first gate electrode above the first channel formation region ¶¶ 0185-0186 & figs. 14A, 14C: transistor 2200 includes an unlabeled gate electrode above the first channel region), and
the second transistor comprising:
a second channel formation region comprising an oxide semiconductor (¶¶ 0153, 0185 & figs. 8, 14: transistor 550 includes a channel region of oxide semiconductor layer 404); and
a second gate electrode over the second channel formation region (¶¶ 0154, 0185-0187 & figs. 8B-8C, 14A, 14C: transistor 550 includes gate electrode 410 above channel region of 404);
wherein a first insulator (¶ 0189: 2201) is above the first gate electrode (fig. 14C: 2201 arranged above gate electrode of 2220),
wherein a second insulator (¶ 0189: 2204) is above the second gate electrode (fig. 14C: 2204 arranged above gate electrode of 550),
wherein a first conductor (¶ 0189: 2205) is above the second insulator (fig. 14C: 2205 arranged above 2204),
wherein a bottom surface of the second gate electrode comprises a region whose bottom surface is positioned below a bottom surface of the oxide semiconductor (fig. 3C: at least a portion of 410 extends through insulating film 402 and below bottom surface of 404),
wherein the second channel formation region is above the first insulator (fig. 14C: channel of 550 arranged above 2201),
wherein the first gate electrode is electrically connected to the second gate electrode through the first conductor (fig. 14C: gate electrode of 2200 connected to gate electrode of 550 through 2205),
wherein the first conductor comprises a region in contact with a top surface of the second insulator (fig. 14C: 2205 includes a portion contacting top surface of 2204),
wherein the first insulator comprises a region in contact with a top surface of the first gate electrode (fig. 14C: 2201 comprises a region in contact with top surface of gate electrode of 2200) and an opening through which the first gate electrode and the first conductor are electrically connected to each other (fig. 14C: 2201 includes an opening through which 2205 connects the first and second gate electrodes),
wherein the opening is provided so as not to overlap with the first channel formation region (fig. 14C: opening in 2201 does not overlap channel region of 2200).
Kobayashi further teaches an electrical connection between one of a source region and a drain region of the first transistor and one of a source region and a drain region of the second transistor (fig. 14C: unlabeled electrode connects source/drain of 2200 to a source/drain of 550).
Kobayashi fails to teach the second transistor in the embodiment of figs. 14A, 14C further comprising a third gate electrode below the second channel formation region, wherein the third gate electrode is electrically connected to the second gate electrode, and
the semiconductor device further comprises a second conductor above the second insulator,
wherein the second conductor comprises a region in contact with a top surface of the second insulator, the second conductor providing the electrical connection to one of a source region and a drain region of the first transistor and one of a source region and a drain region of the second transistor,
wherein crystallinity of the oxide semiconductor in a region overlapping with the second gate electrode is higher than crystallinity of the oxide semiconductor in a region not overlapping with the second gate electrode.
However, Kobayashi does teach the second transistor comprises an oxide semiconductor channel region (¶ 0183 & figs. 14A, 14C: 550 configured as OS device), and further teaches oxide semiconductor transistors (¶ 0120 & figs. 3A-3C, 9A-9C: 460) including a third gate electrode (¶ 0120: 401) below an oxide semiconductor channel formation region (¶ 0052 & figs. 3B-3C: 401 arranged below oxide semiconductor layer 404),
wherein the third gate electrode is electrically connected to a second gate electrode (¶ 0120 & fig. 3C: in at least one embodiment, 401 electrically connected to second gate electrode 410).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor device of Kobayashi in view of Yamazaki with a third gate electrode below the second channel formation region and electrically connected to the second gate electrode, as a means to increase the on-state current, improving device performance (¶ 0120).
Kobayashi as modified above fails to teach the semiconductor device further comprises a second conductor above the second insulator,
wherein the second conductor comprises a region in contact with a top surface of the second insulator, the second conductor providing the electrical connection to one of a source region and a drain region of the first transistor and one of a source region and a drain region of the second transistor,
wherein crystallinity of the oxide semiconductor in a region overlapping with the second gate electrode is higher than crystallinity of the oxide semiconductor in a region not overlapping with the second gate electrode.
Yamazaki teaches a semiconductor device (figs. 1A-1B) including a second conductor (¶ 0047: 154b) in contact with a top surface of a second insulator (fig. 1A: 154b in contact with top surface of insulating layer 146, similar to 2204 of Kobayashi), the second conductor providing an electrical connection to a first source/drain region (¶ 0041: 120) of a first transistor (¶ 0040: 160, similar to 2200 of Kobayashi) and a second source/drain region (¶ 0043: 142a) of a second transistor (¶ 0040 & fig. 1A: 154b provides electrical connection between 120 and 142a of 162, similar to 550 of Kobayashi).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor device of Kobayashi with the second conductor of Yamazaki, as a means to adjust the arrangement and/or positioning of the first and second transistors, improving circuit density, circuit design, and/or allowing for connection to additional circuit elements.
Kobayashi in view of Yamazaki fails to teach wherein crystallinity of the oxide semiconductor in a region overlapping with the second gate electrode is higher than crystallinity of the oxide semiconductor in a region not overlapping with the second gate electrode.
Akimoto teaches a semiconductor device (fig. 1B among others, similar to 550 of Kobayashi) including an oxide semiconductor (¶ 0080: 106, similar to 404 of Kobayashi) and a gate electrode (¶ 0074: 103, similar to 410 of Kobayashi), wherein a crystallinity of the oxide semiconductor in a region overlapping with a gate electrode (¶ 0082 & fig. 1B: portion 107 overlaps 103) has higher crystallinity than the oxide semiconductor in a region not overlapping with the second gate electrode (¶ 0023: first oxide semiconductor region that is formed in a position which overlaps with the gate electrode has higher crystallinity than the second oxide semiconductor region).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the oxide semiconductor of Kobayashi in view of Yamazaki with the crystallinity of Akimoto, as a means to provide a channel region with good crystallinity, avoiding shrinking and bending of the substrate, and/or improving mobility characteristic of the semiconductor element (Akimoto, ¶ 0042).
Regarding claim 10, Kobayashi in view of Yamazaki and Akimoto teaches the semiconductor device according to claim 5, wherein the oxide semiconductor comprises In, Ga, and Zn (Kobayashi, ¶¶ 0251-0253: in at least one embodiment, oxide semiconductor layer 404 includes IGZO).
Regarding claim 11, Kobayashi in view of Yamazaki and Akimoto teaches the semiconductor device according to claim 5, the first conductor (Kobayashi, 2205) further comprising:
a region overlapping with a third conductor (Kobayashi, 2202) configured as a first gate electrode (Kobayashi, fig. 14C: 2205 overlaps 2202, which is connected to gate electrode of 2200, and therefore meets the broadest reasonable interpretation of “a first gate electrode”); and
a region overlapping with a fourth conductor configured as a second gate electrode (Kobayashi, fig. 14C: 2205 overlaps with gate electrode of 550).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gonzalez (PG Pub. No. US 2002/0119640 A1) teaches an inverter (fig. 8-9) including a second conductor (682) comprising a region in contact with a top surface of a second insulator (830), the second conductor electrically connected to one of a source region and a drain region of a first transistor (source/drain region 628/659 of upper transistor 610) and one of a source region and a drain region of the second transistor (source/drain 32 of bottom transistor 14).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at 571-270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BRIAN TURNER/Primary Examiner, Art Unit 2818
Prosecution Insights