DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention I, species I, corresponding to claims 1-9 and 21-31, in the reply filed on 02/03/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-9, 21-26 and 29 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “low” in claim 2 is a relative term which renders the claim indefinite. The term “low” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The limitation “low-dimensional” in the claim has been rendered indefinite by the use of the term “low”.
Claim 4 depends on claim 1. Claim 4 recites the limitation “the gate structure” in line 1. It is not clear whether the limitation refers to one of “a plurality of gate structures” in lines 3-4 of claim 1, or refers to “a gate structure” in line 12 of claim 1.
Claim 5 depends on claim 1. Claim 5 recites the limitation “the gate structure” in line 1. It is not clear whether the limitation refers to one of “a plurality of gate structures” in lines 3-4 of claim 1, or refers to “a gate structure” in line 12 of claim 1.
Claim 6 depends on claim 1. Claim 6 recites the limitation “the gate structure” in line 1. It is not clear whether the limitation refers to one of “a plurality of gate structures” in lines 3-4 of claim 1, or to “a gate structure” in line 12 of claim 1.
The term “low” in claim 21 is a relative term which renders the claim indefinite. The term “low” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The limitation “low-dimensional” in the claim has been rendered indefinite by the use of the term “low”.
Claim 26 depends on claim 21. Claim 26 recites the limitation “the gate structure” in line 1. It is not clear whether the limitation refers to one of “a plurality of gate structures” in lines 3-4 of claim 21, or refers to “a gate structure” in line 10 of claim 21.
Claim 29 depends on claim 27. Claim 29 recites the limitation “the gate structure” in line 1. It is not clear whether the limitation refers to one of “a plurality of gate structures” in line 4 of claim 27, or to “a gate structure” in line 11 of claim 27.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Manfrini (US 2022/0013712) in view of Cheng (US 2021/0083082).
Regarding claim 1, Manfrini discloses, in FIGS. 1L-1M and in related text, a semiconductor structure, comprising:
a semiconductor substrate (100);
a plurality of transistors (120) disposed on the semiconductor substrate and comprising a plurality of gate structures (128) extending lengthwise along a first direction (Y direction) (see Manfrini, [0011]);
a metallization layer (130, 140) disposed over the plurality of transistors, the metallization layer comprising a plurality of metal layers (134, 144) and a plurality of contact vias (see Manfrini, [0012]);
a dielectric layer (160) over the metallization layer (see Manfrini, [0014]);
a semiconductor layer (172) (see Manfrini, [0015]-[0016]);
a source contact and a drain contact (222, 224) disposed directly on (above) the semiconductor layer; and
a gate structure (230) disposed over the semiconductor layer and between the source contact and the drain contact (see Manfrini, [0021]-[0022]).
Manfrini does not explicitly disclose a plurality of dielectric fins extending parallel along the first direction and disposed over the dielectric layer; a semiconductor layer disposed conformally over the plurality of dielectric fins.
Cheng teaches a plurality of dielectric fins (420) extending parallel and disposed over the dielectric layer (220); a semiconductor layer (610) disposed conformally over the plurality of dielectric fins (see Cheng, FIGS. 4 and 7, [0022], [0027], [0033]).
Since Cheng teaches the dielectric layer (220) extending in the same direction as gate structure (710) (see Cheng, FIG. 7, [0038]), and Manfrini discloses the gate structure (230) extending in the first direction (Y direction) (see Manfrini, FIG. 1M), Cheng together with Manfrini teaches a plurality of dielectric fins extending parallel along the first direction.
Manfrini and Cheng are analogous art because they both are directed to transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Manfrini with the features of Cheng because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Manfrini to include a plurality of dielectric fins extending parallel along the first direction and disposed over the dielectric layer; a semiconductor layer disposed conformally over the plurality of dielectric fins, as taught by Cheng, in order to provide a finFET device having a semiconductor layer of a 2D semiconductor material (see Cheng, [0008]).
Regarding claims 2-3, Manfrini in view of Cheng teaches the structure of claim 1.
Cheng teaches wherein the semiconductor layer (610) comprises a low-dimensional (2D) semiconductor material, wherein the low-dimensional semiconductor material comprises molybdenum sulfide (MoS2), tungsten selenide (WSe2), carbon nanotubes, indium oxide, or indium gallium zinc oxide (IGZO) (see Cheng, [0033]), with the same analogous prior art and field of endeavor statement and the same motivation as provided for in claim 1.
Regarding claim 4, Manfrini in view of Cheng teaches the structure of claim 1.
Cheng teaches wherein the gate structure (710) is disposed between the source contact and the drain contact (upper layer of source/drain structure 810) along the gate direction (see Cheng, FIG. 7, [0040]-[0041]). Since Manfrini discloses the gate extending in the first direction (see discussion on claim 1 above), Cheng together with Manfrini teaches wherein the gate structure is disposed between the source contact and the drain contact along the first direction, with the same analogous prior art and field of endeavor statement and the same motivation as provided for in claim 1.
Claims 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Manfrini in view of Cheng, and further in view of Lim (US 2011/0147858).
Regarding claim 6, Manfrini in view of Cheng teaches the structure of claim 1.
Manfrini disclose wherein the gate structure comprises:
a gate dielectric layer (184) over the semiconductor layer (172); a gate electrode (230) over the gate dielectric layer (see Manfrini, FIG. 1L, [0016], [0022]).
Manfrini does not explicitly disclose an interfacial layer disposed on the semiconductor layer; a gate dielectric layer over the interfacial layer.
Lim teaches an interfacial layer (322) disposed on the semiconductor layer (302/303); a gate dielectric layer (324) over the interfacial layer (see Lim, FIGS. 3A-3B, [0018], [0022]).
Manfrini and Lim are analogous art because they both are directed to transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Manfrini with the features of Lim because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Manfrini to include an interfacial layer disposed on the semiconductor layer; a gate dielectric layer over the interfacial layer, as taught by Lim, to reduce damages between the gate dielectric layer and the semiconductor layer (see Lim, [0022]).
Regarding claim 7, Manfrini in view of Cheng and further in view of Lim teaches the structure of claim 6.
Lim teaches wherein the interfacial layer (322) comprises silicon oxide, van der Waals air gap, aluminum oxide, or titanium oxide (see Lim, [0022]), with the same analogous prior art and field of endeavor statement and the same motivation as provided for in claim 6.
Regarding claim 8, Manfrini in view of Cheng and further in view of Lim teaches the structure of claim 6.
Manfrini discloses wherein the gate dielectric layer (184) comprises hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a combination thereof (see Manfrini, [0015]-[0017]).
Regarding claim 9, Manfrini in view of Cheng and further in view of Lim teaches the structure of claim 6.
Manfrini discloses wherein the gate electrode (230) comprises titanium nitride, tantalum nitride, tungsten, ruthenium, or copper (see Manfrini, [0022]).
Claims 1 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Manfrini (US 2022/0013712) in view of van Dal (US 2021/0376084).
Regarding claim 1, Manfrini discloses, in FIGS. 1L-1M and in related text, a semiconductor structure, comprising:
a semiconductor substrate (100);
a plurality of transistors (120) disposed on the semiconductor substrate and comprising a plurality of gate structures (128) extending lengthwise along a first direction (Y direction) (see Manfrini, [0011]);
a metallization layer (130, 140) disposed over the plurality of transistors, the metallization layer comprising a plurality of metal layers (134, 144) and a plurality of contact vias (see Manfrini, [0012]);
a dielectric layer (160) over the metallization layer (see Manfrini, [0014]);
a semiconductor layer (172) (see Manfrini, [0015]-[0016]);
a source contact and a drain contact (222, 224) disposed directly on (above) the semiconductor layer; and
a gate structure (230) disposed over the semiconductor layer and between the source contact and the drain contact (see Manfrini, [0021]-[0022]).
Manfrini does not explicitly disclose a plurality of dielectric fins extending parallel along the first direction and disposed over the dielectric layer; a semiconductor layer disposed conformally over the plurality of dielectric fins.
van Dal teaches a plurality of dielectric fins (103) extending parallel and disposed over the dielectric layer (102); a semiconductor layer (104) disposed conformally over the plurality of dielectric fins (see van Dal, FIGS. 2B and 4B, [0056]-[0058]).
Since van Dal teaches that the plurality of dielectric fins and the gate structure (106) extending in the same direction (into FIG. 8C) (see van Dal, FIG. 8C, [0059], [0063]), and Manfrini discloses the gate structure (230) extending in the first direction (Y direction) (see Manfrini, FIG. 1M), van Dal together with Manfrini teaches a plurality of dielectric fins extending parallel along the first direction.
Manfrini and van Dal are analogous art because they both are directed to transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Manfrini with the features of van Dal because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Manfrini to include a plurality of dielectric fins extending parallel along the first direction and disposed over the dielectric layer; a semiconductor layer disposed conformally over the plurality of dielectric fins, as taught by van Dal, to significantly increase effective channel length (see van Dal, [0063]).
Regarding claim 5, Manfrini in view of van Dal teaches the structure of claim 5.
Manfrini discloses wherein the gate structure (230) is disposed between the source contact and the drain contact (222, 224) along a second direction (X direction) perpendicular to the first direction (Y direction) (see Manfrini, FIG. 1M).
Claims 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over Manfrini (US 2022/0013712) in view of van Dal (US 2021/0376084).
Regarding claim 21, Manfrini discloses, in FIGS. 1L-1M and in related text, a semiconductor structure, comprising:
a semiconductor substrate (100);
a plurality of transistors (120) disposed on the semiconductor substrate and comprising a plurality of gate structures (128) extending lengthwise along a first direction (Y direction) (see Manfrini, [0011]);
a first plurality of metallization layers (134, 144) over the plurality of transistors (see Manfrini, [0012]);
a low-dimensional semiconductor layer (172, including indium gallium zinc oxide) (see Manfrini, [0015]-[0016]);
a gate structure (230, 184) interfacing the low-dimensional semiconductor layer (see Manfrini, [0021]-[0022]);
a dielectric layer (200) over the gate structure and the low-dimensional semiconductor layer;
a source contact and a drain contact (222, 224) extending through the dielectric layer to couple to the low-dimensional semiconductor layer such that the gate structure is disposed between the source contact and the drain contact along a second direction (X direction) perpendicular to the first direction (see Manfrini, [0021]); and
a second plurality of metallization layers (262, 278) over the dielectric layer (see Manfrini, [0029]).
Manfrini does not explicitly disclose: a plurality of dielectric fins extending parallel along the first direction and disposed over the first plurality of metallization layers; a low-dimensional semiconductor layer extending along top surfaces and sidewalls of the plurality of dielectric fins; a gate structure disposed over a subset of the plurality of dielectric fins.
van Dal teaches a plurality of dielectric fins (103) (as part of array 95) extending parallel and disposed over the first plurality of metallization layers (41L, 42L); a low-dimensional semiconductor layer (104, including indium gallium zinc oxide) extending along top surfaces and sidewalls of the plurality of dielectric fins (see van Dal, FIGS. 1C, 2B and 4B, [0051], [0056]-[0058]); a gate structure (106) disposed over a subset of the plurality of dielectric fins (see van Dal, FIG. 8C, [0059], [0063]).
Since van Dal teaches the plurality of dielectric fins and the gate (106) extending in the same direction (into FIG. 8C), and Manfrini discloses the gate structure (230) extending in the first direction (Y direction) (see Manfrini, FIG. 1M), van Dal together with Manfrini teaches a plurality of dielectric fins extending parallel along the first direction.
Manfrini and van Dal are analogous art because they both are directed to transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Manfrini with the features of van Dal because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Manfrini to include a plurality of dielectric fins extending parallel along the first direction and disposed over the first plurality of metallization layers; a low-dimensional semiconductor layer extending along top surfaces and sidewalls of the plurality of dielectric fins; a gate structure disposed over a subset of the plurality of dielectric fins, as taught by van Dal, to significantly increase effective channel length (see van Dal, [0063]).
Regarding claim 22, Manfrini in view of van Dal teaches the structure of claim 21.
Manfrini discloses wherein the first plurality of metallization layers comprises at least 2 metallization layers (see discussion on claim 21 above).
Manfrini does not explicitly disclose between 4 and about 12 metallization layers.
However, the limitation would have been found obvious since mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See also, MPEP § 2144.04.
Regarding claim 23, Manfrini in view of van Dal teaches the structure of claim 21.
Manfrini discloses wherein the second plurality of metallization layers comprises at least 2 metallization layers (see discussion on claim 21 above).
Manfrini does not explicitly disclose between 4 and about 10 metallization layers.
However, the limitation would have been found obvious since mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See also, MPEP § 2144.04.
Regarding claim 24, Manfrini in view of van Dal teaches the structure of claim 21.
Manfrini discloses wherein the low-dimensional semiconductor layer comprises molybdenum sulfide (MoS2), tungsten selenide (WSe2), cuprous oxide (Cu2O), carbon nanotube (CNT), indium oxide (InO), or indium gallium zinc oxide (IGZO) (see discussion on claim 21 above).
Regarding claim 25, Manfrini in view of van Dal teaches the structure of claim 21.
Manfrini discloses wherein the plurality of transistors (120) comprise fin-link filed effect transistors (FinFETs) or gate-all-around (GAA) transistors (see Manfrini, [0011]).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Manfrini in view of van Dal, and further in view of Lim (US 2011/0147858).
Regarding claim 26, Manfrini in view of van Dal teaches the structure of claim 21.
Manfrini discloses wherein the gate structure (230, 184) comprises: a gate dielectric layer (184) disposed on the low-dimensional semiconductor layer (172, including indium gallium zinc oxide); a gate electrode (230) over the gate dielectric layer (see Manfrini, FIG. 1L, [0015]-[0016], [0021]-[0022]).
Manfrini does not explicitly disclose: an interfacial layer disposed on the semiconductor layer; a gate dielectric layer over the interfacial layer.
Lim teaches an interfacial layer (322) disposed on the semiconductor layer (302, 303); a gate dielectric layer (324) over the interfacial layer (see Lim, FIGS. 3A-3B, [0018], [0022]).
Manfrini and Lim are analogous art because they both are directed to transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Manfrini with the features of Lim because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Manfrini to include an interfacial layer disposed on the semiconductor layer; a gate dielectric layer over the interfacial layer, as taught by Lim, to reduce damages between the gate dielectric layer and the semiconductor layer (see Lim, [0022]).
Claims 27-28 and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Manfrini (US 2022/0013712) in view of van Dal (US 2021/0376084).
Regarding claim 27, Manfrini discloses, in FIGS. 1L-1M and in related text, a semiconductor structure, comprising:
a semiconductor substrate (100);
a plurality of transistors (120) disposed on the semiconductor substrate and comprising a plurality of gate structures (128) extending lengthwise along a first direction (Y direction) (see Manfrini, [0011]);
a first plurality of metallization layers (134, 144) over the plurality of transistors (see Manfrini, [0012]);
a dielectric spacer layer (160) over the first plurality of metallization layers (see Manfrini, [0012]);
a semiconductor layer (172) (see Manfrini, [0015]-[0016]);
a gate structure (230, 184) interfacing the semiconductor layer;
a dielectric layer (200) over the gate structure and the semiconductor layer;
a source contact and a drain contact (222, 224) extending through the dielectric layer to couple to the semiconductor layer such that the gate structure is disposed between the source contact and the drain contact along a second direction (X direction) perpendicular to the first direction (see Manfrini, [0021]); and
a second plurality of metallization layers (262, 278) over the dielectric layer (see Manfrini, [0029]),
wherein the semiconductor layer (172) comprises molybdenum sulfide (MoS2), tungsten selenide (WSe2), cuprous oxide (Cu20), carbon nanotube (CNT), indium oxide (InO), or indium gallium zinc oxide (IGZO) (see Manfrini, [0015]-[0016]).
Manfrini discloses multi-gate transistors (see Manfrini, [0011]).
Manfrini does not explicitly disclose: a plurality of dielectric fins extending parallel along the first direction and disposed over the dielectric spacer layer; a semiconductor layer extending along top surfaces and sidewalls of the plurality of dielectric fins; a gate structure disposed over a subset of the plurality of dielectric fins; where the plurality of dielectric fins are continuous with the dielectric spacer layer.
van Dal teaches a plurality of dielectric fins (103) extending parallel and disposed over the dielectric spacer layer (102); a semiconductor layer (104) extending along top surfaces and sidewalls of the plurality of dielectric fins (see van Dal, FIGS. 1C, 2B and 4B, [0056]-[0058]); a gate structure (106) disposed over a subset of the plurality of dielectric fins (see van Dal, FIG. 8C, [0059], [0063]); where the plurality of dielectric fins (103) are continuous with the dielectric spacer layer (102) (see van Dal, FIG. 2B).
Since van Dal teaches the plurality of dielectric fins and the gate structure (106) extending in the same direction (into FIG. 8C), and Manfrini discloses the gate structure (230) extending in the first direction (Y direction in FIG. 1M), van Dal together with Manfrini teaches a plurality of dielectric fins extending parallel along the first direction.
Manfrini and van Dal are analogous art because they both are directed to transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Manfrini with the features of van Dal because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Manfrini to include a plurality of dielectric fins extending parallel along the first direction and disposed over the dielectric spacer layer; a semiconductor layer extending along top surfaces and sidewalls of the plurality of dielectric fins; a gate structure disposed over a subset of the plurality of dielectric fins; where the plurality of dielectric fins are continuous with the dielectric spacer layer, as taught by van Dal, to significantly increase effective channel length (see van Dal, [0063]).
Regarding claim 28, Manfrini in view of van Dal teaches the structure of claim 27.
Manfrini discloses the dielectric spacer.
Manfrini does not explicitly disclose wherein the dielectric spacer layer comprises silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbonitride.
van Dal teaches wherein the dielectric spacer layer (102) comprises silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbonitride (see van Dal, [0056]), with at least the same analogous prior art and field of endeavor statement and the same motivation as provided for in claim 27, and because it is simple substitution of one known element for another to obtain predictable results (as dielectric layers). See also, MPEP § 2143.
Regarding claim 31, Manfrini in view of van Dal teaches the structure of claim 27.
Manfrini discloses wherein the source contact and the drain contact (222, 224) comprises beryllium (Be), nickel (Ni), platinum (Pt), gold (Au), yttrium (Y), ytterbium (Yb), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), or a combination thereof (see Manfrini, [0021])
Claims 29-30 are rejected under 35 U.S.C. 103 as being unpatentable over Manfrini in view of van Dal, and further in view of Lim (US 2011/0147858).
Regarding claim 29, Manfrini in view of van Dal teaches the structure of claim 27.
Manfrini discloses wherein the gate structure (230, 184) comprises: a gate dielectric layer (184) disposed on the semiconductor layer (172); a gate electrode (230) over the gate dielectric layer (see Manfrini, FIG. 1L, [0015]-[0016], [0021]-[0022]).
Manfrini does not explicitly disclose: an interfacial layer disposed on the semiconductor layer; a gate dielectric layer over the interfacial layer.
Lim teaches an interfacial layer (322) disposed on the semiconductor layer (302, 303); a gate dielectric layer (324) over the interfacial layer (see Lim, FIGS. 3A-3B, [0018], [0022]).
Manfrini and Lim are analogous art because they both are directed to transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Manfrini with the features of Lim because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Manfrini to include an interfacial layer disposed on the semiconductor layer; a gate dielectric layer over the interfacial layer, as taught by Lim, to reduce damages between the gate dielectric layer and the semiconductor layer (see Lim, [0022]).
Regarding claim 30, Manfrini in view of van Dal and further in view of Lim teaches the structure of claim 29.
Manfrini discloses wherein the gate dielectric layer (184) comprises hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a combination thereof (see Manfrini, [0015]-[0017]), wherein the gate electrode (230) comprises titanium nitride, tantalum nitride, tungsten, ruthenium, or copper (see Manfrini, [0022]).
Lim teaches wherein the interfacial layer (322) comprises silicon oxide, van der Waals air gap, aluminum oxide, or titanium oxide (see Lim, [0022]), with the same analogous prior art and field of endeavor statement and the same motivation as provided for in claim 29.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHIH TSUN A CHOU whose telephone number is (408)918-7583. The examiner can normally be reached M-F 8:00-16:00 Arizona Time.
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/SHIH TSUN A CHOU/Primary Examiner, Art Unit 2811