DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 07/20/2026. Claims 1-21 are pending for this examination.
Oath/Declaration
The oath or declaration filed on 12/06/2023 is acceptable.
Election/Restrictions
Applicant’s election, with traverse, of Species II (Fig 2) of claims 1-21, in the “Response to Election / Restriction Filed” filed on 07/20/2026 is acknowledged. The traversal is on the ground(s) that, search and examination of all the claims may be made without serious burden.
The species require a different field of search (e.g., searching different classes/subclasses or electronic resources or non-patent language, or deploying different search queries); and/or the prior art applicable to one species would not likely be applicable to another species; and/or the species are likely to raise different non-prior art issues under U.S.C. 101 and/or 35 U.S.C. 112, first paragraph.
Furthermore, the species require separate classification searches (i.e. (H10P50/73 or H10D30/025 or H10P14/6339 or H10B41/27 or H10B43/27 or H10B43/50 or H10P50/268 or H10P50/283 or H10P14/662 or H10P14/69215 or H10P14/69433) such as there are mutually exclusive features, as indicated in office action 04/08/2026 and these mutually exclusive features are categorized in the separate classes. Additionally, the species require different text searches. The requirement is still deemed proper and is therefore made FINAL.
This office action considers claims 1-21are thus pending for prosecution.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-7, 9-15, 17 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ogawa et al (US 2015/0243521 A1; hereafter Ogawa).
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Regarding claim 1. Ogawa discloses a method of forming a device, the method comprising:
loading a substrate (Fig. [8-9], base silicon film 310, Para [ 0095-0102]) into an etch chamber (Para [ 0095-0102]), the substrate comprising an underlayer (etching stopper film 350) and a pair of a first layer (first film 342, Para [ 0096]) and a second layer (second film 344, Para [ 0096]), the pair being stacked to form a layer stack (stack layer 320, Para [ 0096]);
forming a patterned hard mask layer (mask layer 330, Para [0096]) over the layer stack (stack layer 320, Para [0096]), the patterned hard mask layer comprising
a pattern for forming a first set of features (recess or openings in the stack layer 320, Para [0092, 0119]) and a pattern for forming a second set of features (another recess or openings in the stack layer 320, Para [0092, 0119]); and
using the patterned hard mask layer as an etch mask (mask layer 330, Para [0096]), performing a cyclic etching process ( Para [ 0014, 0093-0103]) to etch through the layer stack (stack layer 320, Para [0096]) and expose the underlayer (etching stopper film 350), each cycle of the cyclic etching process comprising a first etch step to selectively etch the first layer (first film, silicon oxide film 342, Para [ 0014, 0093-0113]) and a second etch step to selectively etch the second layer (Fig. [8-9], second film (silicon nitride film) 344, Para [ 0014, 0093-0113]), the cyclic etching process being performed for a total number of cycles (stack layer 320, includes [342/344], Para [0014, 0093-0113]) correlated to a total number of pairs in the layer stack (Fig. [8-9], Para [ 0014, 0093-0112]), and wherein the cyclic etching process forms the first set of features (recess or openings in the stack layer 320, Para [0092, 0119]) and the second set of features (another recess or openings in the stack layer 320, Para [0092, 0119]), the first set of features (152) having a different etch rate than the second set of features (Fig. [8b-8C], Para [ 0014, 0092-0113, 0124]).
Regarding claim 3. Ogawa discloses the method of claim 1, Ogawa further discloses wherein a time to complete the first etch step increases between each cycle during the cyclic etching process (Para [0080-0082, 0108-0110, 0120-0124]).
Regarding claim 4. Ogawa discloses the method of claim 1, Ogawa further discloses wherein a cycle time to complete the first etch step and the second etch step varies across each cycle during the cyclic etching process (Para [0080-0082, 0108-0110, 0120-0124]).
Regarding claim 5. Ogawa discloses the method of claim 4, Ogawa further discloses further comprising dynamically determining a cycle time to complete the first etch step and the second etch step using an end point detection process (Para [0080-0082, 0108-0110, 0120-0124]).
Regarding claim 6. Ogawa discloses the method of claim 1, Ogawa further discloses wherein a cycle time to complete the first etch step and the second etch step remains constant across each cycle during the cyclic etching process (Para [ 0122]).
Regarding claim 7. Ogawa discloses the method of claim 1, Ogawa further discloses wherein a first etch time for the first etch step is based on etching through an associated first layer (first film, silicon oxide film 342, Para [ 0014, 0093-0113]) in forming the first set of features without etching an underlying second layer (Fig. [8-9], second film (silicon nitride film) 344, Para [ 0014, 0093-0113, 0120-0124]) being exposed through the second set of features, and
wherein a second etch time for the second etch step is based on etching through an associated second layer (Fig. [8-9], second film (silicon nitride film) 344, Para [ 0014, 0093-0113, 0120-0124]) in forming the first set of features (recess or openings in the stack layer 320, Para [0092, 0119]) without etching an underlying first layer (first film, silicon oxide film 342, Para [ 0014, 0093-0113]) being exposed through the second set of features (another recess or openings in the stack layer 320, Para [0092, 0119]).
Regarding claim 9. Ogawa discloses the method of claim 1, Ogawa further discloses wherein the first layer comprises a silicon oxide layer (first film, silicon oxide film 342, Para [ 0014, 0093-0113]), the second layer comprises a silicon nitride layer (Fig. [8-9], second film (silicon nitride film) 344, Para [ 0014, 0093-0113]), and the underlayer (etching stopper film 350) comprises a semiconducting material, or a conductive material, or an etch stop layer (etching stopper film 350, Para [ 0014, 0093-0113]).
Regarding claim 10. Ogawa discloses the method of claim 1, Ogawa further discloses wherein the first layer is etched with a first etch chemistry comprising any of CHF3, CH2F2, CH3F, CF4, SF6, and NF3 that are mixed with Ar, Kr, C02, 02, N2, H2, CH4, or NO ( Para [ 0077, 0100-0101]) and the second layer is etched with a second etch chemistry comprising any of C4F6, C4Fs, C3Fs, CF4, SF6, NH3, and NF3 that are mixed with COS, CO, 02, or Ar ( Para [0077, 0100-0101]).
Regarding claim 11. Ogawa discloses a method of forming a device, the method comprising:
loading a substrate (Fig. [8-9], base silicon film 310, Para [0095-0102]) into an etch chamber (Para [0095-0102]), the substrate comprising an underlayer (etching stopper film 350);
performing a first cyclic process (Para [ 0014, 0093-0113]) to deposit a layer stack (stack layer 320, Para [0096]) comprising alternating oxide (first film 342, Para [0096]) and nitride layers (second film 342, Para [ 0096]), the first cyclic process comprising 2n cycles to form 2n alternating oxide and nitride layers, where n is an integer greater than 5 ( layers 342/344, Fig. [8-9], Para [0095-0102]);
forming a patterned hard mask layer (mask layer 330, Para [0096]) over the layer stack (stack layer 320, Para [0096]), wherein the patterned hard mask layer (mask layer 330, Para [0096]) comprises a pattern for forming a first set of high aspect ratio features (recess or openings region in the stack layer 320, Para [0092, 0119]) and a pattern for forming a second set of high aspect ratio features (another recess or openings region in the stack layer 320, Para [0092, 0119]); and
using the patterned hard mask layer as an etch mask (mask layer 330, Para [0096]), performing a second cyclic process (Para [ 0014, 0093-0113]) to etch through the 2n alternating oxide and nitride layers of the layer stack and expose the underlayer, each cycle of the second cyclic process comprising a first etch step to selectively etch the oxide layer (first film 342, Para [0096]) and a second etch step to selectively etch the nitride layer (second film 342, Para [ 0096]),
a total number of cycles in the second cyclic process being n, and wherein the second cyclic process (Para [ 0014, 0093-0113]) forms the first set of high aspect ratio features (recess or openings region in the stack layer 320, Para [0092, 0119]) and the second set of high aspect ratio features (another recess or openings region in the stack layer 320, Para [0092, 0119]), the first set of high aspect ratio features (recess or openings region in the stack layer 320, Para [0092, 0119]) having a different etch rate (Fig. [8b-8C], Para [ 0014, 0092-0113, 0124]) than the second set of high aspect ratio features (another recess or openings region in the stack layer 320, Para [0092, 0119]).
Regarding claim 12. Ogawa discloses the method of claim 11, Ogawa further discloses wherein a time to complete the first etch step increases between each cycle during the second cyclic process (Para [0080-0082, 0108-0110, 0120-0124]).
Regarding claim 13. Ogawa discloses the method of claim 11, Ogawa further discloses wherein a cycle time to complete the first etch step and the second etch step varies across each cycle during the second cyclic process (Para [0080-0082, 0108-0110, 0120-0124]).
Regarding claim 14. Ogawa discloses the method of claim 13, Ogawa further discloses further comprising dynamically determining a cycle time to complete the first etch step and the second etch step using an end point detection process (Para [0080-0082, 0108-0110, 0120-0124]).
Regarding claim 15. Ogawa discloses the method of claim 11, Ogawa further discloses wherein a cycle time to complete the first etch step and the second etch step remains constant across each cycle during the second cyclic process (Para [0080-0082, 0108-0110, 0120-0124]).
Regarding claim 17. Ogawa discloses the method of claim 11, Ogawa further discloses wherein a first etch time for the first etch step is based on etching through a associated oxide layer (first film, silicon oxide film 342, Para [ 0014, 0093-0113]) in forming the first set of high aspect ratio features without etching an underlying nitride layer (Fig. [8-9], second film (silicon nitride film) 344, Para [ 0014, 0093-0113, 0120-0124]) being exposed through the second set of high aspect ratio features and a second etch time for the second etch step is based on etching through a associated nitride layer (Fig. [8-9], second film (silicon nitride film) 344, Para [ 0014, 0093-0113, 0120-0124]) in forming the first set of high aspect ratio features (recess or openings region in the stack layer 320, Para [0092, 0119]) without etching an underlying oxide layer being exposed through the second set of high aspect ratio features (another recess or openings region in the stack layer 320, Para [0092, 0119]).
Regarding claim 19. Ogawa discloses the method of claim 11, Ogawa further discloses wherein oxide layer comprises silicon oxide (first film, silicon oxide film 342, Para [ 0014, 0093-0113]), the nitride layer comprises silicon nitride (Fig. [8-9], second film (silicon nitride film) 344, Para [ 0014, 0093-0113]), and the underlayer comprises a semiconducting material, or a conductive material, or an etch stop layer (etching stopper film 350, Para [0014, 0093-0113]).
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Ogawa et al (US 2015/0243521 A1; hereafter Ogawa) as applied claims above and further in view of Xie et al (US 2024/0381642 A1; hereafter Xie).
Regarding claim 2. Ogawa discloses the method of claim 1, But Ogawa does not disclose explicitly wherein the first set of features is a channel hole and the second set of features is a slit, the method further comprising:
filling the first set of features with a channel stack and filling the second set of features with a gate stack.
In a similar field of endeavor, Xie discloses wherein the first set of features is a channel hole (Fig 2A, region 120, Para [0041-0043]) and the second set of features is a slit (Fig 2A, region 130, Para [0041-0043]), the method further comprising:
filling the first set of features with a channel stack (Fig 2A, region 120, Para [0041-0043]) and filling the second set of features with a gate stack (Fig 2A, region 130, Para [0041-0043]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Ogawa in light of Xie teaching “wherein the first set of features is a channel hole (Fig 2A, region 120, Para [0041-0043]) and the second set of features is a slit (Fig 2A, region 130, Para [0041-0043]), the method further comprising:
filling the first set of features with a channel stack (Fig 2A, region 120, Para [0041-0043]) and filling the second set of features with a gate stack (Fig 2A, region 130, Para [0041-0043])” for further advantage such as improves the electrical connection between the channel layers.
Regarding claim 16. Ogawa discloses the method of claim 11, But Ogawa does not disclose explicitly wherein the first set of high aspect ratio features is a channel hole and the second set of high aspect ratio features is a slit, the method further comprising:
filling the first set of high aspect ratio features with a channel stack and filling the second set of high aspect ratio features with a gate stack.
In a similar field of endeavor, Xie discloses wherein the first set of high aspect ratio features is a channel hole (Fig 2A, region 120, Para [0041-0043]) and t the second set of high aspect ratio features is a slit (Fig 2A, region 130, Para [0041-0043]), the method further comprising:
filling the first set of high aspect ratio features with a channel stack (Fig 2A, region 120, Para [0041-0043]) and filling the second set of high aspect ratio features with a gate stack (Fig 2A, region 130, Para [0041-0043]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Ogawa in light of Xie teaching “wherein the first set of high aspect ratio features is a channel hole (Fig 2A, region 120, Para [0041-0043]) and t the second set of high aspect ratio features is a slit (Fig 2A, region 130, Para [0041-0043]), the method further comprising:
filling the first set of high aspect ratio features with a channel stack (Fig 2A, region 120, Para [0041-0043]) and filling the second set of high aspect ratio features with a gate stack (Fig 2A, region 130, Para [0041-0043])” for further advantage such as improves the electrical connection between the channel layers.
Claim 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Ogawa et al (US 2015/0243521 A1; hereafter Ogawa) as applied claims above and further in view of INOMATA et al (US 2024/0321740 A1; hereafter INOMATA).
Regarding claim 8. Ogawa discloses the method of claim 1, But Ogawa does not disclose explicitly wherein the first set of features have a first etch rate and the second set of features have a second etch rate, the first etch rate being at least about 10% greater than the second etch rate.
In a similar field of endeavor, INOMATA discloses wherein the first set of features have a first etch rate and the second set of features have a second etch rate, the first etch rate being at least about 10% greater than the second etch rate (Fig [1-2A], the contact via openings 29 may have a diameter in a range from 200 nm to 1,500 nm and The support openings 19 may have a diameter in a range from 60 nm to 400 nm, Para [ 0060]. Based on the via openings (19,29), first etch rate can be at least 10% greater than the second etch rate.
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Ogawa in light of INOMATA teaching “wherein the first set of features have a first etch rate and the second set of features have a second etch rate, the first etch rate being at least about 10% greater than the second etch rate (Fig [1-2A], the contact via openings 29 may have a diameter in a range from 200 nm to 1,500 nm and The support openings 19 may have a diameter in a range from 60 nm to 400 nm, Para [ 0060]. Based on the via openings (19,29), first etch rate can be at least 10% greater than the second etch rate” for further advantage such as dielectric layer stack includes layers having different etch rates, so that the whole reliability of the semiconductor structure is improved.
Regarding claim 18. Ogawa discloses the method of claim 11, But Ogawa does not disclose explicitly wherein the first set of high aspect ratio features have a first etch rate and the second set of high aspect ratio features have a second etch rate, the first etch rate being at least about 10% greater than the second etch rate.
In a similar field of endeavor, INOMATA discloses wherein the first set of high aspect ratio features have a first etch rate and the second set of high aspect ratio features have a second etch rate, the first etch rate being at least about 10% greater than the second etch rate (Fig [1-2A], the contact via openings 29 may have a diameter in a range from 200 nm to 1,500 nm and The support openings 19 may have a diameter in a range from 60 nm to 400 nm, Para [ 0060]. Based on the via openings (19,29), first etch rate can be at least 10% greater than the second etch rate.
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Ogawa in light of INOMATA teaching “wherein the first set of high aspect ratio features have a first etch rate and the second set of high aspect ratio features have a second etch rate, the first etch rate being at least about 10% greater than the second etch rate (Fig [1-2A], the contact via openings 29 may have a diameter in a range from 200 nm to 1,500 nm and The support openings 19 may have a diameter in a range from 60 nm to 400 nm, Para [ 0060]. Based on the via openings (19,29), first etch rate can be at least 10% greater than the second etch rate” for further advantage such as dielectric layer stack includes layers having different etch rates, so that the whole reliability of the semiconductor structure is improved.
Claims 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Ogawa et al (US 2015/0243521 A1; hereafter Ogawa) in view of Xie et al (US 2024/0381642 A1; hereafter Xie).
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Regarding claim 20. Ogawa discloses a method of forming a 3D NAND device, the method comprising:
having a substrate (Fig. [8-9], base silicon film 310, Para [0095-0102]) comprising an underlayer (etching stopper film 350) and a layer pair of a silicon oxide layer (first film 342, Para [0096,0102]) and a silicon nitride layer (second film 344, Para [ 0096,0102]), the pair being stacked to form a layer stack (stack layer 320, Para [0096]);
determining a total number of layer pairs in the layer stack (stack layer 320, Para [0096]), wherein the total number of layer pairs is greater than 2n, wherein n is an integer greater than 5 (stack layer 320, includes [342/344], Para [0096]);
determining a number of etch cycles for a cyclic etching process (Para [0014, 0093-0113]) based on the total number of layer pairs (stack layer 320, includes [342/344], Para [0096]);
etching a plurality of patterns and holes through the layer stack (stack layer 320, Para [0096]) using the cyclic etching process (Para [0014, 0093-0113]), the cyclic etching process being repeated for the number of etch cycles (stack layer 320, includes [342/344], Para [0014, 0093-0113]), each cycle comprising a first etching process to selectively etch the oxide layer and a second etching process to selectively etch the nitride layer (stack layer 320, includes [342/344], Para [0014, 0093-0113]).
But Ogawa does not disclose explicitly etching a plurality of gate patterns and channel holes through the layer stack and filling the plurality of gate patterns with a gate stack material and the channel holes with a channel material.
In a similar field of endeavor, Xie discloses etching a plurality of gate patterns (Fig 2A, region 130, Para [0041-0043]) and channel holes (Fig 2A, region 120, Para [0041-0043]) through the layer stack and filling the plurality of gate patterns with a gate stack material (Fig 2A, region 130, Para [0041-0043]) and the channel holes with a channel material (Fig 2A, region 120, Para [0041-0043]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Ogawa in light of Xie teaching “etching a plurality of gate patterns (Fig 2A, region 130, Para [0041-0043]) and channel holes (Fig 2A, region 120, Para [0041-0043]) through the layer stack and filling the plurality of gate patterns with a gate stack material (Fig 2A, region 130, Para [0041-0043]) and the channel holes with a channel material (Fig 2A, region 120, Para [0041-0043])” for further advantage such as improves the electrical connection between the channel layers.
Regarding claim 21. Ogawa and Xie discloses the method of claim 20, Ogawa further discloses wherein a first etch time for the first etching process is based on etching through an associated oxide layer (first film, silicon oxide film 342, Para [ 0014, 0093-0113]) in forming the plurality of patterns without etching an underlying nitride layer (Fig. [8-9], second film (silicon nitride film) 344, Para [ 0014, 0093-0113]) being exposed through the holes, and wherein a second etch time for the second etching process is based on etching through an associated nitride layer(Fig. [8-9], second film (silicon nitride film) 344, Para [ 0014, 0093-0113]) in forming the plurality of patterns without etching an underlying oxide layer being (first film, silicon oxide film 342, Para [ 0014, 0093-0113]) exposed through the holes ( Para [ 0101-0113]).
But Ogawa does not disclose explicitly gate patterns and channel holes.
In a similar field of endeavor, Xie discloses gate patterns (Fig 2A, region 130, Para [0041-0043]) and channel holes (Fig 2A, region 120, Para [0041-0043]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Ogawa in light of Xie teaching “gate patterns (Fig 2A, region 130, Para [0041-0043]) and channel holes (Fig 2A, region 120, Para [0041-0043])” for further advantage such as improves the electrical connection between the channel layers.
ALTERNATE REJECTION FOR CLAIM 1:
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xiao et al (US 2020/0098781 A1; hereafter Xiao).
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Regarding claim 1. Xiao discloses a method of forming a device, the method comprising:
loading a substrate (substrate 100) into an etch chamber (Para [ 0049-0056]), the substrate comprising an underlayer (layer 104) and a pair of a first layer (108) and a second layer (110), the pair being stacked to form a layer stack (stack layer 112);
forming a patterned hard mask layer (hard mask 114) over the layer stack (stack layer 112), the patterned hard mask layer comprising
a pattern for forming a first set of features (region 152, Para [0059]) and a pattern for forming a second set of features (region 150, Para [0059]); and
using the patterned hard mask layer as an etch mask ( hard mask 114), performing a cyclic etching process ( Para [ 0055-0059]) to etch through the layer stack (stack layer 112) and expose the underlayer (layer 104), each cycle of the cyclic etching process comprising a first etch step to selectively etch the first layer and a second etch step to selectively etch the second layer ( Para [ 0055-0056]), the cyclic etching process being performed for a total number of cycles correlated to a total number of pairs in the layer stack ( Para [ 0055-0056]), and wherein the cyclic etching process forms the first set of features (152) and the second set of features (150), the first set of features (152) having a different etch rate than the second set of features ( Fig [8-9], Para [ 0055-0059]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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