DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II (claims 9-15 and linking claims 1 and 5-8) in the reply filed on 5.12.2026 is acknowledged. Claims 1 and 5-15 are elected.
Claims 2-4 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 5.12.2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12.6.2026 is being considered by the examiner.
Claim Objections
Claims are objected to because of the following informalities:
In claim 1, insert –a-- before “semiconductor device” in the preamble.
In claims 6 and 13, insert –to-- after “connected”.
In claims 7 and 14, insert --a-- before “same”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 and 5-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Guo et al. (US 8569135 B2).
Regarding claim 1, Guo discloses (Fig. 14) a method for fabricating semiconductor device, comprising:
providing a substrate (10) having a core (no structural difference imparted by “core”, MPEP 2111, 2112 and/or 2114) region (12B) and an input/output (I/O) (no structural difference imparted by “input/output (I/O)”, MPEP 2111, 2112 and/or 2114) region (12A); and
forming a first metal gate (230B) on the core region and a second metal gate (230A) on the I/O region, wherein the first metal gate comprises a first gate dielectric layer (31B), the second metal gate comprises a second gate dielectric layer (31A+32A), and the first gate dielectric layer and the second gate dielectric layer comprise different shapes (Fig. 14).
Regarding claim 5, Guo discloses the method of claim 1, wherein the first gate dielectric layer (31B) comprises (horizontally) an I-shape (Fig. 14).
Regarding claim 6, Guo discloses the method of claim 1, wherein the second gate dielectric layer (31A+32A) comprises:
a first vertical portion and a second vertical portion (left and right sides of 32A); and
a horizontal portion (bottom of 32A and/or 31A) connected the first vertical portion and the second vertical portion (Fig. 14).
Regarding claim 7, Guo discloses the method of claim 6, wherein the first vertical portion and the second vertical portion (left and right sides of 32A) comprise same material (that of 32A, Fig. 14).
Regarding claim 8, Guo discloses the method of claim 6, wherein the first vertical portion (left or right side of 32A) and the horizontal portion (as 31A) comprise different materials (materials of 31A as “ silicon oxide or silicon nitride” vs materials of 32A as, e.g., “HFO2”).
Regarding claim 9, Guo discloses a semiconductor device (Fig. 14), comprising:
a substrate (10) having a core region (12B) and an input/output (I/O) region (12A. The terms “core” and “input/output (I/O)” do not impart a structural difference per MPEP 2111, 2112 and/or 2114) ; and
a first metal gate (230B) on the core region and a second metal gate (230A) on the I/O region, wherein the first metal gate comprises a first gate dielectric layer (31B), the second metal gate comprises a second gate dielectric layer (31A+32A), and the first gate dielectric layer and the second gate dielectric layer comprise different shapes (Fig. 14).
Regarding claim 10, Guo discloses the semiconductor device of claim 9, further comprising:
a first spacer (52B) adjacent to the first metal gate (230B) and a second spacer (52A) adjacent to the second metal gate (230A, Fig. 14); and
an interlayer dielectric (ILD) layer (60) around the first metal gate and the second metal gate (Fig. 14).
Regarding claim 11, Guo discloses the semiconductor device of claim 9, wherein the first gate dielectric layer (31B) comprises an (horizontal) I-shape (Fig. 14).
Regarding claim 12, Guo discloses the semiconductor device of claim 9, wherein the second gate dielectric layer (31A+32A) comprises a U-shape (Fig. 14).
Regarding claim 13, Guo discloses the semiconductor device of claim 9, wherein the second gate dielectric layer (31A+32A) comprises:
a first vertical portion and a second vertical portion (sides of 32A); and
a horizontal portion (bottom of 32A and/or 31A) connected the first vertical portion and the second vertical portion (Fig. 14).
Regarding claim 14, Guo discloses the semiconductor device of claim 13, wherein the first vertical portion and the second vertical portion (sides of 32A) comprise same material (of 32A).
Regarding claim 15, Guo discloses the semiconductor device of claim 13, wherein the first vertical portion (of 32A) and the horizontal portion (as 31A) comprise different materials (materials of 31A as “ silicon oxide or silicon nitride” vs materials of 32A as, e.g., “HFO2”).
Claim 1 and 5-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hou et al. (US 20150372105 A1).
Regarding claim 1, Hou discloses (Fig. 6) a method for fabricating semiconductor device, comprising:
providing a substrate (100) having a core region (102) and an input/output (I/O) (no structural difference imparted by “input/output (I/O)”, MPEP 2111, 2112 and/or 2114) region (104); and
forming a first metal gate (at least 180) on the core region and a second metal gate (at least 182) on the I/O region, wherein the first metal gate comprises a first gate dielectric layer (170), the second metal gate comprises a second gate dielectric layer (114+170), and the first gate dielectric layer and the second gate dielectric layer comprise different shapes (170 vs 114, Fig. 6).
Regarding claim 5, Hou discloses the method of claim 1, wherein the first gate dielectric layer (170) comprises (partially in a horizontal or vertical direction) an I-shape (Fig. 6).
Regarding claim 6, Hou discloses the method of claim 1, wherein the second gate dielectric layer (114+170) comprises:
a first vertical portion and a second vertical portion (left and right sides of 170); and
a horizontal portion (bottom of 170 and/or 114) connected the first vertical portion and the second vertical portion (Fig. 6).
Regarding claim 7, Hou discloses the method of claim 6, wherein the first vertical portion and the second vertical portion (left and right sides of 170) comprise same material (that of 170, Fig. 6).
Regarding claim 8, Hou discloses the method of claim 6, wherein the first vertical portion (left or right side of 170) and the horizontal portion (as 114) comprise different materials (materials of 114 as “ The oxide layer 114 is formed on the substrate 100 by high-temperature process such as in-situ silicon growth (ISSG), rapid thermal oxidation (RTO)” vs materials of 170 as, e.g., “HFO2”).
Regarding claim 9, Hou discloses a semiconductor device (Fig. 6), comprising:
a substrate (100) having a core region (102) and an input/output (I/O) region (104. The term “input/output (I/O)” does not impart a structural difference per MPEP 2111, 2112 and/or 2114); and
a first metal gate (at least 180) on the core region and a second metal gate (at least 182) on the I/O region, wherein the first metal gate comprises a first gate dielectric layer (170), the second metal gate comprises a second gate dielectric layer (114+170), and the first gate dielectric layer and the second gate dielectric layer comprise different shapes (114 vs 170, Fig. 6).
Regarding claim 10, Hou discloses the semiconductor device of claim 9, further comprising:
a first spacer (124) adjacent to the first metal gate (at least 180) and a second spacer (another 124) adjacent to the second metal gate (at least 182, Fig. 6); and
an interlayer dielectric (ILD) layer (142) around the first metal gate and the second metal gate (Fig. 6).
Regarding claim 11, Hou discloses the semiconductor device of claim 9, wherein the first gate dielectric layer (170) comprises (partially) an (horizontal or vertical) I-shape (Fig. 6).
Regarding claim 12, Hou discloses the semiconductor device of claim 9, wherein the second gate dielectric layer (114+170) comprises a U-shape (Fig. 6).
Regarding claim 13, Hou discloses the semiconductor device of claim 9, wherein the second gate dielectric layer (114+170) comprises:
a first vertical portion and a second vertical portion (sides of 170); and
a horizontal portion (bottom of 170 and/or 114) connected the first vertical portion and the second vertical portion (Fig. 6).
Regarding claim 14, Hou discloses the semiconductor device of claim 13, wherein the first vertical portion and the second vertical portion (sides of 170) comprise same material (of 170).
Regarding claim 15, Guo discloses the semiconductor device of claim 13, wherein the first vertical portion (of 170) and the horizontal portion (as 114) comprise different materials (materials of 114 as “ The oxide layer 114 is formed on the substrate 100 by high-temperature process such as in-situ silicon growth (ISSG), rapid thermal oxidation (RTO)” vs materials of 170 as, e.g., “HFO2”).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhou (US 20170133489 A1) discloses (Fig. 19) a core region (II) and a peripheral region (I) with different transistor structures.
Su et al. (US 10505007 B1) discloses (Fig. 3) a first region (102) and a second region (104) with different transistor structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
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/Andres Munoz/ Primary Examiner, Art Unit 2818
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