DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 2-4 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 5.12.2026.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 5-15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 1 and 9, “the second gate dielectric layer (identified as 40 by applicant) is a single-layer structure” allegedly finds support in Fig. 8. The examiner acknowledges that Fig. 8 shows a gate dielectric layer 40 with vertical portions 42, 44 and a horizontal portion 46, but it is noted that Fig. 3, the step in which the gate dielectric layer 40 is formed, does not support the claimed limitation of a “single-layer structure” thereby causing the claims to include new matter.
In Fig. 3 and related text, the instant application discloses that vertical portions 42,44 and horizontal portion 46 are different materials in the I/O region 16. Under this condition, the second gate dielectric is not a single-layer structure by virtue of said material difference between the vertical portions 42,44 and the horizontal portion 46. Support for the examiner’s position is found in “the oxygen gas injected during the aforementioned oxide growth process would react with inner sidewalls of the spacers 28 made of SiCN to form vertical portions 42, 44 of the gate dielectric layer 40 made of silicon oxycarbonitride (SiOCN) and at the same time react with fin-shaped structure 20 or substrate 12 surface made of silicon to form horizontal portions 46 of the gate dielectric layers 40 made of silicon oxide. In other words, after the oxygen gas injected during the oxide growth process reacts with inner sidewalls of the spacers 28 and surface of fin-shaped structure 20 or substrate 12 to form the gate dielectric layer 40, the two vertical portions 42, 44 and the horizontal portion 46 are preferably made of different materials, in which the two vertical portions 42, 44 are both made of SiOCN while the horizontal portion 46 is made of silicon oxide.” (emphasis added).
Moreover, Fig. 6 and related text discloses “oxygen gas only reacts with surface of the fin-shaped structure 20 or substrate 12, the gate dielectric layer 50 formed at this stage is preferably made of silicon oxide” wherein no change appears to take place in vertical portions 42, 44 and the horizontal portion 46 thereby remaining as different materials.
Hence, when “single-layer structure” is taken to be related to a material composition of the second gate dielectric layer, layer 40 in I/O region 16 is not a single-layer structure and the claims fail to comply with the written description requirement.
None of the dependent claims addresses this deficiency and are rejected along with base claims 1 and 9.
Claims 1 and 5-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1 and 9, “the second gate dielectric layer (identified as 40 by applicant) is a single-layer structure” renders the claims indefinite when compared with the specification (MPEP 2173.03) because it is unclear what is meant by “single-layer structure”.
In Fig. 3 and related text, the instant application discloses that vertical portions 42,44 and horizontal portion 46 are different materials and comprise different thicknesses in the I/O region 16. Under these conditions, it is unclear what a “single-layer structure” is (or isn’t) if different materials and thicknesses are part of said layer; hence the claims are indefinite.
Moreover, the layer 40 in I/O region 16 of Fig. 3 and Fig. 8 does not appear to be changed in a manner which clarifies what a “single-layer structure” is (or isn’t). Finally, the term “single-layer structure” is not used in the specification to aid in the determination of the scope of said limitation.
Hence, the claims are deemed indefinite and for purposes of examination, in accordance with Fig. 3 and claims 7-8 and 14-15, different materials and/or thicknesses will be considered to meet the term “single-layer structure”.
Support for the examiner’s position is found in “Specifically, each of the gate dielectric layers 40 formed on the core region 14 and I/O region 16 includes two vertical portions 42, 44 and a horizontal portion 46 connecting the two vertical portions 42, 44, in which the width or thickness of each of the vertical portions 42, 44 extending along horizontal direction is less than the thickness of the horizontal portion 46 extending along vertical direction” (emphasis added) and “the oxygen gas injected during the aforementioned oxide growth process would react with inner sidewalls of the spacers 28 made of SiCN to form vertical portions 42, 44 of the gate dielectric layer 40 made of silicon oxycarbonitride (SiOCN) and at the same time react with fin-shaped structure 20 or substrate 12 surface made of silicon to form horizontal portions 46 of the gate dielectric layers 40 made of silicon oxide. In other words, after the oxygen gas injected during the oxide growth process reacts with inner sidewalls of the spacers 28 and surface of fin-shaped structure 20 or substrate 12 to form the gate dielectric layer 40, the two vertical portions 42, 44 and the horizontal portion 46 are preferably made of different materials, in which the two vertical portions 42, 44 are both made of SiOCN while the horizontal portion 46 is made of silicon oxide.” (emphasis added).
None of the dependent claims addresses this deficiency and are rejected along with base claims 1 and 19.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 and 5-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Guo et al. (of record, US 8569135 B2).
Regarding claim 1, Guo discloses (Fig. 14) a method for fabricating semiconductor device, comprising:
providing a substrate (10) having a core (no structural difference imparted by “core”, MPEP 2111, 2112 and/or 2114) region (12B) and an input/output (I/O) (no structural difference imparted by “input/output (I/O)”, MPEP 2111, 2112 and/or 2114) region (12A); and
forming a first metal gate (230B) on the core region and a second metal gate (230A) on the I/O region, wherein the first metal gate comprises a first gate dielectric layer (31B), the second metal gate comprises a second gate dielectric layer (31A+32A), the second gate dielectric layer is a single-layer structure (see indefiniteness rejection above wherein different materials and/or thicknesses are taken to fall within the scope of single-layer structure) and the first gate dielectric layer and the second gate dielectric layer comprise different shapes (Fig. 14).
Regarding claim 5, Guo discloses the method of claim 1, wherein the first gate dielectric layer (31B) comprises (horizontally) an I-shape (Fig. 14).
Regarding claim 6, Guo discloses the method of claim 1, wherein the second gate dielectric layer (31A+32A) comprises:
a first vertical portion and a second vertical portion (left and right sides of 32A); and
a horizontal portion (bottom of 32A and/or 31A) connected to the first vertical portion and the second vertical portion (Fig. 14).
Regarding claim 7, Guo discloses the method of claim 6, wherein the first vertical portion and the second vertical portion (left and right sides of 32A) comprise a same material (that of 32A, Fig. 14).
Regarding claim 8, Guo discloses the method of claim 6, wherein the first vertical portion (left or right side of 32A) and the horizontal portion (as 31A) comprise different materials (materials of 31A as “ silicon oxide or silicon nitride” vs materials of 32A as, e.g., “HFO2”).
Regarding claim 9, Guo discloses a semiconductor device (Fig. 14), comprising:
a substrate (10) having a core region (12B) and an input/output (I/O) region (12A. The terms “core” and “input/output (I/O)” do not impart a structural difference per MPEP 2111, 2112 and/or 2114) ; and
a first metal gate (230B) on the core region and a second metal gate (230A) on the I/O region, wherein the first metal gate comprises a first gate dielectric layer (31B), the second metal gate comprises a second gate dielectric layer (31A+32A), the second gate dielectric layer is a single-layer structure (see indefiniteness rejection above wherein different materials and/or thicknesses are taken to fall within the scope of single-layer structure) and the first gate dielectric layer and the second gate dielectric layer comprise different shapes (Fig. 14).
Regarding claim 10, Guo discloses the semiconductor device of claim 9, further comprising:
a first spacer (52B) adjacent to the first metal gate (230B) and a second spacer (52A) adjacent to the second metal gate (230A, Fig. 14); and
an interlayer dielectric (ILD) layer (60) around the first metal gate and the second metal gate (Fig. 14).
Regarding claim 11, Guo discloses the semiconductor device of claim 9, wherein the first gate dielectric layer (31B) comprises an (horizontal) I-shape (Fig. 14).
Regarding claim 12, Guo discloses the semiconductor device of claim 9, wherein the second gate dielectric layer (31A+32A) comprises a U-shape (Fig. 14).
Regarding claim 13, Guo discloses the semiconductor device of claim 9, wherein the second gate dielectric layer (31A+32A) comprises:
a first vertical portion and a second vertical portion (sides of 32A); and
a horizontal portion (bottom of 32A and/or 31A) connected to the first vertical portion and the second vertical portion (Fig. 14).
Regarding claim 14, Guo discloses the semiconductor device of claim 13, wherein the first vertical portion and the second vertical portion (sides of 32A) comprise a same material (of 32A).
Regarding claim 15, Guo discloses the semiconductor device of claim 13, wherein the first vertical portion (of 32A) and the horizontal portion (as 31A) comprise different materials (materials of 31A as “ silicon oxide or silicon nitride” vs materials of 32A as, e.g., “HFO2”).
Claim 1 and 5-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hou et al. (of record, US 20150372105 A1).
Regarding claim 1, Hou discloses (Fig. 6) a method for fabricating semiconductor device, comprising:
providing a substrate (100) having a core region (102) and an input/output (I/O) (no structural difference imparted by “input/output (I/O)”, MPEP 2111, 2112 and/or 2114) region (104); and
forming a first metal gate (at least 180) on the core region and a second metal gate (at least 182) on the I/O region, wherein the first metal gate comprises a first gate dielectric layer (170), the second metal gate comprises a second gate dielectric layer (114+170), the second gate dielectric layer is a single-layer structure (see indefiniteness rejection above wherein different materials and/or thicknesses are taken to fall within the scope of single-layer structure) and the first gate dielectric layer and the second gate dielectric layer comprise different shapes (170 vs 114, Fig. 6).
Regarding claim 5, Hou discloses the method of claim 1, wherein the first gate dielectric layer (170) comprises (partially in a horizontal or vertical direction) an I-shape (Fig. 6).
Regarding claim 6, Hou discloses the method of claim 1, wherein the second gate dielectric layer (114+170) comprises:
a first vertical portion and a second vertical portion (left and right sides of 170); and
a horizontal portion (bottom of 170 and/or 114) connected to the first vertical portion and the second vertical portion (Fig. 6).
Regarding claim 7, Hou discloses the method of claim 6, wherein the first vertical portion and the second vertical portion (left and right sides of 170) comprise a same material (that of 170, Fig. 6).
Regarding claim 8, Hou discloses the method of claim 6, wherein the first vertical portion (left or right side of 170) and the horizontal portion (as 114) comprise different materials (materials of 114 as “ The oxide layer 114 is formed on the substrate 100 by high-temperature process such as in-situ silicon growth (ISSG), rapid thermal oxidation (RTO)” vs materials of 170 as, e.g., “HFO2”).
Regarding claim 9, Hou discloses a semiconductor device (Fig. 6), comprising:
a substrate (100) having a core region (102) and an input/output (I/O) region (104. The term “input/output (I/O)” does not impart a structural difference per MPEP 2111, 2112 and/or 2114); and
a first metal gate (at least 180) on the core region and a second metal gate (at least 182) on the I/O region, wherein the first metal gate comprises a first gate dielectric layer (170), the second metal gate comprises a second gate dielectric layer (114+170), the second gate dielectric layer is a single-layer structure (see indefiniteness rejection above wherein different materials and/or thicknesses are taken to fall within the scope of single-layer structure) and the first gate dielectric layer and the second gate dielectric layer comprise different shapes (114 vs 170, Fig. 6).
Regarding claim 10, Hou discloses the semiconductor device of claim 9, further comprising:
a first spacer (124) adjacent to the first metal gate (at least 180) and a second spacer (another 124) adjacent to the second metal gate (at least 182, Fig. 6); and
an interlayer dielectric (ILD) layer (142) around the first metal gate and the second metal gate (Fig. 6).
Regarding claim 11, Hou discloses the semiconductor device of claim 9, wherein the first gate dielectric layer (170) comprises (partially) an (horizontal or vertical) I-shape (Fig. 6).
Regarding claim 12, Hou discloses the semiconductor device of claim 9, wherein the second gate dielectric layer (114+170) comprises a U-shape (Fig. 6).
Regarding claim 13, Hou discloses the semiconductor device of claim 9, wherein the second gate dielectric layer (114+170) comprises:
a first vertical portion and a second vertical portion (sides of 170); and
a horizontal portion (bottom of 170 and/or 114) connected to the first vertical portion and the second vertical portion (Fig. 6).
Regarding claim 14, Hou discloses the semiconductor device of claim 13, wherein the first vertical portion and the second vertical portion (sides of 170) comprise a same material (of 170).
Regarding claim 15, Guo discloses the semiconductor device of claim 13, wherein the first vertical portion (of 170) and the horizontal portion (as 114) comprise different materials (materials of 114 as “ The oxide layer 114 is formed on the substrate 100 by high-temperature process such as in-situ silicon growth (ISSG), rapid thermal oxidation (RTO)” vs materials of 170 as, e.g., “HFO2”).
Claims 1, 5 and 9-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhou (of record, US 20170133489 A1).
Regarding claim 1, Zhou discloses a method for fabricating a semiconductor device (Fig. 19), comprising:
providing a substrate (400) having a core region (II) and an input/output (I/O) region (I); and
forming a first metal gate (at least 429, [0117]) on the core region (II) and a second metal gate (at least 419) on the I/O region (I), wherein the first metal gate (at least 429) comprises a first gate dielectric layer (427), the second metal gate (at least 419) comprises a second gate dielectric layer (470), the second gate dielectric layer is a single-layer structure (Fig. 19), and the first gate dielectric layer and the second gate dielectric layer comprise different shapes (Fig. 19).
Regarding claim 5, Zhou discloses the method of claim 1, wherein the first gate dielectric layer (427) comprises an (horizontal) I-shape (at a bottom thereof, Fig. 19).
Regarding claim 9, Zhou discloses a semiconductor device (Fig. 19), comprising:
a substrate (400) having a core region (II) and an input/output (I/O) region (I); and
a first metal gate (at least 429) on the core region (II) and a second metal gate (at least 419) on the I/O region (I), wherein the first metal gate (at least 429) comprises a first gate dielectric layer (427), the second metal gate (at least 419) comprises a second gate dielectric layer (470), the second gate dielectric layer is a single-layer structure (Fig. 19), and the first gate dielectric layer and the second gate dielectric layer comprise different shapes (Fig. 19).
Regarding claim 10, Zhou discloses the semiconductor device of claim 9, further comprising:
a first spacer (at least 425) adjacent to the first metal gate (at least 429) and a second spacer (at least 415) adjacent to the second metal gate (at least 419); and
an interlayer dielectric (ILD) layer (460) around the first metal gate and the second metal gate (Fig. 19).
Regarding claim 11, Zhou discloses the semiconductor device of claim 9, wherein the first gate dielectric layer (427) comprises an (horizontal) I-shape (at a bottom thereof, Fig. 19).
Response to Arguments
Applicant's arguments filed 8.27.2026 have been fully considered but they are not persuasive.
Applicant alleges Fig. 8 provides support for “the second gate electric layer (identified as 40) is a single-layer structure”. Applicant’s sole support is Fig. 8 but the examiner notes that Fig. 3 and related text recite that the second gate dielectric layer 40 comprises different materials and thicknesses which causes the claims to include new matter and be indefinite; see 35 USC 112 rejections above.
Applicant alleges the prior art of record fails to disclose or suggest “the second gate dielectric layer is a single-layer structure” because the prior art of record relies on combinations of two layers to for the second gate dielectric layer. This is not persuasive because “single-layer structure” is indefinite in view of Fig. 3 that discloses different materials and thicknesses in the second dielectric layer wherein it is unclear what is or isn’t a single-layer structure when different material and thicknesses are disclosed. For purposes of examination, “a single-layer structure” encompasses multiple materials in accordance to Fig. 3 and this is met by the prior art; see prior art rejections above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571)270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Andres Munoz/ Primary Examiner, Art Unit 2818
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