Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 11-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding claim 11, the claim recites the limitation “the plurality of gates gate” in line(s) 7-8. There is insufficient antecedent basis for this limitation in the claim because the claim 11 antecedently recites a "at least one gate”, but not "a plurality of gates". While seemingly minor, the change in terminology creates ambiguity as to whether these are the same structures. Further, the limitation includes a typographical error ‘gates gate’. For the purpose of examination, the limitation is interpreted as “the at least one gate”. Thus, the examiner recommends amending the limitation to “the at least one gate”.
Regarding claims 12-20, because of their dependency on claim 11, these claims are also rejected for the reasons set forth above with respect to claim 11.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 10-16 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang (US 20160276355).
Regarding claim 1. Fig 1 of Zhang discloses A one-time programmable (OTP) memory structure [0016], comprising:
a semiconductor substrate 103 of a first conductivity type [0026];
a fin ([0026]: Zhang discloses ‘substrate 103 is a FINFET-type structure’, and the fin region including the 115 region is defined by STI region 130) disposed on the semiconductor substrate,
wherein the fin extends along a first direction (vertical),
wherein the fin comprises a first portion (the portion below 112, which having flat top shape) and a second portion (the portion below 114, which having angled shape including flat top and slanted lateral) that is contiguous with the first portion, and
wherein the first portion and the second have different cross-sectional profiles (flat vs angled); and
a gate 102 [0027] extending over the fin along a second direction (horizontal),
wherein the gate partially overlaps with the first portion of the fin and partially overlaps with the second portion of the fin (102 across from the first portion and the second portion of the fin).
Regarding claim 2. Zhang discloses The OTP memory structure according to claim 1 further comprising:
a first gate dielectric layer 112 [0027] between the gate and the first portion of the fin; and
a second gate dielectric layer 114 [0027] between the gate and the second portion of the fin, wherein the first gate dielectric layer and the second gate dielectric have different thicknesses (Fig 1, [0027]: ‘a thick gate dielectric portion 112 and a thin gate dielectric portion 114’).
Regarding claim 3. Zhang discloses The OTP memory structure according to claim 2, wherein the first gate dielectric layer is thicker than the second gate dielectric layer (Fig 1, [0027]).
Regarding claim 4. Zhang discloses The OTP memory structure according to claim 2, wherein a step is disposed between the first gate dielectric layer and the second gate dielectric layer (Fig 1).
Regarding claim 5. Zhang discloses The OTP memory structure according to claim 2, wherein the first gate dielectric layer is an input/output (I/O) oxide layer [0027] and has a thickness of 25-45 angstroms ([0031]: 3 nm), and wherein the second dielectric layer is a core oxide layer and has a thickness of 5-25 angstroms ([0031]: 1 nm).
Regarding claim 6. Zhang discloses The OTP memory structure according to claim 1, wherein the first portion of the fin has a first top width and the second portion of the fin has a second top width, wherein the first top width is greater than the second top width (Fig 1, [0031]: the widths of each fin portions are substantially close to the widths of each thick and think gate dielectrics. Zhang further discloses the ratio of the width of thick gate dielectric portion 112 to the width of thin gate dielectric portion 114 is 2 to 1).
Regarding claim 10. Zhang discloses The OTP memory structure according to claim 1, wherein the gate is a metal gate ([0050]: metal gate stack).
Regarding claim 11. Fig 1 of Zhang discloses A one-time programmable (OTP) memory array [0016]/[0025], comprising:
a semiconductor substrate 103 of a first conductivity type [0026];
a plurality of fins ([0026]: Zhang discloses ‘substrate 103 is a FINFET-type structure’, and the fin region including the 115 region is defined by STI region 130. Furthermore, Zhang disclose memory array, thus, inherently including a plurality of fins on the substrate) disposed on the semiconductor substrate,
wherein the plurality of fins extends along a first direction (vertical),
wherein each of the plurality of fin comprises a first portion (the portion below 112, which having flat top shape) and a second portion (the portion below 114, which having angled shape including flat top and slanted lateral) that is contiguous with the first portion, and
wherein the first portion and the second have different cross-sectional profiles (flat vs angled); and
at least one gate 102 [0027] extending over the plurality of fins along a second direction (horizontal),
wherein the at least one gate (refer to above 112(b) rejection for the examiner’s interpretation) partially overlaps with the first portion and partially overlaps with the second portion (102 across from the first portion and the second portion of the fin).
Regarding claim 12. Zhang discloses The OTP memory array according to claim 11 further comprising:
a first gate dielectric layer 112 [0027] between the at least one gate and the first portion; and
a second gate dielectric layer 114 [0027] between the at least one gate and the second portion, wherein the first gate dielectric layer and the second gate dielectric have different thicknesses (Fig 1, [0027]: ‘a thick gate dielectric portion 112 and a thin gate dielectric portion 114’).
Regarding claim 13. Zhang discloses The OTP memory array according to claim 12, wherein the first gate dielectric layer is thicker than the second gate dielectric layer (Fig 1, [0027]).
Regarding claim 14. Zhang discloses The OTP memory array according to claim 12, wherein a step is disposed between the first gate dielectric layer and the second gate dielectric layer (Fig 1).
Regarding claim 15. Zhang discloses The OTP memory array according to claim 12, wherein the first gate dielectric layer is an input/output (I/O) oxide layer [0027] and has a thickness of 25-45 angstroms ([0031]: 3 nm), and wherein the second dielectric layer is a core oxide layer and has a thickness of 5-25 angstroms ([0031]: 1 nm).
Regarding claim 16. Zhang discloses The OTP memory array according to claim 11, wherein the first portion has a first top width and the second portion has a second top width, wherein the first top width is greater than the second top width (Fig 1, [0031]: the widths of each fin portions are substantially close to the widths of each thick and think gate dielectrics. Zhang further discloses the ratio of the width of thick gate dielectric portion 112 to the width of thin gate dielectric portion 114 is 2 to 1).
Regarding claim 20. Zhang discloses The OTP memory array according to claim 11, wherein the at least one gate is a metal gate ([0050]: metal gate stack).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-8 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over by Zhang (US 20160276355) in view of Chung (US 20150187431).
Regarding claim 7. Zhang discloses The OTP memory structure according to claim 1. But Zhang does not disclose wherein the first portion of the fin has the first conductivity type, and the second portion of the fin has a second conductivity type opposite to the first conductivity type.
However, Fig 6(a3) of Chung discloses the first portion 933 of the fin (931-1) has the first conductivity type (P), and the second portion 937 of the fin has a second conductivity type (N) opposite to the first conductivity type (in the abstract, Chung expressly describes one fin structure being configured to two different active regions, which aligns with longitudinally different conductivity types within the same fin, not separate fins.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Zhang’s device to have the Chung’s fin structure for the purpose of providing enhanced OTP cell with built-in rectifying properties to prevent sneak-path current, utilizing standard CMOS fabrication steps.
Regarding claim 8. Zhang in view of Chung discloses The OTP memory structure according to claim 7, Chung discloses wherein the first conductivity type is P type and the second conductivity type is N type (Fig 6(a3)).
Regarding claim 17. Zhang discloses The OTP memory array according to claim 11. But Zhang does not disclose wherein the first portion has the first conductivity type, and the second portion has a second conductivity type opposite to the first conductivity type.
However, Fig 6(a3) of Chung discloses the first portion 933 of the fin (931-1) has the first conductivity type (P), and the second portion 937 of the fin has a second conductivity type (N) opposite to the first conductivity type (in the abstract, Chung expressly describes one fin structure being configured to two different active regions, which aligns with longitudinally different conductivity types within the same fin, not separate fins.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Zhang’s device to have the Chung’s fin structure for the purpose of providing enhanced OTP cell with built-in rectifying properties to prevent sneak-path current, utilizing standard CMOS fabrication steps.
Regarding claim 18. Zhang in view of Chung discloses The OTP memory array according to claim 17, Chung discloses wherein the first conductivity type is P type and the second conductivity type is N type (Fig 6(a3)).
Claims 9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over by Zhang (US 20160276355) in view of Chang (US 20140308806).
Regarding claim 9. Zhang discloses The OTP memory structure according to claim 1. But Zhang does not disclose wherein the first portion of the fin has a rectangular-shaped cross-sectional profile, and wherein the second portion of the fin has a conical tip-shaped cross-sectional profile and a sidewall surface with at least two different slopes.
However, Fig 4C of Chang discloses the first portion (30R1) of the fin 30 has a rectangular-shaped cross-sectional profile, and wherein the second portion (30T and 30R2) of the fin has a conical tip-shaped cross-sectional profile and a sidewall surface with at least two different slopes (Chang teaches both the rectangular portion and tapered tip are formed on one continuous fin).
Thus, it would have been obvious to a person of ordinary skill in the art at the time of the invention to employ known fin shaping techniques (as taught in Chang) in an OTP memory fin (as taught in Zhang) to achieve improved electrical characteristics such as controlled field concentration and breakdown behavior. In particular, tapering the fin top to have multiple slopes in combination with an underlying rectangular base portion is a straightforward application of fin geometry known in the art.
Furthermore, it was well known in the semiconductor device art to modify fin cross section profiles to adjust device performance, leakage, and threshold behavior. Combining the fin shaping of Chang with the OTP device structures of Zhang would have been obvious because such shaping affects electric field distribution and is therefore beneficial in high field applications like OTP programming.
Regarding claim 19. Zhang discloses The OTP memory array according to claim 11. But Zhang does not disclose wherein the first portion has a rectangular-shaped cross-sectional profile, and wherein the second portion of the fin has a conical tip-shaped cross-sectional profile and a sidewall surface with at least two different slopes.
However, Fig 4C of Chang discloses the first portion (30R1) of the fin 30 has a rectangular-shaped cross-sectional profile, and wherein the second portion (30T and 30R2) of the fin has a conical tip-shaped cross-sectional profile and a sidewall surface with at least two different slopes (Chang teaches both the rectangular portion and tapered tip are formed on one continuous fin).
Thus, it would have been obvious to a person of ordinary skill in the art at the time of the invention to employ known fin shaping techniques (as taught in Chang) in an OTP memory fin (as taught in Zhang) to achieve improved electrical characteristics such as controlled field concentration and breakdown behavior. In particular, tapering the fin top to have multiple slopes in combination with an underlying rectangular base portion is a straightforward application of fin geometry known in the art.
Furthermore, it was well known in the semiconductor device art to modify fin cross section profiles to adjust device performance, leakage, and threshold behavior. Combining the fin shaping of Chang with the OTP device structures of Zhang would have been obvious because such shaping affects electric field distribution and is therefore beneficial in high field applications like OTP programming.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
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/Changhyun Yi/Primary Examiner, Art Unit 2812