Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Amendment filed on 4/13/26 has been entered.
Response to Arguments
Applicant’s arguments have been fully considered but they are moot because the arguments do not apply to any of the references being used in the current rejection.
Claim Objections
Claim 1 is objected to because of the following informalities: in line 6, the “the second” should be replaced with “the second portion”.
Claim 11 is objected to because of the following informalities: in line 7, the “the second” should be replaced with “the second portion”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 10-16 and 20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Zhang (US 20160276355) in view of Zheng (US 20170110465).
Regarding claim 1. Zhang discloses a one-time programmable (OTP) memory structure (Fig. 1; [0016]) comprising:
a semiconductor substrate 103 of a first conductivity type [0026];
a fin ([0026]: Zhang discloses “substrate 103 is a FINFET-type structure,” and fin region 115 is defined by STI region 130) disposed on the semiconductor substrate, wherein the fin extends along a first direction, and wherein the fin comprises a first portion adjacent region 112 and a second portion adjacent regions 114/115 contiguous with the first portion (Fig. 1); and
a gate 102 [0027] extending over the fin along a second direction transverse to the first direction, wherein the gate partially overlaps with the first portion of the fin and partially overlaps with the second portion of the fin.
Zhang further discloses that the first portion and the second portion have different outer profiles (see Fig. 1, substantially planar upper fin region adjacent 112 versus angled/slanted fin region adjacent 114 and 115).
But Zhang does not expressly disclose wherein the first portion and the second portion have different cross-sectional profiles taken along the second direction, as recited.
However, Figs. 1B and 1C of Zheng disclose fin structure 110 including a first portion disposed below tip portion 145 having a substantially rectangular cross-sectional profile and a second portion 145 ([0024], tip portion) contiguous with the first portion and having a tapered/angular cross-sectional profile, thereby disclosing wherein the first portion and the second portion have different cross-sectional profiles taken along the second direction. Specifically, Fig. 1C illustrates the substantially rectangular cross-sectional profile of the first portion of fin structure 110, while Fig. 1B illustrates the tapered/angular cross-sectional profile of second portion 145. Zheng further teaches that the tapered tip portion enhances electric field concentration during programming operations, thereby improving OTP programming characteristics.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the fin structure of Zhang to incorporate the differing cross-sectional profiles taught by Zheng in order to enhance electric field concentration and improve programming characteristics of the OTP memory device while maintaining compatibility with FINFET-based OTP memory structures.
Regarding claim 2. Zhang in view of Zheng discloses The OTP memory structure according to claim 1. Zhang discloses further comprising:
a first gate dielectric layer 112 [0027] between the gate and the first portion of the fin; and
a second gate dielectric layer 114 [0027] between the gate and the second portion of the fin, wherein the first gate dielectric layer and the second gate dielectric have different thicknesses (Fig 1, [0027]: ‘a thick gate dielectric portion 112 and a thin gate dielectric portion 114’).
Regarding claim 3. Zhang in view of Zheng discloses The OTP memory structure according to claim 2. Zhang discloses wherein the first gate dielectric layer is thicker than the second gate dielectric layer (Fig 1, [0027]).
Regarding claim 4. Zhang in view of Zheng discloses The OTP memory structure according to claim 2. Zhang discloses wherein a step is disposed between the first gate dielectric layer and the second gate dielectric layer (Fig 1).
Regarding claim 5. Zhang in view of Zheng discloses The OTP memory structure according to claim 2. Zhang discloses wherein the first gate dielectric layer is an input/output (I/O) oxide layer [0027] and has a thickness of 25-45 angstroms ([0031]: 3 nm), and wherein the second dielectric layer is a core oxide layer and has a thickness of 5-25 angstroms ([0031]: 1 nm).
Regarding claim 6. Zhang in view of Zheng discloses The OTP memory structure according to claim 1. Zhang discloses wherein the first portion of the fin has a first top width and the second portion of the fin has a second top width, wherein the first top width is greater than the second top width (Fig 1, [0031]: the widths of each fin portions are substantially close to the widths of each thick and think gate dielectrics. Zhang further discloses the ratio of the width of thick gate dielectric portion 112 to the width of thin gate dielectric portion 114 is 2 to 1).
Regarding claim 10. Zhang in view of Zheng discloses The OTP memory structure according to claim 1. Zhang discloses wherein the gate is a metal gate ([0050]: metal gate stack).
Regarding claim 11. Zhang discloses a one-time programmable (OTP) memory array (Fig. 1; [0016], [0025]) comprising:
a semiconductor substrate 103 of a first conductivity type [0026];
a plurality of fins disposed on the semiconductor substrate ([0026], substrate 103 is a FINFET-type structure and fin region 115 is defined by STI region 130), wherein the plurality of fins extends along a first direction, and wherein each of the plurality of fins comprises a first portion adjacent region 112 and a second portion adjacent regions 114/115 contiguous with the first portion (Fig. 1). Zhang further discloses a memory array structure, which would have been understood by one of ordinary skill in the art to include a plurality of fins disposed on the substrate; and
at least one gate 102 ([0027]) extending over the plurality of fins along a second direction transverse to the first direction, wherein the at least one gate partially overlaps with the first portion and partially overlaps with the second portion of each fin.
Zhang further discloses that the first portion and the second portion have different outer profiles (see Fig. 1, substantially planar upper fin region adjacent 112 versus angled/slanted fin region adjacent 114 and 115).
But Zhang does not expressly disclose wherein the first portion and the second portion have different cross-sectional profiles taken along the second direction, as recited.
However, Figs. 1B and 1C of Zheng disclose fin structure 110 including a first portion disposed below tip portion 145 having a substantially rectangular cross-sectional profile and a second portion 145 ([0024], tip portion) contiguous with the first portion and having a tapered/angular cross-sectional profile, thereby disclosing wherein the first portion and the second portion have different cross-sectional profiles taken along the second direction. Specifically, Fig. 1C illustrates the substantially rectangular cross-sectional profile of the first portion of fin structure 110, while Fig. 1B illustrates the tapered/angular cross-sectional profile of second portion 145. Zheng further teaches that the tapered tip portion enhances electric field concentration during programming operations, thereby improving OTP programming characteristics.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the fin structure of Zhang to incorporate the differing cross-sectional profiles taught by Zheng in order to enhance electric field concentration and improve programming characteristics of the OTP memory array while maintaining compatibility with FINFET-based OTP memory structures.
Regarding claim 12. Zhang in view of Zheng discloses The OTP memory structure according to claim 11. Zhang discloses further comprising:
a first gate dielectric layer 112 [0027] between the at least one gate and the first portion; and
a second gate dielectric layer 114 [0027] between the at least one gate and the second portion, wherein the first gate dielectric layer and the second gate dielectric have different thicknesses (Fig 1, [0027]: ‘a thick gate dielectric portion 112 and a thin gate dielectric portion 114’).
Regarding claim 13. Zhang in view of Zheng discloses The OTP memory structure according to claim 12. Zhang discloses wherein the first gate dielectric layer is thicker than the second gate dielectric layer (Fig 1, [0027]).
Regarding claim 14. Zhang in view of Zheng discloses The OTP memory structure according to claim 12. Zhang discloses wherein a step is disposed between the first gate dielectric layer and the second gate dielectric layer (Fig 1).
Regarding claim 15. Zhang in view of Zheng discloses The OTP memory structure according to claim 12. Zhang discloses wherein the first gate dielectric layer is an input/output (I/O) oxide layer [0027] and has a thickness of 25-45 angstroms ([0031]: 3 nm), and wherein the second dielectric layer is a core oxide layer and has a thickness of 5-25 angstroms ([0031]: 1 nm).
Regarding claim 16. Zhang in view of Zheng discloses The OTP memory structure according to claim 11. Zhang discloses wherein the first portion has a first top width and the second portion has a second top width, wherein the first top width is greater than the second top width (Fig 1, [0031]: the widths of each fin portions are substantially close to the widths of each thick and think gate dielectrics. Zhang further discloses the ratio of the width of thick gate dielectric portion 112 to the width of thin gate dielectric portion 114 is 2 to 1).
Regarding claim 20. Zhang in view of Zheng discloses The OTP memory structure according to claim 11. Zhang discloses wherein the at least one gate is a metal gate ([0050]: metal gate stack).
Claims 7-8 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over by Zhang (US 20160276355) in view of Zheng (US 20170110465), and further in view of Chung (US 20150187431).
Regarding claim 7. Zhang in view of Zheng discloses The OTP memory structure according to claim 1. But Zhang in view of Zheng does not disclose wherein the first portion of the fin has the first conductivity type, and the second portion of the fin has a second conductivity type opposite to the first conductivity type.
However, Fig 6(a3) of Chung discloses the first portion 933 of the fin (931-1) has the first conductivity type (P), and the second portion 937 of the fin has a second conductivity type (N) opposite to the first conductivity type (in the abstract, Chung expressly describes one fin structure being configured to two different active regions, which aligns with longitudinally different conductivity types within the same fin, not separate fins.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Zhang in view of Zheng’s device to have the Chung’s fin structure for the purpose of providing enhanced OTP cell with built-in rectifying properties to prevent sneak-path current, utilizing standard CMOS fabrication steps.
Regarding claim 8. Zhang in view of Zheng and Chung discloses The OTP memory structure according to claim 7, Chung discloses wherein the first conductivity type is P type and the second conductivity type is N type (Fig 6(a3)).
Regarding claim 17. Zhang in view of Zheng discloses The OTP memory array according to claim 11. But Zhang in view of Zheng does not disclose wherein the first portion has the first conductivity type, and the second portion has a second conductivity type opposite to the first conductivity type.
However, Fig 6(a3) of Chung discloses the first portion 933 of the fin (931-1) has the first conductivity type (P), and the second portion 937 of the fin has a second conductivity type (N) opposite to the first conductivity type (in the abstract, Chung expressly describes one fin structure being configured to two different active regions, which aligns with longitudinally different conductivity types within the same fin, not separate fins.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Zhang in view of Zheng’s device to have the Chung’s fin structure for the purpose of providing enhanced OTP cell with built-in rectifying properties to prevent sneak-path current, utilizing standard CMOS fabrication steps.
Regarding claim 18. Zhang in view of Zheng and Chung discloses The OTP memory array according to claim 17, Chung discloses wherein the first conductivity type is P type and the second conductivity type is N type (Fig 6(a3)).
Claims 9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 20160276355) in view of Zheng (US 20170110465), and further in view of Chang (US 20140308806).
Regarding claim 9, Zhang in view of Zheng discloses the OTP memory structure according to claim 1. But Zhang in view of Zheng does not expressly disclose wherein the first portion has a rectangular-shaped cross-sectional profile taken along the second direction, and wherein the second portion of the fin has a conical tip-shaped cross-sectional profile taken along the second direction and a sidewall surface with at least two different slopes.
However, Chang discloses this limitation. In particular, Fig. 4C of Chang discloses continuous fin structure 30 including a first portion 30R1 having a substantially rectangular-shaped cross-sectional profile and a second portion 30T/30R2 having a tapered/conical tip-shaped cross-sectional profile with sidewall surfaces having at least two different slopes. Chang further teaches that the rectangular portion and tapered tip portion are formed on a continuous fin structure.
Zheng further discloses differing cross-sectional profiles taken along the second direction, as discussed above with respect to claim 1. Specifically, Figs. 1B and 1C of Zheng disclose cross-sectional profiles of different portions of fin structure 110 taken along the second direction.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the fin structure of Zhang, as modified by Zheng, to incorporate the fin shaping techniques taught by Chang in order to improve electric field concentration, programming characteristics, and breakdown behavior in the OTP memory device. In particular, providing a tapered fin tip with multiple sidewall slopes above a rectangular fin base would have been a predictable use of known fin geometry optimization techniques for controlling electric field distribution in semiconductor memory structures while maintaining compatibility with FINFET-based OTP memory structures.
Regarding claim 19, Zhang in view of Zheng discloses the OTP memory array according to claim 11. But Zhang in view of Zheng does not expressly disclose wherein the first portion has a rectangular-shaped cross-sectional profile taken along the second direction, and wherein the second portion of the fin has a conical tip-shaped cross-sectional profile taken along the second direction and a sidewall surface with at least two different slopes.
However, Chang discloses this limitation. In particular, Fig. 4C of Chang discloses continuous fin structure 30 including a first portion 30R1 having a substantially rectangular-shaped cross-sectional profile and a second portion 30T/30R2 having a tapered/conical tip-shaped cross-sectional profile with sidewall surfaces having at least two different slopes. Chang further teaches that the rectangular portion and tapered tip portion are formed on a continuous fin structure.
Zheng further discloses differing cross-sectional profiles taken along the second direction, as discussed above with respect to claim 11. Specifically, Figs. 1B and 1C of Zheng disclose cross-sectional profiles of different portions of fin structure 110 taken along the second direction.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the fin structure of Zhang, as modified by Zheng, to incorporate the fin shaping techniques taught by Chang in order to improve electric field concentration, programming characteristics, and breakdown behavior in the OTP memory array.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Changhyun Yi/Primary Examiner, Art Unit 2812
Prosecution Insights